A new Boolean resubstitution technique with permissible functions and ordered binary decision diagrams (OBDDs) is presented. Boolean resubstitution is one technique for multilevel logic optimization. Permissible functions are special don't care sets. The data structure, of permissible functions and logic functions at each node in Boolean networks is represented in terms of OBDD. Therefore, logic functions can be flexibly manipulated and rapidly executed. Boolean resubstitution was also applied to a multilevel logic synthesis. Results of experiments employing the improved OBDD operation and Boolean resubstitution techniques are presented.<>
{"title":"Boolean resubstitution with permissible functions and binary decision diagrams","authors":"H. Sato, Y. Yasue, Y. Matsunaga, M. Fujita","doi":"10.1109/DAC.1990.114868","DOIUrl":"https://doi.org/10.1109/DAC.1990.114868","url":null,"abstract":"A new Boolean resubstitution technique with permissible functions and ordered binary decision diagrams (OBDDs) is presented. Boolean resubstitution is one technique for multilevel logic optimization. Permissible functions are special don't care sets. The data structure, of permissible functions and logic functions at each node in Boolean networks is represented in terms of OBDD. Therefore, logic functions can be flexibly manipulated and rapidly executed. Boolean resubstitution was also applied to a multilevel logic synthesis. Results of experiments employing the improved OBDD operation and Boolean resubstitution techniques are presented.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131758864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A set of novel tradeoff experiments using MABAL, a module and bus allocation program, is described. MABAL uses a simple heuristic algorithm to concurrently perform functional unit allocation, register allocation, interconnect allocation, and module binding, while minimizing overall cost. MABAL was used to produce over 3000-RTL (register transfer level) designs from a specification which had been previously scheduled. Tradeoffs between buses and multiplexers and between data steering logic and functional logic were investigated. The results indicate that data path tradeoffs were sensitive to the characteristics of the module library used, and illustrate the difficulty of integrating module generations or logic synthesis, with high-level synthesis.<>
{"title":"Data path tradeoffs using MABAL","authors":"Kayhan Küçükçakar, A. C. Parker","doi":"10.1109/DAC.1990.114909","DOIUrl":"https://doi.org/10.1109/DAC.1990.114909","url":null,"abstract":"A set of novel tradeoff experiments using MABAL, a module and bus allocation program, is described. MABAL uses a simple heuristic algorithm to concurrently perform functional unit allocation, register allocation, interconnect allocation, and module binding, while minimizing overall cost. MABAL was used to produce over 3000-RTL (register transfer level) designs from a specification which had been previously scheduled. Tradeoffs between buses and multiplexers and between data steering logic and functional logic were investigated. The results indicate that data path tradeoffs were sensitive to the characteristics of the module library used, and illustrate the difficulty of integrating module generations or logic synthesis, with high-level synthesis.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129200168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An adaptive timing-driven VLSI layout system, called JUNE, has been developed. The constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. The placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. Experimental results for industrial sea-of-gates chips confirmed the effectiveness of this approach.<>
{"title":"An adaptive timing-driven layout for high speed VLSI","authors":"S. Sutanthavibul, E. Shragowitz","doi":"10.1109/DAC.1990.114835","DOIUrl":"https://doi.org/10.1109/DAC.1990.114835","url":null,"abstract":"An adaptive timing-driven VLSI layout system, called JUNE, has been developed. The constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. The placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. Experimental results for industrial sea-of-gates chips confirmed the effectiveness of this approach.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123071416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design data management system is a crucial component in an IC CAD framework environment as the design involves a large volume of data in diversified formats. The authors identify requirements for such a system and present the approach that a design framework utilizes to support these requirements. Several aspects, including a library model, version control, configuration management, access control, and history tracking, are explored. and feasible solutions are proposed. The system is currently under developed and will be released in the next generation of the Cadence design framework.<>
{"title":"Design data management in a CAD framework environment","authors":"Lung-Chun Liu","doi":"10.1109/DAC.1990.114847","DOIUrl":"https://doi.org/10.1109/DAC.1990.114847","url":null,"abstract":"The design data management system is a crucial component in an IC CAD framework environment as the design involves a large volume of data in diversified formats. The authors identify requirements for such a system and present the approach that a design framework utilizes to support these requirements. Several aspects, including a library model, version control, configuration management, access control, and history tracking, are explored. and feasible solutions are proposed. The system is currently under developed and will be released in the next generation of the Cadence design framework.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123330897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A program that performs automatic placement of integrated circuit layouts is described. The macro block placement program (MBP) places widely ranging mixes of macro blocks and standard cells into slicing layouts. It uses a minimum net-cut criteria to partition standard cells into flexible virtual blocks before block placement. Blocks are then placed using a simulated annealing optimization. The block placement algorithm evaluates placements based on both routing area costs and net costs. An adaptive move selection algorithm maximizes the annealing performance. A simple annealing-based optimization of the standard cell partitions completes the process.<>
{"title":"Integrated placement for mixed macro cell and standard cell designs","authors":"M. Upton, K. Samii, S. Sugiyama","doi":"10.1145/123186.123219","DOIUrl":"https://doi.org/10.1145/123186.123219","url":null,"abstract":"A program that performs automatic placement of integrated circuit layouts is described. The macro block placement program (MBP) places widely ranging mixes of macro blocks and standard cells into slicing layouts. It uses a minimum net-cut criteria to partition standard cells into flexible virtual blocks before block placement. Blocks are then placed using a simulated annealing optimization. The block placement algorithm evaluates placements based on both routing area costs and net costs. An adaptive move selection algorithm maximizes the annealing performance. A simple annealing-based optimization of the standard cell partitions completes the process.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126280477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new methodology is presented for the solution of a multi-layer routing problem that has the potential to outperform channel-based multi-layer routing algorithms by expanding the routing regions to include areas over the cells. It is assumed that four routing layers are available. Routing is completed in two steps. A selected group of nets is routed in the between-cell areas using existing channel-routing algorithms and the first two routing layers. Then the remaining nets are routed over the entire layout area, between-cell and over-cell areas, using a new two-dimensional router and the next two routing layers. The router used for over-cell routing recognizes arbitrarily sized obstacles, for example, due to power and ground routing or sensitive circuits in the underlying cells. The proposed router was tested on a number of macro-cell layout examples.<>
{"title":"A multi-layer router utilizing over-cell areas","authors":"E. Katsadas, E. Kinnen","doi":"10.1145/123186.123446","DOIUrl":"https://doi.org/10.1145/123186.123446","url":null,"abstract":"A new methodology is presented for the solution of a multi-layer routing problem that has the potential to outperform channel-based multi-layer routing algorithms by expanding the routing regions to include areas over the cells. It is assumed that four routing layers are available. Routing is completed in two steps. A selected group of nets is routed in the between-cell areas using existing channel-routing algorithms and the first two routing layers. Then the remaining nets are routed over the entire layout area, between-cell and over-cell areas, using a new two-dimensional router and the next two routing layers. The router used for over-cell routing recognizes arbitrarily sized obstacles, for example, due to power and ground routing or sensitive circuits in the underlying cells. The proposed router was tested on a number of macro-cell layout examples.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125748390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Application of corolla-based partitioning to improve synthesis of large multi-level logic circuits is introduced. First, stem regions, petals, and corollas are defined. Next, the partitioning algorithm is outlined and the resynthesis process is described. Results of partitioning and logic resynthesis on a variety of large circuit benchmarks are summarized. It is found that logic resynthesis based on corolla partitioning consistently reduces reconvergent fanout branches, transistor pairs and layout areas, while improving circuit delay and testability.<>
{"title":"Corolla based circuit partitioning and resynthesis","authors":"S. Dey, F. Brglez, G. Kedem","doi":"10.1109/DAC.1990.114926","DOIUrl":"https://doi.org/10.1109/DAC.1990.114926","url":null,"abstract":"Application of corolla-based partitioning to improve synthesis of large multi-level logic circuits is introduced. First, stem regions, petals, and corollas are defined. Next, the partitioning algorithm is outlined and the resynthesis process is described. Results of partitioning and logic resynthesis on a variety of large circuit benchmarks are summarized. It is found that logic resynthesis based on corolla partitioning consistently reduces reconvergent fanout branches, transistor pairs and layout areas, while improving circuit delay and testability.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129932881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<>
{"title":"Layout synthesis of MOS digital cells","authors":"A. Domic","doi":"10.1109/DAC.1990.114861","DOIUrl":"https://doi.org/10.1109/DAC.1990.114861","url":null,"abstract":"The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132695175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A unified framework and associated algorithms are presented. This framework allows for a uniform treatment of arbitrary decomposition topologies operating at the state transition graph (STG) level, while targeting a cost function that is close to the eventual logic implementation. Previous work has targeted specific decomposition topologies via the formulation of decomposition as implicant covering with associated constraints. It is shown that this formulation can be used to target arbitrary desired topologies merely by customizing the constraints during implicant covering. It is also shown how this work relates to preserved partitions and covers traditionally used in parallel and cascade decompositions, and how this formulation establishes the relationship between state assignment and a finite state machine decomposition. Memory and CPU-time-efficient re-decomposition algorithms that operate on distributed-style specifications and which are more global than those presented in the past have been developed. These algorithms are implemented in the sequential logic synthesis system, FLAMES, that is being developed at UCB/MIT.<>
{"title":"A unified approach to the decomposition and re-decomposition of sequential machines","authors":"P. Ashar, S. Devadas, A. Newton","doi":"10.1109/DAC.1990.114925","DOIUrl":"https://doi.org/10.1109/DAC.1990.114925","url":null,"abstract":"A unified framework and associated algorithms are presented. This framework allows for a uniform treatment of arbitrary decomposition topologies operating at the state transition graph (STG) level, while targeting a cost function that is close to the eventual logic implementation. Previous work has targeted specific decomposition topologies via the formulation of decomposition as implicant covering with associated constraints. It is shown that this formulation can be used to target arbitrary desired topologies merely by customizing the constraints during implicant covering. It is also shown how this work relates to preserved partitions and covers traditionally used in parallel and cascade decompositions, and how this formulation establishes the relationship between state assignment and a finite state machine decomposition. Memory and CPU-time-efficient re-decomposition algorithms that operate on distributed-style specifications and which are more global than those presented in the past have been developed. These algorithms are implemented in the sequential logic synthesis system, FLAMES, that is being developed at UCB/MIT.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114839263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Described is a class of parallel algorithms for circuit simulation based on hierarchical relaxation that has been implemented on the Cedar multiprocessor. The Cedar machine is a reconfigurable, general-purpose supercomputer that was designed and implemented at the University of Illinois. A hierarchical circuit simulation scheme is developed to exploit the hierarchical organization of Cedar. The new algorithm and a number of key issues, such as multilevel circuit partitioning, data partitioning, cluster algorithm selection, and cluster algorithm implementation, are described. Performance results on a variety of different configurations of Cedar that illustrate the benefits of the hierarchical over the nonhierarchical approach are also presented.<>
{"title":"Parallel circuit simulation using hierarchical relaxation","authors":"G. Hung, Yen-Cheng Wen, K. Gallivan, R. Saleh","doi":"10.1109/DAC.1990.114889","DOIUrl":"https://doi.org/10.1109/DAC.1990.114889","url":null,"abstract":"Described is a class of parallel algorithms for circuit simulation based on hierarchical relaxation that has been implemented on the Cedar multiprocessor. The Cedar machine is a reconfigurable, general-purpose supercomputer that was designed and implemented at the University of Illinois. A hierarchical circuit simulation scheme is developed to exploit the hierarchical organization of Cedar. The new algorithm and a number of key issues, such as multilevel circuit partitioning, data partitioning, cluster algorithm selection, and cluster algorithm implementation, are described. Performance results on a variety of different configurations of Cedar that illustrate the benefits of the hierarchical over the nonhierarchical approach are also presented.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126084217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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