A mathematical formulation is presented of the simulated evolution algorithm, a novel optimization technique, followed by a thorough analysis of the associated Markov-chain model. A hierarchical approach is used to solve the placement problem for medium to large circuits which incorporates elements of both placement and circuit partitioning in a single algorithm. It is found that the new hierarchical method not only reduces the overall execution time but also significantly increases the quality of the final result. Its success can be attributed to the fact that it reduces the number of local minima that the optimization algorithm encounters. Therefore, the global structure of the placement can be optimized first, regardless of intermediate limitations imposed by local constraints. By gradually refining the granularity of the optimization method, a solution close to the global minimum can be achieved. A standard cell placement program is described based on the new approach whose preliminary results are comparable to the best simulated annealing algorithms.<>
{"title":"Optimization by simulated evolution with applications to standard cell placement","authors":"R. Kling, P. Banerjee","doi":"10.1109/DAC.1990.114822","DOIUrl":"https://doi.org/10.1109/DAC.1990.114822","url":null,"abstract":"A mathematical formulation is presented of the simulated evolution algorithm, a novel optimization technique, followed by a thorough analysis of the associated Markov-chain model. A hierarchical approach is used to solve the placement problem for medium to large circuits which incorporates elements of both placement and circuit partitioning in a single algorithm. It is found that the new hierarchical method not only reduces the overall execution time but also significantly increases the quality of the final result. Its success can be attributed to the fact that it reduces the number of local minima that the optimization algorithm encounters. Therefore, the global structure of the placement can be optimized first, regardless of intermediate limitations imposed by local constraints. By gradually refining the granularity of the optimization method, a solution close to the global minimum can be achieved. A standard cell placement program is described based on the new approach whose preliminary results are comparable to the best simulated annealing algorithms.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130453166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new parallel hierarchical algorithm for global routing (PHIGURE) is presented. The router is based on the work of M. Burstein and R. Pelavin, (IEEE Trans. CAD, vol.CAD-2, no.4, p.223-34, Oct. 1983) but has many extensions for general global routing and parallel execution. Main features of the algorithm include structured hierarchical decomposition into separate independent tasks which are suitable for parallel execution and adaptive simplex solution for adding feedthroughs and adjusting channel heights for row-based layout. The algorithm is described and results are presented for a shared-memory multiprocessor implementation.<>
{"title":"PHIGURE: a parallel hierarchical global router","authors":"Randall J. Brouwer, P. Banerjee","doi":"10.1145/123186.123429","DOIUrl":"https://doi.org/10.1145/123186.123429","url":null,"abstract":"A new parallel hierarchical algorithm for global routing (PHIGURE) is presented. The router is based on the work of M. Burstein and R. Pelavin, (IEEE Trans. CAD, vol.CAD-2, no.4, p.223-34, Oct. 1983) but has many extensions for general global routing and parallel execution. Main features of the algorithm include structured hierarchical decomposition into separate independent tasks which are suitable for parallel execution and adaptive simplex solution for adding feedthroughs and adjusting channel heights for row-based layout. The algorithm is described and results are presented for a shared-memory multiprocessor implementation.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123095841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There are two canonical optimization problems, network bisectioning (NB) and traveling salesman (TS), that emerge from the physical design and layout of integrated circuits. An analogy is used between iterative techniques for combinatorial optimization and the evolution of biological species to obtain the stochastic evolution (SE) heuristic for solving a wide range of combinatorial optimization problems. It is shown that SE can be specifically tailored to solve both NB and TS. Experimental results for the NB and TS problems show that the SE algorithm produces better quality solutions and is faster than the simulated annealing algorithm in all instances considered.<>
{"title":"Stochastic evolution: a fast effective heuristic for some generic layout problems","authors":"Y. Saab, V. Rao","doi":"10.1109/DAC.1990.114823","DOIUrl":"https://doi.org/10.1109/DAC.1990.114823","url":null,"abstract":"There are two canonical optimization problems, network bisectioning (NB) and traveling salesman (TS), that emerge from the physical design and layout of integrated circuits. An analogy is used between iterative techniques for combinatorial optimization and the evolution of biological species to obtain the stochastic evolution (SE) heuristic for solving a wide range of combinatorial optimization problems. It is shown that SE can be specifically tailored to solve both NB and TS. Experimental results for the NB and TS problems show that the SE algorithm produces better quality solutions and is faster than the simulated annealing algorithm in all instances considered.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128984184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nobu Matsumoto, Y. Watanabe, K. Usami, Y. Sugeno, H. Hatada, S. Mori
A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21 K-transistor data-path whose density is 5.64 KTr/mm/sup 2/, greater than the 5.38 KTr/mm/sup 2/ of a hand-crafted datapath, was generated using 1- mu m CMOS technology.<>
描述了一种数据路径生成器，它可以生成高密度LSI掩模布局，相当于手工制作的掩模布局。生成器的入口是门级的分层符号布局。位行切片技术是实现大尺寸高密度数据路径生成的关键技术。采用1 μ m CMOS技术，生成了密度为5.64 KTr/mm/sup 2/的21 k晶体管数据路径，其密度大于手工制作数据路径的5.38 KTr/mm/sup 2/。
{"title":"Datapath generator based on gate-level symbolic layout","authors":"Nobu Matsumoto, Y. Watanabe, K. Usami, Y. Sugeno, H. Hatada, S. Mori","doi":"10.1145/123186.123314","DOIUrl":"https://doi.org/10.1145/123186.123314","url":null,"abstract":"A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21 K-transistor data-path whose density is 5.64 KTr/mm/sup 2/, greater than the 5.38 KTr/mm/sup 2/ of a hand-crafted datapath, was generated using 1- mu m CMOS technology.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116438176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new fault analysis method for synchronous sequential circuits is presented. Using the iterative array method, extended forward propagation and backward implication are performed, based on the observed values at primary outputs, to deduce the actual values of each line to determine its fault status. Any stuck fault can be identified, even in a circuit without any initialization sequence. A fault which is covered is tested unconditionally; thus the results obtained would not be invalidated in the presence of tested or untestable lines. Examples are given to demonstrate the ability of the method.<>
{"title":"A fault analysis method for synchronous sequential circuits","authors":"T. Kuo, Jau-Yien Lee, Jhing-Fa Wang","doi":"10.1109/DAC.1990.114950","DOIUrl":"https://doi.org/10.1109/DAC.1990.114950","url":null,"abstract":"A new fault analysis method for synchronous sequential circuits is presented. Using the iterative array method, extended forward propagation and backward implication are performed, based on the observed values at primary outputs, to deduce the actual values of each line to determine its fault status. Any stuck fault can be identified, even in a circuit without any initialization sequence. A fault which is covered is tested unconditionally; thus the results obtained would not be invalidated in the presence of tested or untestable lines. Examples are given to demonstrate the ability of the method.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123982882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The problem of routing region definition in the VLSI building-block layout design style is addressed. An algorithm is presented to decompose the routing area into a set of straight channels and switchboxes such that the number of switchboxes in the decomposition is minimized. The algorithm is based on a graph-theoretic approach that makes use of an efficient polynomial time-optimal algorithm for computing minimum clique covers of triangulated graphs. The algorithm was compared with a previously known greedy approach and an exhaustive search optimal algorithm. For all the test problems considered, the new algorithm consistently outperformed the greedy algorithm, and it produced optimal solutions in almost all cases.<>
{"title":"A channel/switchbox definition algorithm for building-block layout","authors":"Yang Cai, D. F. Wong","doi":"10.1145/123186.123425","DOIUrl":"https://doi.org/10.1145/123186.123425","url":null,"abstract":"The problem of routing region definition in the VLSI building-block layout design style is addressed. An algorithm is presented to decompose the routing area into a set of straight channels and switchboxes such that the number of switchboxes in the decomposition is minimized. The algorithm is based on a graph-theoretic approach that makes use of an efficient polynomial time-optimal algorithm for computing minimum clique covers of triangulated graphs. The algorithm was compared with a previously known greedy approach and an exhaustive search optimal algorithm. For all the test problems considered, the new algorithm consistently outperformed the greedy algorithm, and it produced optimal solutions in almost all cases.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115611636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An analytical method for VLSI general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and all application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions, such as chip area, interconnection length, timing delays or any combinations of them, are permitted. Routing space is estimated by the global router. Experimental data are provided.<>
{"title":"An analytical approach to floorplan design and optimization","authors":"S. Sutanthavibul, E. Shragowitz, J. B. Rosen","doi":"10.1109/DAC.1990.114852","DOIUrl":"https://doi.org/10.1109/DAC.1990.114852","url":null,"abstract":"An analytical method for VLSI general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and all application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions, such as chip area, interconnection length, timing delays or any combinations of them, are permitted. Routing space is estimated by the global router. Experimental data are provided.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121844101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate-level circuit and SOP faults into the equivalent stuck-at-faults. Then SOPRANO derives test patterns for SOP faults using a gate-level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.<>
{"title":"SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits","authors":"H. K. Lee, D. Ha","doi":"10.1109/DAC.1990.114936","DOIUrl":"https://doi.org/10.1109/DAC.1990.114936","url":null,"abstract":"The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate-level circuit and SOP faults into the equivalent stuck-at-faults. Then SOPRANO derives test patterns for SOP faults using a gate-level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131398587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<>
{"title":"Optimum and heuristic data path scheduling under resource constraints","authors":"C. Hwang, Y. Hsu, Y. Lin","doi":"10.1109/DAC.1990.114831","DOIUrl":"https://doi.org/10.1109/DAC.1990.114831","url":null,"abstract":"An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131296420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new method for high-level logic synthesis is reported whose basic feature is the tight interaction and coupling of the scheduling and allocation phases providing a global direction to the synthesis. A linear-program-based allocation is proposed which uses multifunction-ALU cost estimation and iteratively drives a tree-search for scheduling. A new interconnect optimization algorithm is proposed. It is based on several interconnect transformations for multiplexer input collapsing and merging. Several other important synthesis aspects are included, e.g., register and interconnect bindings, operation chaining, and operation multicycling. The method has been implemented in C on a Sun 3/60 workstation.<>
{"title":"A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm","authors":"C. Papachristou, H. Konuk","doi":"10.1109/DAC.1990.114833","DOIUrl":"https://doi.org/10.1109/DAC.1990.114833","url":null,"abstract":"A new method for high-level logic synthesis is reported whose basic feature is the tight interaction and coupling of the scheduling and allocation phases providing a global direction to the synthesis. A linear-program-based allocation is proposed which uses multifunction-ALU cost estimation and iteratively drives a tree-search for scheduling. A new interconnect optimization algorithm is proposed. It is based on several interconnect transformations for multiplexer input collapsing and merging. Several other important synthesis aspects are included, e.g., register and interconnect bindings, operation chaining, and operation multicycling. The method has been implemented in C on a Sun 3/60 workstation.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132811385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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