Pub Date : 2018-06-13DOI: 10.1049/iet-cds.2018.0013
Bahram Azizollah-Ganji, Sanaz Kheiry, S. Soleimani
This study presents an implantable passive wireless blood pressure sensor using an inductive coupling wireless sensing technique that is designed for long-term monitoring of blood pressure in hypertension patients. This sensor includes a gold tapered square spiral inductor and a circular capacitor with a polyimide diaphragm. The purpose of this study is to minimise the dimension of the sensor due to the limitation of space around the vessel; therefore, a microelectromechanical systems (MEMS) inductor and a capacitor with small dimension and high sensitivity are used. In this structure, the diaphragm is deflected by applied pressure which capacitance and then resonance frequency are changed. These changes are sensed remotely with inductive coupling, which eliminates the need of wires connection for monitoring. In this method, a blood pressure signal can be obtained by measuring the impedance phase dip from the external coil. The distance between two coils is 8 mm. The sensor is designed to provide a resonance frequency range of 282-381 MHz for a pressure range of 0-250 mmHg. Simulation has been done using COMSOL Multiphysics and ADS software. The dimension of the sensor is 2.2 mm × 2.2 mm and the sensitivity of the sensor is 1550. This sensor has a small size and high sensitivity rather than previous works.
本研究提出了一种植入式无源无线血压传感器，采用电感耦合无线传感技术，设计用于高血压患者的长期血压监测。该传感器包括一个黄金锥形方形螺旋电感和一个圆形电容器与聚酰亚胺隔膜。由于容器周围空间的限制，本研究的目的是尽量减少传感器的尺寸;因此，采用了尺寸小、灵敏度高的微机电系统(MEMS)电感和电容。在这种结构中，膜片在施加压力的作用下发生偏转，从而改变电容和谐振频率。这些变化通过电感耦合远程感知，从而消除了对电线连接进行监测的需要。在这种方法中，通过测量外部线圈的阻抗相位倾角来获得血压信号。两个线圈之间的距离为8mm。该传感器设计用于在0-250 mmHg的压力范围内提供282-381 MHz的共振频率范围。利用COMSOL Multiphysics和ADS软件进行了仿真。传感器尺寸为2.2 mm × 2.2 mm，灵敏度为1550。与以往的传感器相比，该传感器体积小，灵敏度高。
{"title":"Design of small size and high sensitive less-invasive wireless blood pressure sensor using MEMS technology","authors":"Bahram Azizollah-Ganji, Sanaz Kheiry, S. Soleimani","doi":"10.1049/iet-cds.2018.0013","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.0013","url":null,"abstract":"This study presents an implantable passive wireless blood pressure sensor using an inductive coupling wireless sensing technique that is designed for long-term monitoring of blood pressure in hypertension patients. This sensor includes a gold tapered square spiral inductor and a circular capacitor with a polyimide diaphragm. The purpose of this study is to minimise the dimension of the sensor due to the limitation of space around the vessel; therefore, a microelectromechanical systems (MEMS) inductor and a capacitor with small dimension and high sensitivity are used. In this structure, the diaphragm is deflected by applied pressure which capacitance and then resonance frequency are changed. These changes are sensed remotely with inductive coupling, which eliminates the need of wires connection for monitoring. In this method, a blood pressure signal can be obtained by measuring the impedance phase dip from the external coil. The distance between two coils is 8 mm. The sensor is designed to provide a resonance frequency range of 282-381 MHz for a pressure range of 0-250 mmHg. Simulation has been done using COMSOL Multiphysics and ADS software. The dimension of the sensor is 2.2 mm × 2.2 mm and the sensitivity of the sensor is 1550. This sensor has a small size and high sensitivity rather than previous works.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118066796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-13DOI: 10.1049/iet-cds.2017.0499
Jian-Dong Wu, Zhuo-Jia Chen, Jun-Sheng Wang, Lei Zhou, Weijing Wu, Miao Xu, Lei Wang, R. Yao, Junbiao Peng
This study proposes a Manchester-encoded data transmission circuit suitable for 13.56 MHz radio-frequency identification (ID) tags integrated by indium-zinc-oxide thin-film transistors (TFTs). All the modules in the circuit are only constructed by two types of logic units: NOT gate and NOR gate. The 16 bit ID data are stored in the read-only-memory circuits realised by a fixed TFTs array. The 16 bit ID data are encoded by Manchester module as the output of the Manchester-encoded data transmission circuit with a bit rate of 103 kbps. The chip area is 6.5 mm 2 with the total number of gates as 76 and the sum of the transistors as 300. Moreover, the power consumption is 3.8 mW at VDD = 5 V.
本研究提出一种适用于铟锌氧化物薄膜晶体管(TFTs)集成的13.56 MHz射频识别(ID)标签的曼彻斯特编码数据传输电路。电路中的所有模块仅由两种类型的逻辑单元构成:非门和非门。16位ID数据存储在由固定tft阵列实现的只读存储器电路中。16位ID数据由曼彻斯特模块编码，作为曼彻斯特编码数据传输电路的输出，比特率为103kbps。芯片面积为6.5 mm 2，栅极总数为76个，晶体管总数为300个。此外，VDD = 5 V时的功耗为3.8 mW。
{"title":"Manchester-encoded data transmission circuit integrated by metal-oxide TFTs suitable for 13.56 MHz radio-frequency identification tag application","authors":"Jian-Dong Wu, Zhuo-Jia Chen, Jun-Sheng Wang, Lei Zhou, Weijing Wu, Miao Xu, Lei Wang, R. Yao, Junbiao Peng","doi":"10.1049/iet-cds.2017.0499","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0499","url":null,"abstract":"This study proposes a Manchester-encoded data transmission circuit suitable for 13.56 MHz radio-frequency identification (ID) tags integrated by indium-zinc-oxide thin-film transistors (TFTs). All the modules in the circuit are only constructed by two types of logic units: NOT gate and NOR gate. The 16 bit ID data are stored in the read-only-memory circuits realised by a fixed TFTs array. The 16 bit ID data are encoded by Manchester module as the output of the Manchester-encoded data transmission circuit with a bit rate of 103 kbps. The chip area is 6.5 mm\u0000 2\u0000 with the total number of gates as 76 and the sum of the transistors as 300. Moreover, the power consumption is 3.8 mW at VDD = 5 V.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120399547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-13DOI: 10.1049/iet-cds.2017.0542
K. V. Ramana, S. Majhi, A. Gogoi
Accurate dynamics of power converters are necessary to achieve good control performance. In this study, the dynamical model of the DC-DC buck converter is identified by the relay feedback method. The relay is connected in the closed loop to produce a limit cycle output. The important information of the oscillatory output is used for the identification. The relay is approximated using dual-input describing function (DIDF) in the mathematical modelling. DIDF can handle symmetric and asymmetric limit cycle outputs. The converter is modelled as a second-order plus dead-time system. Using the gain and phase angle criteria, analytical expressions are derived to estimate the dynamics. The converter dynamics obtained from the proposed method are compared with that estimated using the state-space averaging method. The model is also identified from the real-time experiment. To check the efficacy of the identified model, a model validation test is performed.
{"title":"Identification of DC-DC buck converter dynamics using relay feedback method with experimental validation","authors":"K. V. Ramana, S. Majhi, A. Gogoi","doi":"10.1049/iet-cds.2017.0542","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0542","url":null,"abstract":"Accurate dynamics of power converters are necessary to achieve good control performance. In this study, the dynamical model of the DC-DC buck converter is identified by the relay feedback method. The relay is connected in the closed loop to produce a limit cycle output. The important information of the oscillatory output is used for the identification. The relay is approximated using dual-input describing function (DIDF) in the mathematical modelling. DIDF can handle symmetric and asymmetric limit cycle outputs. The converter is modelled as a second-order plus dead-time system. Using the gain and phase angle criteria, analytical expressions are derived to estimate the dynamics. The converter dynamics obtained from the proposed method are compared with that estimated using the state-space averaging method. The model is also identified from the real-time experiment. To check the efficacy of the identified model, a model validation test is performed.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118144344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-09DOI: 10.1049/iet-cds.2017.0212
François Gaugaz, F. Krummenacher, M. Kayal
The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.
{"title":"High-speed analogue sampled-data signal processing for real-time fault location in electrical power networks","authors":"François Gaugaz, F. Krummenacher, M. Kayal","doi":"10.1049/iet-cds.2017.0212","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0212","url":null,"abstract":"The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118768143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-30DOI: 10.1049/iet-cds.2017.0411
M. Kumngern, Thanat Nonthaputha, F. Khateb
This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 μm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.
{"title":"Low-power sample and hold circuits using current conveyor analogue switches","authors":"M. Kumngern, Thanat Nonthaputha, F. Khateb","doi":"10.1049/iet-cds.2017.0411","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0411","url":null,"abstract":"This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 μm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118040736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-30DOI: 10.1049/iet-cds.2017.0255
K. Nanamori, Yusuke Sugihara, Masayoshi Yamamoto
Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.
{"title":"Oscillation analysis and current peak reduction in paralleled SiC MOSFETs","authors":"K. Nanamori, Yusuke Sugihara, Masayoshi Yamamoto","doi":"10.1049/iet-cds.2017.0255","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0255","url":null,"abstract":"Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120139470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-11DOI: 10.1049/iet-cds.2017.0058
A. Liacha, A. K. Oudjida, F. Ferguene, Mohammed Bakiri, M. L. Berrandjia
In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r . The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.
{"title":"Design of high-speed, low-power, and area-efficient FIR filters","authors":"A. Liacha, A. K. Oudjida, F. Ferguene, Mohammed Bakiri, M. L. Berrandjia","doi":"10.1049/iet-cds.2017.0058","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0058","url":null,"abstract":"In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r . The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119212982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-11DOI: 10.1049/iet-cds.2016.0342
Jin Wu, You-Chen Zhang, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun
A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal-oxide-semiconductor process, the measurement results show that DLL's frequency locking range is 60-240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <;1 ns and maximum range of around 1 μs as well as the differential non-linearity <;0.68 LSB and the integration non-linearity within -0.97 to 1.24 LSB are obtained for two-segment TDC.
{"title":"Low-jitter DLL applied for two-segment TDC","authors":"Jin Wu, You-Chen Zhang, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun","doi":"10.1049/iet-cds.2016.0342","DOIUrl":"https://doi.org/10.1049/iet-cds.2016.0342","url":null,"abstract":"A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal-oxide-semiconductor process, the measurement results show that DLL's frequency locking range is 60-240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <;1 ns and maximum range of around 1 μs as well as the differential non-linearity <;0.68 LSB and the integration non-linearity within -0.97 to 1.24 LSB are obtained for two-segment TDC.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120493275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-21DOI: 10.1049/iet-cds.2017.0290
A. Caddemi, E. Cardillo, G. Crupi
This study is focused on the experimental investigation of noise at microwave frequencies for scaled gallium arsenide high-electron-mobility transistor's (HEMT's). The light activation of noise has been achieved by laser exposure in the visible range. The devices have 0.25 μm gate length and 100–200–300 μm gate widths. Their DC characteristics, linear scattering and noise parameters were measured both in dark condition and under continuous wave light exposure in the 2–18 GHz frequency range. Previous results had shown a remarkable influence on all the above-measured parameters under illumination, with a special concern for the noise performance. Therefore, the authors investigated the origin of this light-activated noise in terms of the intrinsic noise sources, by extracting a noise temperature circuit model for each HEMT.In addition, the noise model formulation based on the P, R and C as well as the K g, K r and K c coefficients is used to enlighten the key aspects of the optically activated noise on the device performance. It is observed that the degradation of the minimum noise figure can be attributed to the noise coefficient R, related to the gate noise source that is strongly affected by the charge generation related to light exposure.
{"title":"Light activation of noise at microwave frequencies: a study on scaled gallium arsenide HEMT's","authors":"A. Caddemi, E. Cardillo, G. Crupi","doi":"10.1049/iet-cds.2017.0290","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0290","url":null,"abstract":"This study is focused on the experimental investigation of noise at microwave frequencies for scaled gallium arsenide high-electron-mobility transistor's (HEMT's). The light activation of noise has been achieved by laser exposure in the visible range. The devices have 0.25 μm gate length and 100–200–300 μm gate widths. Their DC characteristics, linear scattering and noise parameters were measured both in dark condition and under continuous wave light exposure in the 2–18 GHz frequency range. Previous results had shown a remarkable influence on all the above-measured parameters under illumination, with a special concern for the noise performance. Therefore, the authors investigated the origin of this light-activated noise in terms of the intrinsic noise sources, by extracting a noise temperature circuit model for each HEMT.In addition, the noise model formulation based on the P, R and C as well as the K g, K r and K c coefficients is used to enlighten the key aspects of the optically activated noise on the device performance. It is observed that the degradation of the minimum noise figure can be attributed to the noise coefficient R, related to the gate noise source that is strongly affected by the charge generation related to light exposure.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120738912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-20DOI: 10.1049/iet-cds.2016.0452
Yanhan Zeng, Yu-Ao Liu, Xin Zhang, Hongzhou Tan
Based on negative feedback technique, a complementary metal-oxide semiconductor (CMOS) voltage reference with ultra-low-power, low supply voltage and high-power supply rejection ratio (PSRR) is proposed and simulated using a 0.18 standard micrometre CMOS technology. The operating supply voltage ranges from 0.85 V to 2.5 V and the temperature ranges from -20°C to 80°C. The voltage reference can achieve a temperature coefficient of 16.3 ppm/°C and line sensitivity as low as 0.086 ppm/V, without the use of resistors or special devices, consuming 202 nA current at 27°C. Besides, the PSRR is only -113 dB at 1 Hz, -64 dB at 1 kHz, respectively.
基于负反馈技术，提出了一种超低功耗、低电源电压和高电源抑制比(PSRR)的互补金属氧化物半导体(CMOS)基准电压，并采用0.18标准微米CMOS技术进行了仿真。工作电压范围:0.85 V ~ 2.5 V，工作温度范围:-20℃~ 80℃。该基准电压可实现16.3 ppm/°C的温度系数和低至0.086 ppm/V的线路灵敏度，无需使用电阻或特殊器件，在27°C下消耗202na电流。此外，PSRR在1hz时仅为-113 dB，在1khz时为-64 dB。
{"title":"Ultra-low-power, high PSRR CMOS voltage reference with negative feedback","authors":"Yanhan Zeng, Yu-Ao Liu, Xin Zhang, Hongzhou Tan","doi":"10.1049/iet-cds.2016.0452","DOIUrl":"https://doi.org/10.1049/iet-cds.2016.0452","url":null,"abstract":"Based on negative feedback technique, a complementary metal-oxide semiconductor (CMOS) voltage reference with ultra-low-power, low supply voltage and high-power supply rejection ratio (PSRR) is proposed and simulated using a 0.18 standard micrometre CMOS technology. The operating supply voltage ranges from 0.85 V to 2.5 V and the temperature ranges from -20°C to 80°C. The voltage reference can achieve a temperature coefficient of 16.3 ppm/°C and line sensitivity as low as 0.086 ppm/V, without the use of resistors or special devices, consuming 202 nA current at 27°C. Besides, the PSRR is only -113 dB at 1 Hz, -64 dB at 1 kHz, respectively.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120788821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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