Pub Date : 2019-08-07DOI: 10.1049/IET-CDS.2019.0063
A. Dyskin, I. Kallfass
A feasibility study of a carrier recovery technique based on a feed-forward controlled leakage transmission carrier is presented. The study proposes a receiver topology and verifies its feasibility by means of the system-level simulations. The results of the study indicate that the proposed technique is theoretically modulation-independent and can be used with each modulation format. To demonstrate a practical feasibility, a BPSK receiver topology is proposed and based on it a demonstrator chip is implemented in a SiGe 0.13 μm heterojunction bipolar transistor technology. To reduce the complexity of the integrated receiver and to sustain low risks at the first production run, the receiver was implemented as all-resistive. The carrier recovery circuit on the chip comprises a static frequency divider and a K a -band phase-locked loop with quadrature outputs. A direct-conversion sub-harmonic mixer plays the role of a E-band demodulator. The proposed technique can be used in various high baud rate communication applications, saving on the computing power of the digital process.
{"title":"Feasibility study of the feed-forward carrier recovery technique for E-band integrated receivers","authors":"A. Dyskin, I. Kallfass","doi":"10.1049/IET-CDS.2019.0063","DOIUrl":"https://doi.org/10.1049/IET-CDS.2019.0063","url":null,"abstract":"A feasibility study of a carrier recovery technique based on a feed-forward controlled leakage transmission carrier is presented. The study proposes a receiver topology and verifies its feasibility by means of the system-level simulations. The results of the study indicate that the proposed technique is theoretically modulation-independent and can be used with each modulation format. To demonstrate a practical feasibility, a BPSK receiver topology is proposed and based on it a demonstrator chip is implemented in a SiGe 0.13 μm heterojunction bipolar transistor technology. To reduce the complexity of the integrated receiver and to sustain low risks at the first production run, the receiver was implemented as all-resistive. The carrier recovery circuit on the chip comprises a static frequency divider and a K a -band phase-locked loop with quadrature outputs. A direct-conversion sub-harmonic mixer plays the role of a E-band demodulator. The proposed technique can be used in various high baud rate communication applications, saving on the computing power of the digital process.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120737682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-12DOI: 10.1049/IET-CDS.2019.0029
Ali Kazemi Nasaban Shotorban, Kian Jafari, K. Abedi
Here, a novel optical micro-electro-mechanical systems (MEMS) accelerometer sensor based on a micro-ring resonator and an elliptical disk is proposed. The designed optical MEMS accelerometer is then analysed to obtain its functional characteristics. The proposed optical MEMS sensor presents an optical sensitivity of 0.0025 nm/g, a mechanical sensitivity of 1.56 nm/g, a linear measurement range of ±22 g, a first resonance frequency of 13.02 kHz, and a footprint of 34 μm × 50 μm. Furthermore, the achieved functional characteristics of the proposed accelerometer are compared to several recent contributions in the related field. According to this comparison study, the present optical MEMS accelerometer can be a suitable device for many applications ranging from consumer electronics to inertial measurement units.
{"title":"Optical MEMS accelerometer sensor relying on a micro-ring resonator and an elliptical disk","authors":"Ali Kazemi Nasaban Shotorban, Kian Jafari, K. Abedi","doi":"10.1049/IET-CDS.2019.0029","DOIUrl":"https://doi.org/10.1049/IET-CDS.2019.0029","url":null,"abstract":"Here, a novel optical micro-electro-mechanical systems (MEMS) accelerometer sensor based on a micro-ring resonator and an elliptical disk is proposed. The designed optical MEMS accelerometer is then analysed to obtain its functional characteristics. The proposed optical MEMS sensor presents an optical sensitivity of 0.0025 nm/g, a mechanical sensitivity of 1.56 nm/g, a linear measurement range of ±22 g, a first resonance frequency of 13.02 kHz, and a footprint of 34 μm × 50 μm. Furthermore, the achieved functional characteristics of the proposed accelerometer are compared to several recent contributions in the related field. According to this comparison study, the present optical MEMS accelerometer can be a suitable device for many applications ranging from consumer electronics to inertial measurement units.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119069287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1049/IET-CDS.2018.5422
Junqi Huang, T. Kumar, Haider Abbas, F. Lombardi
This study presents frequency upscaling as a technique for developing error resilient arithmetic designs in approximate computing whereby the input signal frequency of the circuit is upscaled beyond its largest operating value in generating errors in the arithmetic operation while speeding up the computational throughput. This study initially presents the mathematical modelling of frequency upscaling for both exact and inexact full adders. An exhaustive simulation and evaluation of 4 and 8 bits subtraction followed by addition of two images and approximate discrete cosine transform (DCT) is pursued using exact and inexact circuits when subjected to the proposed technique. The results estimated using the proposed model show good agreement with the simulation results. The normalised mean error distance of subtraction using an inexact circuit is close to the exact value for different technology nodes. The peak signal-to-noise ratio (PSNR) results for the addition of two images show that the inexact full adder achieves a higher output image quality than the exact circuit when the frequency is scaled up. Also, in an approximate DCT, the input frequency of an inexact full adder can be scaled up significantly higher than an exact full adder without a significant decrease in PSNR value.
{"title":"Approximate computing using frequency upscaling","authors":"Junqi Huang, T. Kumar, Haider Abbas, F. Lombardi","doi":"10.1049/IET-CDS.2018.5422","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5422","url":null,"abstract":"This study presents frequency upscaling as a technique for developing error resilient arithmetic designs in approximate computing whereby the input signal frequency of the circuit is upscaled beyond its largest operating value in generating errors in the arithmetic operation while speeding up the computational throughput. This study initially presents the mathematical modelling of frequency upscaling for both exact and inexact full adders. An exhaustive simulation and evaluation of 4 and 8 bits subtraction followed by addition of two images and approximate discrete cosine transform (DCT) is pursued using exact and inexact circuits when subjected to the proposed technique. The results estimated using the proposed model show good agreement with the simulation results. The normalised mean error distance of subtraction using an inexact circuit is close to the exact value for different technology nodes. The peak signal-to-noise ratio (PSNR) results for the addition of two images show that the inexact full adder achieves a higher output image quality than the exact circuit when the frequency is scaled up. Also, in an approximate DCT, the input frequency of an inexact full adder can be scaled up significantly higher than an exact full adder without a significant decrease in PSNR value.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117962316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-20DOI: 10.1049/IET-CDS.2018.5544
Soumyajit Seth
Robust Chaos occurring in piecewise smooth dynamical systems is very important in practical applications. It is defined by the absence of periodic windows and coexisting attractors in some neighbourhood of the parameter space. In earlier works, the occurrence of robust chaos was reported in the context of piecewise linear 1D and 2D maps, and regions of occurrences have been investigated in 1D and 2D switching circuits. Here, it has been reported the first experimental observation of this phenomenon in a 3D electronic switching system and obtain the region of parameter space by constructing a discrete map of the system.
{"title":"Observation of robust chaos in 3D electronic system","authors":"Soumyajit Seth","doi":"10.1049/IET-CDS.2018.5544","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5544","url":null,"abstract":"Robust Chaos occurring in piecewise smooth dynamical systems is very important in practical applications. It is defined by the absence of periodic windows and coexisting attractors in some neighbourhood of the parameter space. In earlier works, the occurrence of robust chaos was reported in the context of piecewise linear 1D and 2D maps, and regions of occurrences have been investigated in 1D and 2D switching circuits. Here, it has been reported the first experimental observation of this phenomenon in a 3D electronic switching system and obtain the region of parameter space by constructing a discrete map of the system.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119115554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-13DOI: 10.1049/IET-CDS.2018.5044
B. Kushwaha, Gautam Rituraj, Praveen Kumar, P. Bauer
In recent years, the use of wireless power transfer (WPT) has gained momentum in electric vehicle charging. To design the WPT system, three-dimensional (3D) finite element method (FEM) is used for mutual inductance calculation, and the system performance is evaluated using a circuit simulator. The use of 3D FEM makes the initial design a tedious process. Hence, there is a need for a reliable analytical model which can be used in the preliminary design process. This work proposes a mathematical model of a series–parallel (SP) compensated WPT system that can determine the mutual inductance and the system parameters such as voltage, current, power, and efficiency for different misalignments. The mathematical model consists of electromagnetic and steady-state models. This model can be used to analyse the component stress of SP compensated WPT system. The results of the mathematical model are verified experimentally. Thus, the proposed method can be adopted in the initial design process of SP compensated WPT system.
{"title":"Mathematical model for the analysis of series-parallel compensated wireless power transfer system for different misalignments","authors":"B. Kushwaha, Gautam Rituraj, Praveen Kumar, P. Bauer","doi":"10.1049/IET-CDS.2018.5044","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5044","url":null,"abstract":"In recent years, the use of wireless power transfer (WPT) has gained momentum in electric vehicle charging. To design the WPT system, three-dimensional (3D) finite element method (FEM) is used for mutual inductance calculation, and the system performance is evaluated using a circuit simulator. The use of 3D FEM makes the initial design a tedious process. Hence, there is a need for a reliable analytical model which can be used in the preliminary design process. This work proposes a mathematical model of a series–parallel (SP) compensated WPT system that can determine the mutual inductance and the system parameters such as voltage, current, power, and efficiency for different misalignments. The mathematical model consists of electromagnetic and steady-state models. This model can be used to analyse the component stress of SP compensated WPT system. The results of the mathematical model are verified experimentally. Thus, the proposed method can be adopted in the initial design process of SP compensated WPT system.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119739275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-13DOI: 10.1049/IET-CDS.2018.5273
J. Pandey, Tarun Goel, A. Karmakar
Data security is essential for the proliferation of the Internet of things and cyber-physical system technologies. Data security can be efficiently achieved by incorporating lightweight cryptography techniques. In this study, a set of high-performance hardware architectures for PRESENT lightweight block cipher are proposed that perform encryption, decryption and integrated encryption/decryption operations. Datapath of the architectures is of 64 bit width that supports standard 80 and 128 bits key lengths. The architectures are synthesised on Xilinx Virtex-5 XC5VLX110T (ff1136-1) field-programmable gate array device of ML-505 platform. To perform functional verification, a large number of test vectors are used. Performance measurement is performed by evaluating maximum frequency, throughput, power dissipation and energy consumption. Experimentally, it is found that the proposed architectures are resource-efficient, high-performance and suitable for lightweight, latency-critical and low-power applications in comparison with existing architectures.
{"title":"Hardware architectures for PRESENT block cipher and their FPGA implementations","authors":"J. Pandey, Tarun Goel, A. Karmakar","doi":"10.1049/IET-CDS.2018.5273","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5273","url":null,"abstract":"Data security is essential for the proliferation of the Internet of things and cyber-physical system technologies. Data security can be efficiently achieved by incorporating lightweight cryptography techniques. In this study, a set of high-performance hardware architectures for PRESENT lightweight block cipher are proposed that perform encryption, decryption and integrated encryption/decryption operations. Datapath of the architectures is of 64 bit width that supports standard 80 and 128 bits key lengths. The architectures are synthesised on Xilinx Virtex-5 XC5VLX110T (ff1136-1) field-programmable gate array device of ML-505 platform. To perform functional verification, a large number of test vectors are used. Performance measurement is performed by evaluating maximum frequency, throughput, power dissipation and energy consumption. Experimentally, it is found that the proposed architectures are resource-efficient, high-performance and suitable for lightweight, latency-critical and low-power applications in comparison with existing architectures.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119827071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-30DOI: 10.1049/IET-CDS.2018.5304
Ramin Razmdideh, M. Saneei
Time-to-digital converter (TDC) is one of the important blocks in most of the digital systems that need to have high resolution. Time difference amplifier (TDA) is used in TDC for increasing the resolution. In this study, an all-digital TDA is proposed. The proposed TDA uses the delay lines with difference delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and has a gain of ten and a chip area of about 0.003 mm2. The calculated maximum gain error is 5%. The proposed TDA consumes 0.94 mW power under 1.1 V supply voltage.
{"title":"All-digital delay line-based time difference amplifier in 65 nm CMOS technology","authors":"Ramin Razmdideh, M. Saneei","doi":"10.1049/IET-CDS.2018.5304","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5304","url":null,"abstract":"Time-to-digital converter (TDC) is one of the important blocks in most of the digital systems that need to have high resolution. Time difference amplifier (TDA) is used in TDC for increasing the resolution. In this study, an all-digital TDA is proposed. The proposed TDA uses the delay lines with difference delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and has a gain of ten and a chip area of about 0.003 mm2. The calculated maximum gain error is 5%. The proposed TDA consumes 0.94 mW power under 1.1 V supply voltage.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119762671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-18DOI: 10.1049/IET-CDS.2018.5560
Yongtao Qiu, Jie Zhou, Youjiang Liu, Guifu Zhang, Yinong Liu
This article presented a novel digital blind calibration technique of time-skew mismatches for time-interleaved analogue-to-digital converter (TI-ADC). Based on the frequency-shifted and derived operation, the spurious signals could be reconstructed and subtracted from the sampled signal adaptively. The main advantage of the proposed calibration technique is applicable to any channel TI-ADC and could achieve higher performance in comparison with the state-of-the-arts. Numerical simulations and experimental results have demonstrated that the proposed calibration technique could significantly improve the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI-ADC system.
{"title":"Novel adaptive blind calibration technique of time-skew mismatches for any channel time-interleaved analogue-to-digital converters","authors":"Yongtao Qiu, Jie Zhou, Youjiang Liu, Guifu Zhang, Yinong Liu","doi":"10.1049/IET-CDS.2018.5560","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5560","url":null,"abstract":"This article presented a novel digital blind calibration technique of time-skew mismatches for time-interleaved analogue-to-digital converter (TI-ADC). Based on the frequency-shifted and derived operation, the spurious signals could be reconstructed and subtracted from the sampled signal adaptively. The main advantage of the proposed calibration technique is applicable to any channel TI-ADC and could achieve higher performance in comparison with the state-of-the-arts. Numerical simulations and experimental results have demonstrated that the proposed calibration technique could significantly improve the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI-ADC system.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117380349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-15DOI: 10.1049/IET-CDS.2018.5220
Lu Liu, Daiguo Xu, Shiliu Xu
This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-to-analogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm.
{"title":"Rapid calibration of bits weights error for high-resolution successive approximation register ADC","authors":"Lu Liu, Daiguo Xu, Shiliu Xu","doi":"10.1049/IET-CDS.2018.5220","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5220","url":null,"abstract":"This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-to-analogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119697012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-07DOI: 10.1049/IET-CDS.2018.5263
M. Bilal
Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.
{"title":"Resource-efficient FPGA implementation of perspective transformation for bird's eye view generation using high-level synthesis framework","authors":"M. Bilal","doi":"10.1049/IET-CDS.2018.5263","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5263","url":null,"abstract":"Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120457066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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