Pub Date : 2015-04-09DOI: 10.1049/iet-cds.2013.0437
D. Alghisi, M. Ferrari, V. Ferrari
This paper presents a battery-less non-contact temperature measurement system powered by energy harvesting from intentional human action. The conversion between the human action and electrical energy is provided by a hand-crank electromagnetic (EM) converter. The AC voltage generated by the EM converter has time-varying amplitude and frequency and is rectified by a metal–oxide-semiconductor field-effect transistor-based voltage doubler active rectifier circuit. The harvested energy is efficiently stored into multiple capacitors by the innovative sequential charging of storage capacitors technique, and used to power a micro electro mechanical system thermopile sensor with related signal conditioning electronics plus a liquid-crystal display to visualise the temperature readings. With a force of about 29.4 N over 2 cm applied to the EM converter, the power management circuit is able to extract an energy of 27.5 mJ and power the non-contact temperature measurement system for about 33 s.
本文提出了一种无电池的非接触式温度测量系统，该系统由人类有意行为的能量收集提供动力。人的动作和电能之间的转换是由手曲柄电磁转换器提供的。电磁变换器产生的交流电压具有时变幅度和时变频率，并由基于金属氧化物半导体场效应晶体管的倍压有源整流电路进行整流。通过创新的存储电容器顺序充电技术，收集的能量被有效地存储在多个电容器中，并用于为带有相关信号调理电子设备的微机电系统热电堆传感器提供动力，外加一个液晶显示器，以显示温度读数。当对EM转换器施加约29.4 N / 2 cm的力时，电源管理电路能够提取27.5 mJ的能量，并为非接触式温度测量系统供电约33 s。
{"title":"Battery-less non-contact temperature measurement system powered by energy harvesting from intentional human action","authors":"D. Alghisi, M. Ferrari, V. Ferrari","doi":"10.1049/iet-cds.2013.0437","DOIUrl":"https://doi.org/10.1049/iet-cds.2013.0437","url":null,"abstract":"This paper presents a battery-less non-contact temperature measurement system powered by energy harvesting from intentional human action. The conversion between the human action and electrical energy is provided by a hand-crank electromagnetic (EM) converter. The AC voltage generated by the EM converter has time-varying amplitude and frequency and is rectified by a metal–oxide-semiconductor field-effect transistor-based voltage doubler active rectifier circuit. The harvested energy is efficiently stored into multiple capacitors by the innovative sequential charging of storage capacitors technique, and used to power a micro electro mechanical system thermopile sensor with related signal conditioning electronics plus a liquid-crystal display to visualise the temperature readings. With a force of about 29.4 N over 2 cm applied to the EM converter, the power management circuit is able to extract an energy of 27.5 mJ and power the non-contact temperature measurement system for about 33 s.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115628551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1049/iet-cds.2013.0475
A. Erfanian, H. Mehrara, F. Raissi, M. Khaje
The authors report on Coulomb blockade effect in the PtSi/porous Si Schottky barrier. A model of two-dimensional multi-tunnelling junction (2D-MTJ) can explain the blockade characteristic of this barrier. Using the SIMON simulator, the electrical characteristics of the proposed model were investigated. The results show that simulated current–voltage curves achieve a reasonable fit with the measured data and the present model can be used to study the PtSi/porous Si Schottky barrier behaviour. In accordance with both the studies, Coulomb blockade phenomenon is observed in current oscillation and single-electron effect of this device at low temperatures (5 K) is justified using the 2D-MTJ model. In addition, it indicates that by increasing the current value with temperature and for high drain voltages, PtSi/porous Si Schottky barrier behaves like a single island single-electron tunnelling (SET) junction as previously reported by Raissi et al.
{"title":"Coulomb blockade in PtSi/porous Si Schottky barrier as a two-dimensional multi-tunnelling junction","authors":"A. Erfanian, H. Mehrara, F. Raissi, M. Khaje","doi":"10.1049/iet-cds.2013.0475","DOIUrl":"https://doi.org/10.1049/iet-cds.2013.0475","url":null,"abstract":"The authors report on Coulomb blockade effect in the PtSi/porous Si Schottky barrier. A model of two-dimensional multi-tunnelling junction (2D-MTJ) can explain the blockade characteristic of this barrier. Using the SIMON simulator, the electrical characteristics of the proposed model were investigated. The results show that simulated current–voltage curves achieve a reasonable fit with the measured data and the present model can be used to study the PtSi/porous Si Schottky barrier behaviour. In accordance with both the studies, Coulomb blockade phenomenon is observed in current oscillation and single-electron effect of this device at low temperatures (5 K) is justified using the 2D-MTJ model. In addition, it indicates that by increasing the current value with temperature and for high drain voltages, PtSi/porous Si Schottky barrier behaves like a single island single-electron tunnelling (SET) junction as previously reported by Raissi et al.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134277947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-02-02DOI: 10.1049/iet-cds.2014.0204
S. Awan, G. Pan, Laith M. Al Taan, Bing-Jing Li, N. Jamil
The authors report measurement of the radio-frequency (RF) transport electromagnetic properties of chemical vapour deposition graphene over the direct current (DC) to 110 MHz frequency range at room temperature. Graphene on Si/SiO2 substrate was mounted in a shielded four terminal-pair (4TP) adaptor which enabled direct connection to a calibrated precision impedance analyser for measurements. Good agreement is observed for the DC four-probe resistance and the 4TP resistance at 40 Hz, both yielding R ≈ 104 Ω. In general, the apparent graphene channel electromagnetic properties are found to be strongly influenced by the substrate parasitic capacitance and resistance, particularly for high-frequencies f > 1 MHz. A phenomenological lumped-parameter equivalent circuit model is presented which matches the frequency response of the graphene 4TP impedance device over approximately seven decades of the frequency range of the applied transport alternating current. Based on this model, it is shown for the first time, that the intrinsic graphene channel resistance of the 4TP device is ‘frequency-independent’ with R G ≃ 105 Ω or sheet resistance of approximately 182 Ω/□. The parasitic substrate impedance of the device is found to be R P ≃ 2.2 Ω and C P ≃ 600 pF. These results suggest that our new RF 4TP method is in good agreement with the conventional DC four-probe method for measuring the intrinsic sheet resistance of single-atom thick materials and could potentially open up new applications in RF electronics, AC quantum Hall effect metrology and sensors based on graphene 4TP devices operating over a broad range of frequencies.
{"title":"Radio-frequency transport Electromagnetic Properties of chemical vapour deposition graphene from direct current to 110 MHz","authors":"S. Awan, G. Pan, Laith M. Al Taan, Bing-Jing Li, N. Jamil","doi":"10.1049/iet-cds.2014.0204","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0204","url":null,"abstract":"The authors report measurement of the radio-frequency (RF) transport electromagnetic properties of chemical vapour deposition graphene over the direct current (DC) to 110 MHz frequency range at room temperature. Graphene on Si/SiO2 substrate was mounted in a shielded four terminal-pair (4TP) adaptor which enabled direct connection to a calibrated precision impedance analyser for measurements. Good agreement is observed for the DC four-probe resistance and the 4TP resistance at 40 Hz, both yielding R ≈ 104 Ω. In general, the apparent graphene channel electromagnetic properties are found to be strongly influenced by the substrate parasitic capacitance and resistance, particularly for high-frequencies f > 1 MHz. A phenomenological lumped-parameter equivalent circuit model is presented which matches the frequency response of the graphene 4TP impedance device over approximately seven decades of the frequency range of the applied transport alternating current. Based on this model, it is shown for the first time, that the intrinsic graphene channel resistance of the 4TP device is ‘frequency-independent’ with R G ≃ 105 Ω or sheet resistance of approximately 182 Ω/□. The parasitic substrate impedance of the device is found to be R P ≃ 2.2 Ω and C P ≃ 600 pF. These results suggest that our new RF 4TP method is in good agreement with the conventional DC four-probe method for measuring the intrinsic sheet resistance of single-atom thick materials and could potentially open up new applications in RF electronics, AC quantum Hall effect metrology and sensors based on graphene 4TP devices operating over a broad range of frequencies.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130588694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-02-02DOI: 10.1049/iet-cds.2014.0069
V. Kochat, Anindita Sahoo, A. N. Pal, Sneha Eashwer, Gopalakrishnan Ramalingam, A. Sampathkumar, R. Tero, T. V. Thu, S. Kaushal, H. Okada, A. Sandhu, S. Raghavan, A. Ghosh
The authors report a detailed investigation of the flicker noise (1/f noise) in graphene films obtained from chemical vapour deposition (CVD) and chemical reduction of graphene oxide. The authors find that in the case of polycrystalline graphene films grown by CVD, the grain boundaries and other structural defects are the dominant source of noise by acting as charged trap centres resulting in huge increase in noise as compared with that of exfoliated graphene. A study of the kinetics of defects in hydrazine-reduced graphene oxide (RGO) films as a function of the extent of reduction showed that for longer hydrazine treatment time strong localised crystal defects are introduced in RGO, whereas the RGO with shorter hydrazine treatment showed the presence of large number of mobile defects leading to higher noise amplitude.
{"title":"Origin of 1/f noise in graphene produced for large-scale applications in electronics","authors":"V. Kochat, Anindita Sahoo, A. N. Pal, Sneha Eashwer, Gopalakrishnan Ramalingam, A. Sampathkumar, R. Tero, T. V. Thu, S. Kaushal, H. Okada, A. Sandhu, S. Raghavan, A. Ghosh","doi":"10.1049/iet-cds.2014.0069","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0069","url":null,"abstract":"The authors report a detailed investigation of the flicker noise (1/f noise) in graphene films obtained from chemical vapour deposition (CVD) and chemical reduction of graphene oxide. The authors find that in the case of polycrystalline graphene films grown by CVD, the grain boundaries and other structural defects are the dominant source of noise by acting as charged trap centres resulting in huge increase in noise as compared with that of exfoliated graphene. A study of the kinetics of defects in hydrazine-reduced graphene oxide (RGO) films as a function of the extent of reduction showed that for longer hydrazine treatment time strong localised crystal defects are introduced in RGO, whereas the RGO with shorter hydrazine treatment showed the presence of large number of mobile defects leading to higher noise amplitude.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121605778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-01-23DOI: 10.1049/iet-cds.2014.0064
Homod S. Alaabdlqader, A. Sleiman, P. Sayers, M. Mabrook
To produce organic non-volatile organic memory transistors, graphene oxide (GO) nanoparticles were embedded in the floating gate of an all organic memory structure using polymethylmethacrylate as the dielectric and pentacene as the organic semiconductor. The current–voltage characteristics and the memory behaviour of the GO-based organic thin film memory transistors are reported. GO-based memory transistors were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics were attributed to the charging and discharging of the floating gate. Fast switching and large memory windows (∼26 V) exhibiting high charge density (6.25 × 1012 cm−2) were achieved.
{"title":"Graphene oxide-based non-volatile organic field effect memory transistors","authors":"Homod S. Alaabdlqader, A. Sleiman, P. Sayers, M. Mabrook","doi":"10.1049/iet-cds.2014.0064","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0064","url":null,"abstract":"To produce organic non-volatile organic memory transistors, graphene oxide (GO) nanoparticles were embedded in the floating gate of an all organic memory structure using polymethylmethacrylate as the dielectric and pentacene as the organic semiconductor. The current–voltage characteristics and the memory behaviour of the GO-based organic thin film memory transistors are reported. GO-based memory transistors were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics were attributed to the charging and discharging of the floating gate. Fast switching and large memory windows (∼26 V) exhibiting high charge density (6.25 × 1012 cm−2) were achieved.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131758508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-01-08DOI: 10.1049/iet-cds.2014.0093
Zhong Yan, D. Nika, A. Balandin
The authors review thermal properties of graphene and few-layer graphene (FLG), and discuss applications of these materials in thermal management of advanced electronics. The intrinsic thermal conductivity of graphene - among the highest of known materials - is dominated by phonons near the room temperature. The examples of thermal management applications include the FLG heat spreaders integrated near the heat generating areas of the high-power density transistors. It has been demonstrated that FLG heat spreaders can lower the hot-spot temperature during device operation, resulting in improved performance and reliability of the devices.
{"title":"Thermal properties of graphene and few-layer graphene: applications in electronics","authors":"Zhong Yan, D. Nika, A. Balandin","doi":"10.1049/iet-cds.2014.0093","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0093","url":null,"abstract":"The authors review thermal properties of graphene and few-layer graphene (FLG), and discuss applications of these materials in thermal management of advanced electronics. The intrinsic thermal conductivity of graphene - among the highest of known materials - is dominated by phonons near the room temperature. The examples of thermal management applications include the FLG heat spreaders integrated near the heat generating areas of the high-power density transistors. It has been demonstrated that FLG heat spreaders can lower the hot-spot temperature during device operation, resulting in improved performance and reliability of the devices.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130936952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-08-19DOI: 10.1049/iet-cds.2014.0275
T. Chakraborty, V. Apalkov
Bloch electrons in a perpendicular magnetic field exhibit unusual dynamics that has been studied for more than half a century. The single-electron energy spectrum of this system, the Hofstadter butterfly has been the subject of theoretical and experimental investigations for the past two decades. Experimental observation of these unusual spectra in semiconductor nanostructures, however, met with only limited success. The fractal nature of the butterfly spectrum was finally observed in 2013, thanks to the unique electronic properties of graphene. Here, the authors present an overview of the theoretical understanding of Hofstadter butterflies in monolayer and bilayer graphene. First, they briefly discuss the energy spectra in conventional semiconductor systems. The electronic properties of monolayer and bilayer graphene are then presented. Theoretical background on the Moire pattern in graphene and its application in the magnetoconductance probe that resulted in graphene butterflies are explained. They have also touched upon the important role of electron–electron interaction in the butterfly pattern in graphene. Experimental efforts to investigate this aspect of fractal butterflies have just begun. They conclude by discussing the future prospects of butterfly search, especially for interacting Dirac fermions in graphene.
{"title":"Fractal butterflies of Dirac fermions in monolayer and bilayer graphene","authors":"T. Chakraborty, V. Apalkov","doi":"10.1049/iet-cds.2014.0275","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0275","url":null,"abstract":"Bloch electrons in a perpendicular magnetic field exhibit unusual dynamics that has been studied for more than half a century. The single-electron energy spectrum of this system, the Hofstadter butterfly has been the subject of theoretical and experimental investigations for the past two decades. Experimental observation of these unusual spectra in semiconductor nanostructures, however, met with only limited success. The fractal nature of the butterfly spectrum was finally observed in 2013, thanks to the unique electronic properties of graphene. Here, the authors present an overview of the theoretical understanding of Hofstadter butterflies in monolayer and bilayer graphene. First, they briefly discuss the energy spectra in conventional semiconductor systems. The electronic properties of monolayer and bilayer graphene are then presented. Theoretical background on the Moire pattern in graphene and its application in the magnetoconductance probe that resulted in graphene butterflies are explained. They have also touched upon the important role of electron–electron interaction in the butterfly pattern in graphene. Experimental efforts to investigate this aspect of fractal butterflies have just begun. They conclude by discussing the future prospects of butterfly search, especially for interacting Dirac fermions in graphene.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133408169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-01DOI: 10.1049/iet-cds.2013.0011
Chan-Hui Jeong, Kyu-Young Kim, Chan-Keun Kwon, H. Kim, Soo-Won Kim
The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .
{"title":"Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops","authors":"Chan-Hui Jeong, Kyu-Young Kim, Chan-Keun Kwon, H. Kim, Soo-Won Kim","doi":"10.1049/iet-cds.2013.0011","DOIUrl":"https://doi.org/10.1049/iet-cds.2013.0011","url":null,"abstract":"The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118577210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-01DOI: 10.1049/iet-cds.2013.0098
P. Tsai, Tzuen-Hsi Huang, Yu-Ting Chen
A dual-band quadrature voltage-controlled oscillator (QVCO) with high figure-of-merits (FOMs) and cost-area efficiency is presented by integrating with differential inner-diamond-structure switchable inductors which have improved performances. This proposed QVCO is fabricated in a 0.18-μm complementary metal-oxide semiconductor process with an active-region area of 0.61 mm2. The QVCO core totally consumes 6.8 mA from 1.8 V supply voltage. The frequency tuning ranges are 120 MHz (from 3.18 to 3.3 GHz) for the low-band and 500 MHz (from 6.94 to 7.44 GHz) for the high-band, while the tuning voltage rises from 0 to 1.8 V. The best phase noises with an offset frequency of 1 MHz from the oscillation frequency in the low- and high-bands are −121.9 and −117.5 dBc/Hz, respectively. The measured phase errors in both high-band and low-band are less than 1°. The calculated FOMs, no matter the switch is off or on, are better than −180 dBc/Hz.
{"title":"Dual-band quadrature voltage-controlled oscillator using differential inner-diamond-structure switchable inductor","authors":"P. Tsai, Tzuen-Hsi Huang, Yu-Ting Chen","doi":"10.1049/iet-cds.2013.0098","DOIUrl":"https://doi.org/10.1049/iet-cds.2013.0098","url":null,"abstract":"A dual-band quadrature voltage-controlled oscillator (QVCO) with high figure-of-merits (FOMs) and cost-area efficiency is presented by integrating with differential inner-diamond-structure switchable inductors which have improved performances. This proposed QVCO is fabricated in a 0.18-μm complementary metal-oxide semiconductor process with an active-region area of 0.61 mm2. The QVCO core totally consumes 6.8 mA from 1.8 V supply voltage. The frequency tuning ranges are 120 MHz (from 3.18 to 3.3 GHz) for the low-band and 500 MHz (from 6.94 to 7.44 GHz) for the high-band, while the tuning voltage rises from 0 to 1.8 V. The best phase noises with an offset frequency of 1 MHz from the oscillation frequency in the low- and high-bands are −121.9 and −117.5 dBc/Hz, respectively. The measured phase errors in both high-band and low-band are less than 1°. The calculated FOMs, no matter the switch is off or on, are better than −180 dBc/Hz.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119820708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-01DOI: 10.1049/iet-cds.2012.0398
B. K. Mohanty, Anurag Mahajan
In this paper, we have proposed a novel scheduling scheme for generating continuous input-blocks for the succeeding processing units of parallel structure to achieve 100% hardware utilisation efficiency (HUE) without block folding. Based on the proposed scheme, we have derived a parallel and pipeline structure for multilevel lifting two-dimensional discrete wavelet transform (DWT). The proposed structure involves regular data-flow and does not require frame-buffer, and calculates DWT levels concurrently. A theoretical comparison shows that the proposed structure for J = 2 involves 1.25 times more multipliers and adders, 2 N more registers than those of existing folded block-based structure and offers 1.25 times higher throughput, where N is the input-image width. Compared with similar existing parallel structure, the proposed structure requires the same number of multipliers and adders, 2.125 N less registers and offers the same throughput rate. Application specific integrated circuit synthesis result shows that the core of the proposed structure for 2-level DWT and image size (512 × 512) involves 41% less area-delay-product and 36% less energy-per-image than those of similar existing parallel structure.
{"title":"Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer","authors":"B. K. Mohanty, Anurag Mahajan","doi":"10.1049/iet-cds.2012.0398","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0398","url":null,"abstract":"In this paper, we have proposed a novel scheduling scheme for generating continuous input-blocks for the succeeding processing units of parallel structure to achieve 100% hardware utilisation efficiency (HUE) without block folding. Based on the proposed scheme, we have derived a parallel and pipeline structure for multilevel lifting two-dimensional discrete wavelet transform (DWT). The proposed structure involves regular data-flow and does not require frame-buffer, and calculates DWT levels concurrently. A theoretical comparison shows that the proposed structure for\u0000 J \u0000= 2 involves 1.25 times more multipliers and adders, 2\u0000 N \u0000more registers than those of existing folded block-based structure and offers 1.25 times higher throughput, where\u0000 N \u0000is the input-image width. Compared with similar existing parallel structure, the proposed structure requires the same number of multipliers and adders, 2.125\u0000 N \u0000less registers and offers the same throughput rate. Application specific integrated circuit synthesis result shows that the core of the proposed structure for 2-level DWT and image size (512 × 512) involves 41% less area-delay-product and 36% less energy-per-image than those of similar existing parallel structure.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117704783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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