Pub Date : 2019-03-01DOI: 10.1049/iet-cds.2018.5110
Tanmai Kulshreshtha, A. Dhar
This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.
{"title":"Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm","authors":"Tanmai Kulshreshtha, A. Dhar","doi":"10.1049/iet-cds.2018.5110","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.5110","url":null,"abstract":"This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118030416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-04DOI: 10.1049/IET-CDS.2018.5201
Arun Kumar, S. Bhushan, P. Tiwari
Here, an analytical modelling of drain current is presented for double gate-all-around (DGAA) MOSFETs. A common feature in all the multi-gate (MG) MOSFETs is that the channel charge in the sub-threshold regime is proportional to the channel cross-sectional area; whereas, the inversion charges above threshold locate near the Si/SiO2 interfaces and are proportional to the total gated perimeter of the channel body. This distinctive feature introduces the notion of equivalent charge and has been widely used to model the drain current of any arbitrary non-classical MOSFET architecture. The authors have extended the aforementioned quasi-approach to model the drain current of DGAA MOSFET. The total gated perimeter of DGAA MOSFET is mapped by the gated perimeter of two GAA MOSFETs with different radii for the calculation of surface inversion charges above threshold. The currents obtained from two GAA MOSFETs are summed up to obtain the current of DGAA MOSFET. I–V characteristics and transconductance of the device for various physical parameters are compared and analysed with the numerical simulation results obtained from Visual-TCAD of Cogenda Int.
{"title":"Drain current modelling of double gate-all-around (DGAA) MOSFETs","authors":"Arun Kumar, S. Bhushan, P. Tiwari","doi":"10.1049/IET-CDS.2018.5201","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5201","url":null,"abstract":"Here, an analytical modelling of drain current is presented for double gate-all-around (DGAA) MOSFETs. A common feature in all the multi-gate (MG) MOSFETs is that the channel charge in the sub-threshold regime is proportional to the channel cross-sectional area; whereas, the inversion charges above threshold locate near the Si/SiO2 interfaces and are proportional to the total gated perimeter of the channel body. This distinctive feature introduces the notion of equivalent charge and has been widely used to model the drain current of any arbitrary non-classical MOSFET architecture. The authors have extended the aforementioned quasi-approach to model the drain current of DGAA MOSFET. The total gated perimeter of DGAA MOSFET is mapped by the gated perimeter of two GAA MOSFETs with different radii for the calculation of surface inversion charges above threshold. The currents obtained from two GAA MOSFETs are summed up to obtain the current of DGAA MOSFET. I–V characteristics and transconductance of the device for various physical parameters are compared and analysed with the numerical simulation results obtained from Visual-TCAD of Cogenda Int.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119736578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-17DOI: 10.1049/iet-cds.2018.0086
J. Chen
The solutions of inverter switch and routing scheme are integrated to develop a mobile controlled energy saving system (MCESS). For the transient response problem of an n-channel metal-oxide-semiconductor field-effect transistor acting as an invert switch, and a routing scheme is solved for developing the MCESS. It can be claimed that all the mentioned previously schemes are very challenge for addressing the problems in the design of an analogue processing circuit and the implementation of Android applications (or Apps). The developed MCESS is experimentally verified automatically switch for adjusting the energy output appropriately. A control system with a solution of MCESS can replace the traditional sustainable energy systems, and obtain much longer lifetime and a steady state of the storage equipment. Furthermore, the proposed MCESS integrates Apps developed on a smart device using the Android platform with different wireless protocols, such as WiFi, Bluetooth for controlling the system with contactless. Moreover, there much experience in the development of MCESS is provided audiences with useful materials, for example a routing solution that employs wireless local area network with the WiFi protocol is implemented to transmit packets of the regulator circuit and the instant feedback display.
{"title":"Integrated routing scheme and inverter switch to develop a mobile controlled energy saving system","authors":"J. Chen","doi":"10.1049/iet-cds.2018.0086","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.0086","url":null,"abstract":"The solutions of inverter switch and routing scheme are integrated to develop a mobile controlled energy saving system (MCESS). For the transient response problem of an n-channel metal-oxide-semiconductor field-effect transistor acting as an invert switch, and a routing scheme is solved for developing the MCESS. It can be claimed that all the mentioned previously schemes are very challenge for addressing the problems in the design of an analogue processing circuit and the implementation of Android applications (or Apps). The developed MCESS is experimentally verified automatically switch for adjusting the energy output appropriately. A control system with a solution of MCESS can replace the traditional sustainable energy systems, and obtain much longer lifetime and a steady state of the storage equipment. Furthermore, the proposed MCESS integrates Apps developed on a smart device using the Android platform with different wireless protocols, such as WiFi, Bluetooth for controlling the system with contactless. Moreover, there much experience in the development of MCESS is provided audiences with useful materials, for example a routing solution that employs wireless local area network with the WiFi protocol is implemented to transmit packets of the regulator circuit and the instant feedback display.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120264128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-17DOI: 10.1049/IET-CDS.2018.5165
M. K. Tiwari, N. Pandey, S. K. Paul, Saiyid Mohammad Irshad Rizvi
In this study, an effective and efficient approach for reliability analysis is developed to bridge the gap between device-level reliability and that at the product level. Continual reduction of device dimensions, gate-oxide and increase in channel doping results in an increased electric field which is introducing most of the reliability concerns. Four most important reliability issues impacting circuit design are hot carrier injection, bias temperature instability, time-dependent dielectric breakdown and self-heating. As the second-generation current controlled conveyor (CCCII) circuit are used to implement oscillator, filter clock and so on, which are working continuously even in sleep mode. So it is important to take care of all the reliability aspects while designing CCCII. There is a challenge in complex design to identify which devices (MOS, resistor and capacitor) are susceptible to degradation and then redesign and mitigate this effect for a robust and reliable design. The objective of this work is to detect reliability issues and design a programmable current conveyor which can work safely for a long duration. The circuit has been designed and simulated using 28 nm CMOS technology model parameters on Cadence Virtuoso/AMS environment (ELDO simulator) using ± 1.8 V supply voltage and results have been verified with post-layout netlist.
{"title":"Programmable CCCII: reliability analysis and design methodology","authors":"M. K. Tiwari, N. Pandey, S. K. Paul, Saiyid Mohammad Irshad Rizvi","doi":"10.1049/IET-CDS.2018.5165","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5165","url":null,"abstract":"In this study, an effective and efficient approach for reliability analysis is developed to bridge the gap between device-level reliability and that at the product level. Continual reduction of device dimensions, gate-oxide and increase in channel doping results in an increased electric field which is introducing most of the reliability concerns. Four most important reliability issues impacting circuit design are hot carrier injection, bias temperature instability, time-dependent dielectric breakdown and self-heating. As the second-generation current controlled conveyor (CCCII) circuit are used to implement oscillator, filter clock and so on, which are working continuously even in sleep mode. So it is important to take care of all the reliability aspects while designing CCCII. There is a challenge in complex design to identify which devices (MOS, resistor and capacitor) are susceptible to degradation and then redesign and mitigate this effect for a robust and reliable design. The objective of this work is to detect reliability issues and design a programmable current conveyor which can work safely for a long duration. The circuit has been designed and simulated using 28 nm CMOS technology model parameters on Cadence Virtuoso/AMS environment (ELDO simulator) using ± 1.8 V supply voltage and results have been verified with post-layout netlist.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118583239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-03DOI: 10.1049/iet-cds.2018.5112
Nevena R. Brnovic, I. Djurović, Veselin N. Ivanović, M. Simeunović
Flexible, multiple-clock-cycle, hardware design for the quasi-maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.
{"title":"Hardware implementation of the quasi-maximum likelihood estimator core for polynomial phase signals","authors":"Nevena R. Brnovic, I. Djurović, Veselin N. Ivanović, M. Simeunović","doi":"10.1049/iet-cds.2018.5112","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.5112","url":null,"abstract":"Flexible, multiple-clock-cycle, hardware design for the quasi-maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119080594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-26DOI: 10.1049/iet-cds.2018.5148
Ashima Gupta, Anil Singh, A. Agarwal
This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.
{"title":"Highly-digital voltage scalable 4-bit flash ADC","authors":"Ashima Gupta, Anil Singh, A. Agarwal","doi":"10.1049/iet-cds.2018.5148","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.5148","url":null,"abstract":"This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120714765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-30DOI: 10.1049/iet-cds.2018.5166
Guishu Liang, Zheng Qi
Fractional-order circuits find a widespread use in different engineering applications. The problem of realising fractional-order circuits has been discussed by several authors, however, it is far from being solved. Realising fractional-order resistorless passive network with three element orders is been studied. At first, this study extends the two-variable reactance matrix synthesis method to three-variable case, and then proposes a synthesis method of fractional-order reactance matrix with three element orders by variable substitution. The process in above methods mainly involves variable substitution, decomposition of three-variable reactance matrix, extraction of unit inductors, Laurent series expansion, spectral factorisation of two-variable positive semidefinite Hermitian matrix and synthesis of univariable reactance matrix. Then the above-mentioned synthesis process is illustrated by two examples.
{"title":"Synthesis of passive fractional-order LC n-port with three element orders","authors":"Guishu Liang, Zheng Qi","doi":"10.1049/iet-cds.2018.5166","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.5166","url":null,"abstract":"Fractional-order circuits find a widespread use in different engineering applications. The problem of realising fractional-order circuits has been discussed by several authors, however, it is far from being solved. Realising fractional-order resistorless passive network with three element orders is been studied. At first, this study extends the two-variable reactance matrix synthesis method to three-variable case, and then proposes a synthesis method of fractional-order reactance matrix with three element orders by variable substitution. The process in above methods mainly involves variable substitution, decomposition of three-variable reactance matrix, extraction of unit inductors, Laurent series expansion, spectral factorisation of two-variable positive semidefinite Hermitian matrix and synthesis of univariable reactance matrix. Then the above-mentioned synthesis process is illustrated by two examples.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117903721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-13DOI: 10.1049/iet-cds.2018.5033
F. A. Khanday, Mohammad Rafiq Dar, N. A. Kant, J. Rosselló, C. Psychalinos
Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.
{"title":"0.65 V integrable electronic realisation of integer- and fractional-order Hindmarsh-Rose neuron model using companding technique","authors":"F. A. Khanday, Mohammad Rafiq Dar, N. A. Kant, J. Rosselló, C. Psychalinos","doi":"10.1049/iet-cds.2018.5033","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.5033","url":null,"abstract":"Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118112797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-26DOI: 10.1049/iet-cds.2018.0059
Md. Sakib Hasan, S. Islam
An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G4FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G4FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G4FET circuits.
{"title":"DC modelling of SOI four-gate transistor (G4FET) for implementation in circuit simulator using multivariate regression polynomial","authors":"Md. Sakib Hasan, S. Islam","doi":"10.1049/iet-cds.2018.0059","DOIUrl":"https://doi.org/10.1049/iet-cds.2018.0059","url":null,"abstract":"An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G4FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G4FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G4FET circuits.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118304615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-15DOI: 10.1049/iet-cds.2017.0538
Mohammad Reza Nikbakhsh, E. Abiri, Hossein Ghasemian, M. Salehi
In this study, a variable gain low noise amplifier (VG-LNA) working at X band is designed and simulated in 65 nm complementary metal oxide semiconductor technology. A two-stage structure is used in the proposed VG-LNA. Besides, the current-reused technique causes a higher gain without consuming extra power. As an on-chip voltage ( V cnt ) is changed, the gain continuously and almost linearly varies. The highest gain is 27.8 dB that can be reduced to 8.3 dB almost linearly and continuously as the control voltage is increased. The lowest value of S11 is −28.2 dB at 10 GHz. Also, NF is <2.75 dB at the operating frequency range; while NF min = 1.8 dB. The highest value of third-order intercept point is 2.03 dBm that always remain larger than −10.1 dBm. The basic advantage of this structure in comparison with other similar works is that not only the key parameters remain fixed with reduction of gain, but also the operation range of V cnt is widened from 0.3 V to V dd in order to extend the gain control range to 19.5 dB. Moreover, these results are achieved in a situation that the proposed VG-LNA draws only 3.9 mA from a 1.2 V.
{"title":"Two-stage current-reused variable-gain low-noise amplifier for X-band receivers in 65 nm complementary metal oxide semiconductor technology","authors":"Mohammad Reza Nikbakhsh, E. Abiri, Hossein Ghasemian, M. Salehi","doi":"10.1049/iet-cds.2017.0538","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0538","url":null,"abstract":"In this study, a variable gain low noise amplifier (VG-LNA) working at X band is designed and simulated in 65 nm complementary metal oxide semiconductor technology. A two-stage structure is used in the proposed VG-LNA. Besides, the current-reused technique causes a higher gain without consuming extra power. As an on-chip voltage (\u0000 V cnt\u0000) is changed, the gain continuously and almost linearly varies. The highest gain is 27.8 dB that can be reduced to 8.3 dB almost linearly and continuously as the control voltage is increased. The lowest value of S11 is −28.2 dB at 10 GHz. Also, NF is <2.75 dB at the operating frequency range; while NF\u0000 min\u0000 = 1.8 dB. The highest value of third-order intercept point is 2.03 dBm that always remain larger than −10.1 dBm. The basic advantage of this structure in comparison with other similar works is that not only the key parameters remain fixed with reduction of gain, but also the operation range of V cnt\u0000 is widened from 0.3 V to V dd\u0000 in order to extend the gain control range to 19.5 dB. Moreover, these results are achieved in a situation that the proposed VG-LNA draws only 3.9 mA from a 1.2 V.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117845898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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