Pub Date : 2017-06-08DOI: 10.1049/iet-cds.2016.0287
S. Saxena, R. Mehra
Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.
{"title":"Low-power and high-speed 13T SRAM cell using FinFETs","authors":"S. Saxena, R. Mehra","doi":"10.1049/iet-cds.2016.0287","DOIUrl":"https://doi.org/10.1049/iet-cds.2016.0287","url":null,"abstract":"Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118855093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-06DOI: 10.1049/iet-cds.2016.0434
L. Albasha, O. Hammi
Radio-frequency integrated circuits (RFICs) design and fabrication require sets of skills that are professionally earned through years of hands-on experiences in a developed industrial environment such as fabless design houses. Difficult design specifications, dynamic working environment, and tight deadlines in ruthless time cycles of design to mass production are all, but few examples that academia often fails to train young engineers to face. In general, no skill-based education can be easily found for fresh graduates interested in a career in IC design. As part of an industry-oriented graduate course in RFIC, students were introduced into industry design flow through lectures and major project assignments. The latter were selected to form an integrated design flow that ultimately leads to the design of a full RFIC. Students were offered to select design blocks as projects and were given specifications to meet, extracted from a transceiver architecture study. The outcome of the work showed an interesting trend of students starting their design in individual efforts, but later clustering together in team effort to match their designs together and to finish their tasks at the fictitious tape-out deadline.
{"title":"Introducing industrial design flow of an RFIC chip to a graduate course: building the ecosystem and bridging the gap between industry and academia","authors":"L. Albasha, O. Hammi","doi":"10.1049/iet-cds.2016.0434","DOIUrl":"https://doi.org/10.1049/iet-cds.2016.0434","url":null,"abstract":"Radio-frequency integrated circuits (RFICs) design and fabrication require sets of skills that are professionally earned through years of hands-on experiences in a developed industrial environment such as fabless design houses. Difficult design specifications, dynamic working environment, and tight deadlines in ruthless time cycles of design to mass production are all, but few examples that academia often fails to train young engineers to face. In general, no skill-based education can be easily found for fresh graduates interested in a career in IC design. As part of an industry-oriented graduate course in RFIC, students were introduced into industry design flow through lectures and major project assignments. The latter were selected to form an integrated design flow that ultimately leads to the design of a full RFIC. Students were offered to select design blocks as projects and were given specifications to meet, extracted from a transceiver architecture study. The outcome of the work showed an interesting trend of students starting their design in individual efforts, but later clustering together in team effort to match their designs together and to finish their tasks at the fictitious tape-out deadline.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120769915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-07DOI: 10.1049/iet-cds.2017.0047
Tapabrata Sen, Anoop Chandrika Sreekantan, S. Sen
This study presents two simple and efficient linearisation circuits for giant magneto-resistance (GMR)-based magnetic field sensors. GMR sensors are commonly available in wheatstone-bridge form, comprising two active GMR and two passive GMR elements. The output of such a sensor possesses a non-linear dependence on the input magnetic field. The proposed linearisation circuits operate on the output of a GMR sensor and provide a linear output with respect to the magnetic field. The first GMR linearisation circuit (GLC1) is based on an enhanced feedback compensation approach, while the second (GLC2) scheme uses a constant current technique. The methodologies of the schemes are described using mathematical derivations. Detailed analyses of the schemes are carried out to bring out the effects of circuit and sensor non-idealities on circuit performance. Further, the circuits were implemented on printed circuit boards and tested. Test results showed the capability of GLC1 and GLC2 to produce linear transfer characteristics. A prototype GMR sensor unit was then fabricated and tested with the developed circuits. Output non-linearity obtained during the experimentation was around 0.7%. Analyses of the results proved the superior performance of GLC1 and GLC2 over the existing schemes.
{"title":"Design and performance evaluation of two novel linearisation circuits for giant magneto-resistance based sensors","authors":"Tapabrata Sen, Anoop Chandrika Sreekantan, S. Sen","doi":"10.1049/iet-cds.2017.0047","DOIUrl":"https://doi.org/10.1049/iet-cds.2017.0047","url":null,"abstract":"This study presents two simple and efficient linearisation circuits for giant magneto-resistance (GMR)-based magnetic field sensors. GMR sensors are commonly available in wheatstone-bridge form, comprising two active GMR and two passive GMR elements. The output of such a sensor possesses a non-linear dependence on the input magnetic field. The proposed linearisation circuits operate on the output of a GMR sensor and provide a linear output with respect to the magnetic field. The first GMR linearisation circuit (GLC1) is based on an enhanced feedback compensation approach, while the second (GLC2) scheme uses a constant current technique. The methodologies of the schemes are described using mathematical derivations. Detailed analyses of the schemes are carried out to bring out the effects of circuit and sensor non-idealities on circuit performance. Further, the circuits were implemented on printed circuit boards and tested. Test results showed the capability of GLC1 and GLC2 to produce linear transfer characteristics. A prototype GMR sensor unit was then fabricated and tested with the developed circuits. Output non-linearity obtained during the experimentation was around 0.7%. Analyses of the results proved the superior performance of GLC1 and GLC2 over the existing schemes.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119893761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1049/iet-cds.2015.0359
L. Wen, Haibo Wen, Xiaoyang Zeng
A new sub-threshold level shifter for ultra-low voltage digital systems is presented in this study. The self-controlled supply feedback loop is quintessential for this circuit. Measured results from a test chip show that it is capable of realising a voltage conversion from a voltage as low as 0.1-1.2 V reliably, while maintaining an operational frequency of 25.2 kHz, when implemented in a 65-nm process technology. In addition, it also has ample process variation tolerance and low static power consumption. To support multi-voltage digital systems, the proposed level converter can up-convert an input at any voltage with this range to normal voltage domains.
{"title":"Sub-threshold level converter with internal supply feedback for multi-voltage applications","authors":"L. Wen, Haibo Wen, Xiaoyang Zeng","doi":"10.1049/iet-cds.2015.0359","DOIUrl":"https://doi.org/10.1049/iet-cds.2015.0359","url":null,"abstract":"A new sub-threshold level shifter for ultra-low voltage digital systems is presented in this study. The self-controlled supply feedback loop is quintessential for this circuit. Measured results from a test chip show that it is capable of realising a voltage conversion from a voltage as low as 0.1-1.2 V reliably, while maintaining an operational frequency of 25.2 kHz, when implemented in a 65-nm process technology. In addition, it also has ample process variation tolerance and low static power consumption. To support multi-voltage digital systems, the proposed level converter can up-convert an input at any voltage with this range to normal voltage domains.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120639598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-09DOI: 10.1049/iet-cds.2014.0130
T. Sánchez-Rodríguez, J. Galán, M. Pedro, A. López-Martín, R. Carvajal, J. Ramírez-Angulo
A CMOS variable gain amplifier (VGA) based on a novel linear and tunable triode transconductor is presented. The proposed transconductor employs local negative feedback for linearisation controlling the drain voltage of the input transistors biased in the triode region. The new design is able to operate at low supply voltage and the stability is guaranteed. The transconductor features a 47.75 dB dc gain and a 4.23 MHz unity gain frequency with a power consumption of only 91 µA. To show the feasibility of the proposed transconductor, a VGA has been fabricated. Measurement results for a 0.13 µm CMOS design show a −3 dB bandwidth above 2.8 MHz and a third-order harmonic distortion at 500 kHz below −46 dB over the whole gain range. The VGA exhibits a maximum power consumption of only 395 µW from a single 1.2 V supply.
{"title":"Low-power CMOS variable gain amplifier based on a novel tunable transconductor","authors":"T. Sánchez-Rodríguez, J. Galán, M. Pedro, A. López-Martín, R. Carvajal, J. Ramírez-Angulo","doi":"10.1049/iet-cds.2014.0130","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0130","url":null,"abstract":"A CMOS variable gain amplifier (VGA) based on a novel linear and tunable triode transconductor is presented. The proposed transconductor employs local negative feedback for linearisation controlling the drain voltage of the input transistors biased in the triode region. The new design is able to operate at low supply voltage and the stability is guaranteed. The transconductor features a 47.75 dB dc gain and a 4.23 MHz unity gain frequency with a power consumption of only 91 µA. To show the feasibility of the proposed transconductor, a VGA has been fabricated. Measurement results for a 0.13 µm CMOS design show a −3 dB bandwidth above 2.8 MHz and a third-order harmonic distortion at 500 kHz below −46 dB over the whole gain range. The VGA exhibits a maximum power consumption of only 395 µW from a single 1.2 V supply.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134241541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-09DOI: 10.1049/iet-cds.2014.0202
S. Karmakar, M. Gogna, E. Suarez, F. Jain
This paper presents the observation of intermediate state in the quantum dot gate field-effect transistors (QDGFETs) in silicon-on-insulator (SOI) substrate. Silicon dioxide (SiO2)-cladded silicon (Si) quantum dots (QDs) are site-specifically self-assembled on the top of SiO2 tunnel gate insulator on SOI substrates. Charge carrier tunnelling from the inversion channel to the QD layers on top of the gate insulator is responsible for the generation of intermediate state. Charge tunnelling is also verified by the C–V characteristics of the MOS device having same insulator structure as the gate region of the QDGFET. Considering the transfer of charge carriers from the inversion channel to two layers of SiO2-cladded Si QDs, a model based on self-consistent solution of Schrodinger and Poisson equations, is also presented, to explain the generation of intermediate state.
{"title":"Three-state quantum dot gate field-effect transistor in silicon-on-insulator","authors":"S. Karmakar, M. Gogna, E. Suarez, F. Jain","doi":"10.1049/iet-cds.2014.0202","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0202","url":null,"abstract":"This paper presents the observation of intermediate state in the quantum dot gate field-effect transistors (QDGFETs) in silicon-on-insulator (SOI) substrate. Silicon dioxide (SiO2)-cladded silicon (Si) quantum dots (QDs) are site-specifically self-assembled on the top of SiO2 tunnel gate insulator on SOI substrates. Charge carrier tunnelling from the inversion channel to the QD layers on top of the gate insulator is responsible for the generation of intermediate state. Charge tunnelling is also verified by the C–V characteristics of the MOS device having same insulator structure as the gate region of the QDGFET. Considering the transfer of charge carriers from the inversion channel to two layers of SiO2-cladded Si QDs, a model based on self-consistent solution of Schrodinger and Poisson equations, is also presented, to explain the generation of intermediate state.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131237725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-09DOI: 10.1049/iet-cds.2014.0089
Giray Kömürcü, A. E. Pusane, Günhan Dündar
The number of applicable challenge–response pairs (CRPs) in physical unclonable functions (PUFs) is critical especially for authentication protocols in security systems. Ideally, full read-out of all CRPs should be infeasible and CRPs should be independent from each other for a highly secure system. CRP concept is not defined in ordering-based ring oscillator (RO) PUFs presented in the literature. In this paper, the authors propose two methods for enhanced CRP set in ordering-based RO-PUFs and analyse their performance in terms of uniqueness and area efficiency. Next, they propose three secure usage scenarios based on enhanced CRP set methods, preventing the CRPs from leaking information about each other. With the proposed systems, 100% robust, area and power efficient and secure PUF structures with exponential number of CRPs become possible that are very convenient especially for authentication protocols.
{"title":"Enhanced challenge-response set and secure usage scenarios for ordering-based ring oscillator-physical unclonable functions","authors":"Giray Kömürcü, A. E. Pusane, Günhan Dündar","doi":"10.1049/iet-cds.2014.0089","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0089","url":null,"abstract":"The number of applicable challenge–response pairs (CRPs) in physical unclonable functions (PUFs) is critical especially for authentication protocols in security systems. Ideally, full read-out of all CRPs should be infeasible and CRPs should be independent from each other for a highly secure system. CRP concept is not defined in ordering-based ring oscillator (RO) PUFs presented in the literature. In this paper, the authors propose two methods for enhanced CRP set in ordering-based RO-PUFs and analyse their performance in terms of uniqueness and area efficiency. Next, they propose three secure usage scenarios based on enhanced CRP set methods, preventing the CRPs from leaking information about each other. With the proposed systems, 100% robust, area and power efficient and secure PUF structures with exponential number of CRPs become possible that are very convenient especially for authentication protocols.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-09DOI: 10.1049/IET-CDS.2013.0438
Matteo Biggio, F. Bizzarri, A. Brambilla, M. Storace
This paper proposes a numerical method for accurate time-domain noise simulation of mixed analogue/digital electrical circuits that in principle do not admit a periodic steady-state working condition, such as fractional ΔΣ phase-locked loops (PLLs). By means of a tool known as saltation matrix, which allows dealing with non-smooth vector fields, a variational approach is adopted. The power spectral density of a noisy electrical variable is computed by applying the Thomson's multitaper method (MTM) to the numerical solution of the stochastic variational model of the circuit. This allows to resort to a single transient simulation run, thus avoiding cpu time consuming Monte-Carlo-like approaches. The effectiveness of the proposed method is shown by comparing simulation results related to a commercial fractional ΔΣ PLL with experimental data.
{"title":"Efficient transient noise analysis of non-periodic mixed analogue/digital circuits","authors":"Matteo Biggio, F. Bizzarri, A. Brambilla, M. Storace","doi":"10.1049/IET-CDS.2013.0438","DOIUrl":"https://doi.org/10.1049/IET-CDS.2013.0438","url":null,"abstract":"This paper proposes a numerical method for accurate time-domain noise simulation of mixed analogue/digital electrical circuits that in principle do not admit a periodic steady-state working condition, such as fractional ΔΣ phase-locked loops (PLLs). By means of a tool known as saltation matrix, which allows dealing with non-smooth vector fields, a variational approach is adopted. The power spectral density of a noisy electrical variable is computed by applying the Thomson's multitaper method (MTM) to the numerical solution of the stochastic variational model of the circuit. This allows to resort to a single transient simulation run, thus avoiding cpu time consuming Monte-Carlo-like approaches. The effectiveness of the proposed method is shown by comparing simulation results related to a commercial fractional ΔΣ PLL with experimental data.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125681840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-09DOI: 10.1049/iet-cds.2014.0019
Debashis Mandal, P. Mandal, T. K. Bhattacharyya
This paper reports an analytical approach to predict the reference spur of a conventional frequency synthesiser more accurately in comparison with the existing technique where the ripple voltage waveform at voltage controlled oscillator input is approximated by narrow rectangular pulse. In this work, the ripple voltage waveform is represented by a combination of triangular and rectangular pulses. Transistor level SPICE simulations show that using the proposed approach, the error in the predicted spur has been reduced from about 29.84 to 0.64 dB. Measured result shows 4.39 dB error in the predicted spur. The derived expression has been extended further to predict the spur in frequency synthesisers having pulse repetition-based spur reducing technique including the repetition mismatch.
{"title":"Prediction of reference spur in frequency synthesisers","authors":"Debashis Mandal, P. Mandal, T. K. Bhattacharyya","doi":"10.1049/iet-cds.2014.0019","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0019","url":null,"abstract":"This paper reports an analytical approach to predict the reference spur of a conventional frequency synthesiser more accurately in comparison with the existing technique where the ripple voltage waveform at voltage controlled oscillator input is approximated by narrow rectangular pulse. In this work, the ripple voltage waveform is represented by a combination of triangular and rectangular pulses. Transistor level SPICE simulations show that using the proposed approach, the error in the predicted spur has been reduced from about 29.84 to 0.64 dB. Measured result shows 4.39 dB error in the predicted spur. The derived expression has been extended further to predict the spur in frequency synthesisers having pulse repetition-based spur reducing technique including the repetition mismatch.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133831438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-09DOI: 10.1049/iet-cds.2013.0424
Yushi Zhou, F. Yuan
This study presents a Volterra series approach to analyse injection-locked non-harmonic oscillators. We show that by depicting the voltage transfer characteristics of comparators using hyperbolic tangent functions, non-harmonic oscillators can be analysed analytically using a set of Volterra circuits that are linear, have the same topology and element values but different inputs. We further show that the larger lock range of non-harmonic oscillators as compared with that of their harmonic counterparts is because of the harsher non-linear characteristics of these oscillators and the lower-order attenuation of the high-order frequency components of the oscillators. The reduced non-linear characteristics of ring oscillators because of the absence of positive feedback also gives rise to a smaller lock range as compared with relaxation oscillators. These theoretical findings are validated using both the simulation results of relaxation oscillators and ring oscillators designed in IBM 130 nm complementary metal oxide semiconductor technology and the measurement results of ring oscillators implemented using commercial ICs.
{"title":"Study of injection-locked non-harmonic oscillators using Volterra series","authors":"Yushi Zhou, F. Yuan","doi":"10.1049/iet-cds.2013.0424","DOIUrl":"https://doi.org/10.1049/iet-cds.2013.0424","url":null,"abstract":"This study presents a Volterra series approach to analyse injection-locked non-harmonic oscillators. We show that by depicting the voltage transfer characteristics of comparators using hyperbolic tangent functions, non-harmonic oscillators can be analysed analytically using a set of Volterra circuits that are linear, have the same topology and element values but different inputs. We further show that the larger lock range of non-harmonic oscillators as compared with that of their harmonic counterparts is because of the harsher non-linear characteristics of these oscillators and the lower-order attenuation of the high-order frequency components of the oscillators. The reduced non-linear characteristics of ring oscillators because of the absence of positive feedback also gives rise to a smaller lock range as compared with relaxation oscillators. These theoretical findings are validated using both the simulation results of relaxation oscillators and ring oscillators designed in IBM 130 nm complementary metal oxide semiconductor technology and the measurement results of ring oscillators implemented using commercial ICs.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126484522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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