Pub Date : 2013-09-19DOI: 10.1049/iet-cds.2013.0026
Bing Shi, Ankur Srivastava, A. Bar-Cohen
Three-dimensional integrated circuits (3D-ICs) bring about new challenges to chip thermal management because of their high heat densities. Micro-channel-based liquid cooling and thermal through-silicon-vias (TSVs) have been adopted to alleviate the thermal issues in 3D-ICs. Thermal TSV enables higher interlayer thermal conductivity thereby achieving a more uniform thermal profile. Although somewhat effective in reducing temperatures, they are limited by the nature of the heat sink. On the other hand, micro-channel-based liquid cooling is significantly capable of addressing 3D-IC cooling needs, but consumes a lot of extra power for pumping coolant through channels. This study proposes a hybrid 3D-IC cooling scheme which combines micro-channel liquid cooling and thermal TSV with one acting as heat removal agent, whereas the other enabling beneficial heat conduction paths to the micro-channel structures. The experimental results show that the proposed hybrid cooling scheme provides much better cooling capability than using only thermal TSVs, although consuming 56% less cooling power compared with pure micro-channel cooling.
{"title":"Co-design of micro-fluidic heat sink and thermal through-silicon-vias for cooling of three-dimensional integrated circuit","authors":"Bing Shi, Ankur Srivastava, A. Bar-Cohen","doi":"10.1049/iet-cds.2013.0026","DOIUrl":"https://doi.org/10.1049/iet-cds.2013.0026","url":null,"abstract":"Three-dimensional integrated circuits (3D-ICs) bring about new challenges to chip thermal management because of their high heat densities. Micro-channel-based liquid cooling and thermal through-silicon-vias (TSVs) have been adopted to alleviate the thermal issues in 3D-ICs. Thermal TSV enables higher interlayer thermal conductivity thereby achieving a more uniform thermal profile. Although somewhat effective in reducing temperatures, they are limited by the nature of the heat sink. On the other hand, micro-channel-based liquid cooling is significantly capable of addressing 3D-IC cooling needs, but consumes a lot of extra power for pumping coolant through channels. This study proposes a hybrid 3D-IC cooling scheme which combines micro-channel liquid cooling and thermal TSV with one acting as heat removal agent, whereas the other enabling beneficial heat conduction paths to the micro-channel structures. The experimental results show that the proposed hybrid cooling scheme provides much better cooling capability than using only thermal TSVs, although consuming 56% less cooling power compared with pure micro-channel cooling.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119458169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-19DOI: 10.1049/iet-cds.2012.0358
Oghenekarho Okobiah, S. Mohanty, E. Kougianos
Continuous and aggressive scaling of semiconductor technology has led to persistent and dominant nanoscale effects on analogue/mixed-signal (AMS) circuits. Design space exploration and optimisation costs using conventional techniques have increased to infeasible levels. Hence, growing research for alternative design and metamodelling techniques with a much reduced design space exploration and optimisation cost and high level of accuracy, continues to be very active. This study presents a geostatistical inspired metamodelling and optimisation technique for fast and accurate design optimisation of nano-complementary metal oxide semiconductor (CMOS) circuits. The design methodology proposed integrates a simple Kriging technique with efficient and accurate prediction characteristics as the metamodel generation technique. A gravitational search algorithm (GSA) is applied on the generated metamodel (substituted for the circuit netlist) to solve the design optimisation problem. The proposed methodology is applicable to AMS circuits and systems. Its effectiveness is illustrated with the optimisation of a 45 nm CMOS thermal sensor. With six design parameters, the design optimisation time for the thermal sensor is decreased by 90% and produces an improvement of 36.8% in power consumption. To the best of the authors' knowledge this is the first work to use GSA for analogue design optimisation.
{"title":"Geostatistical-inspired fast layout optimisation of a nano-CMOS thermal sensor","authors":"Oghenekarho Okobiah, S. Mohanty, E. Kougianos","doi":"10.1049/iet-cds.2012.0358","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0358","url":null,"abstract":"Continuous and aggressive scaling of semiconductor technology has led to persistent and dominant nanoscale effects on analogue/mixed-signal (AMS) circuits. Design space exploration and optimisation costs using conventional techniques have increased to infeasible levels. Hence, growing research for alternative design and metamodelling techniques with a much reduced design space exploration and optimisation cost and high level of accuracy, continues to be very active. This study presents a geostatistical inspired metamodelling and optimisation technique for fast and accurate design optimisation of nano-complementary metal oxide semiconductor (CMOS) circuits. The design methodology proposed integrates a simple Kriging technique with efficient and accurate prediction characteristics as the metamodel generation technique. A gravitational search algorithm (GSA) is applied on the generated metamodel (substituted for the circuit netlist) to solve the design optimisation problem. The proposed methodology is applicable to AMS circuits and systems. Its effectiveness is illustrated with the optimisation of a 45 nm CMOS thermal sensor. With six design parameters, the design optimisation time for the thermal sensor is decreased by 90% and produces an improvement of 36.8% in power consumption. To the best of the authors' knowledge this is the first work to use GSA for analogue design optimisation.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118215775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-20DOI: 10.1049/iet-cds.2012.0249
Guohuan Hua, Weifeng Sun, Xiaoying He, Shen Xu, Zhiqun Li
An analytical model is proposed to analyse the energy recovery circuit (ERC) efficiency of plasma display panel (PDP) data driver integrated circuit (IC). The experimental measurements agree with the analysis results very well. The analysis results show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time T ERC , the channel resistor R on and the capacitance of C L . The range of T ERC is restricted in actual PDP system. C L is determined by physical parameters of PDP panel, and its value is nearly changeless. Therefore the ERC efficiency of PDP data driver IC can be improved significantly by using superior DPLD (double-channel p-type lateral extended drain metal oxidesemi conductor) transistor that has smaller R on .
{"title":"Analytical model for energy recovery circuit of plasma display panel data driver integrated circuit","authors":"Guohuan Hua, Weifeng Sun, Xiaoying He, Shen Xu, Zhiqun Li","doi":"10.1049/iet-cds.2012.0249","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0249","url":null,"abstract":"An analytical model is proposed to analyse the energy recovery circuit (ERC) efficiency of plasma display panel (PDP) data driver integrated circuit (IC). The experimental measurements agree with the analysis results very well. The analysis results show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time T ERC , the channel resistor R on and the capacitance of C L . The range of T ERC is restricted in actual PDP system. C L is determined by physical parameters of PDP panel, and its value is nearly changeless. Therefore the ERC efficiency of PDP data driver IC can be improved significantly by using superior DPLD (double-channel p-type lateral extended drain metal oxidesemi conductor) transistor that has smaller R on .","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118589465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-01DOI: 10.1049/iet-cds.2012.0270
Tong-Ho Chung, Hee-Do Kang, J. Yook
This study presents a new equivalent circuit modelling methodology for various-type spiral resonators in printed circuit board environment. The N-turn spiral resonator can be decomposed into an N Π-equivalent circuit model, and each Π-model is comprised of a series inductance, parallel capacitance, two shunt capacitors and the resistances of the conductor and dielectric. Both the inductance and capacitance of the equivalent circuit are calculated by the proposed formulas, which are based on the electromagnetic theory. It has been demonstrated that the proposed equivalent circuit model of the spiral resonator is well matched in S-parameters, Q-factor and inductance values as well as in self-resonance frequency values within 8% tolerance with measurement and full-wave electromagnetic field solver.
{"title":"Broadband equivalent circuit modelling of spiral resonators for printed circuit board applications","authors":"Tong-Ho Chung, Hee-Do Kang, J. Yook","doi":"10.1049/iet-cds.2012.0270","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0270","url":null,"abstract":"This study presents a new equivalent circuit modelling methodology for various-type spiral resonators in printed circuit board environment. The N-turn spiral resonator can be decomposed into an N Π-equivalent circuit model, and each Π-model is comprised of a series inductance, parallel capacitance, two shunt capacitors and the resistances of the conductor and dielectric. Both the inductance and capacitance of the equivalent circuit are calculated by the proposed formulas, which are based on the electromagnetic theory. It has been demonstrated that the proposed equivalent circuit model of the spiral resonator is well matched in S-parameters, Q-factor and inductance values as well as in self-resonance frequency values within 8% tolerance with measurement and full-wave electromagnetic field solver.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120707641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2011.0360
Hossein Karimiyan Alidash, A. Calimera, A. Macii, E. Macii, M. Poncino
In sub-nanometer complementary metal oxide semiconductor (CMOS) technologies, process variability strongly affects the fabrication yield. To face this problem, post-silicon adaptive approaches have been proposed as a promising solution. However, their actual implementation requires the availability of effective monitoring architectures that can sense and sample process variation across the die. In this study, the authors present a sensor circuit for capturing on-chip variations owing to the fabrication process. The proposed solution is based on the concept of ‘variation amplification’ and uses the propagation delay measurement through a pass-transistor chain. Our monitor architecture, which consists of a self-contained cell containing N- and P-type sensors along with an all-digital delay measurement circuitry, is able to capture local variations of negative metal oxide semiconductors and positive metal oxide semiconductors transistors individually, therefore enabling fine tuning of the circuit. The authors also propose an array-based integration of the monitors, where the sensors are placed in a different location of the die and connected together with the scan–chain to distribute the sampled data. Detailed SPICE level simulations conducted on an industrial 45-nm CMOS technology demonstrate the sensing capability of the proposed architecture and the effectiveness of the on-chip all-digital measurement process.
{"title":"On-chip process variation-tracking through an all-digital monitoring architecture","authors":"Hossein Karimiyan Alidash, A. Calimera, A. Macii, E. Macii, M. Poncino","doi":"10.1049/iet-cds.2011.0360","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0360","url":null,"abstract":"In sub-nanometer complementary metal oxide semiconductor (CMOS) technologies, process variability strongly affects the fabrication yield. To face this problem, post-silicon adaptive approaches have been proposed as a promising solution. However, their actual implementation requires the availability of effective monitoring architectures that can sense and sample process variation across the die. In this study, the authors present a sensor circuit for capturing on-chip variations owing to the fabrication process. The proposed solution is based on the concept of ‘variation amplification’ and uses the propagation delay measurement through a pass-transistor chain. Our monitor architecture, which consists of a self-contained cell containing N- and P-type sensors along with an all-digital delay measurement circuitry, is able to capture local variations of negative metal oxide semiconductors and positive metal oxide semiconductors transistors individually, therefore enabling fine tuning of the circuit. The authors also propose an array-based integration of the monitors, where the sensors are placed in a different location of the die and connected together with the scan–chain to distribute the sampled data. Detailed SPICE level simulations conducted on an industrial 45-nm CMOS technology demonstrate the sensing capability of the proposed architecture and the effectiveness of the on-chip all-digital measurement process.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127429637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2011.0322
T. Matić, T. Svedek, D. Vinko
Hysteretic comparator (Schmitt trigger) is the basic part of the asynchronous sigma-delta modulator (ASDM). If propagation delay of a hysteretic comparator is not equal to zero and it has measurable value, than it affects the ASDM output frequency spectrum. As ASDM is a circuit with serial connection of an integrator and a hysteretic comparator followed by a negative feedback loop, propagation delay of the comparator will introduce the timing errors in ASDM output signal-triggering events. Therefore ASDM central frequency will be lower then it is in the case for propagation delay equal to zero. This study provides mathematical analysis of the hysteretic comparator propagation delay influence to the ASDM output frequency spectrum. The method for ASDM central frequency improvement using integrator voltage clamping has been proposed. Mathematical analysis, together with simulation and measurement results, shows partial central frequency increment. As ASDM circuit can be used as an oscillator for zero-input signals, central frequency improvement can be significant.
{"title":"Integrator clamping for asynchronous sigma-delta modulator central frequency increment","authors":"T. Matić, T. Svedek, D. Vinko","doi":"10.1049/iet-cds.2011.0322","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0322","url":null,"abstract":"Hysteretic comparator (Schmitt trigger) is the basic part of the asynchronous sigma-delta modulator (ASDM). If propagation delay of a hysteretic comparator is not equal to zero and it has measurable value, than it affects the ASDM output frequency spectrum. As ASDM is a circuit with serial connection of an integrator and a hysteretic comparator followed by a negative feedback loop, propagation delay of the comparator will introduce the timing errors in ASDM output signal-triggering events. Therefore ASDM central frequency will be lower then it is in the case for propagation delay equal to zero. This study provides mathematical analysis of the hysteretic comparator propagation delay influence to the ASDM output frequency spectrum. The method for ASDM central frequency improvement using integrator voltage clamping has been proposed. Mathematical analysis, together with simulation and measurement results, shows partial central frequency increment. As ASDM circuit can be used as an oscillator for zero-input signals, central frequency improvement can be significant.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121820781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2012.0011
A. Dogan, J. Constantin, David Atienza Alonso, A. Burg, L. Benini
In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations exist. To this end, a single- and a multi-core architecture are proposed and compared. The single-core architecture is composed of one ULP processing core, an instruction memory (IM) and a data memory (DM), while the multi-core architecture consists of several ULP processing cores, individual IMs for each core, a shared DM and an interconnection crossbar between the cores and the DM. These architectures are compared with respect to power/performance trade-offs for different target workloads of online biomedical signal analysis, while exploiting near threshold computing. The results show that with respect to the single-core architecture, the multi-core solution consumes 62% less power for high computation requirements (167 MOps/s), while consuming 46% more power for extremely low computation needs when the power consumption is dominated by leakage. Additionally, the authors show that the proposed ULP processing core, using a simplified instruction set architecture (ISA), achieves energy savings of 54% compared to a reference microcontroller ISA (PIC24).
{"title":"Low-power processor architecture exploration for online biomedical signal analysis","authors":"A. Dogan, J. Constantin, David Atienza Alonso, A. Burg, L. Benini","doi":"10.1049/iet-cds.2012.0011","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0011","url":null,"abstract":"In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations exist. To this end, a single- and a multi-core architecture are proposed and compared. The single-core architecture is composed of one ULP processing core, an instruction memory (IM) and a data memory (DM), while the multi-core architecture consists of several ULP processing cores, individual IMs for each core, a shared DM and an interconnection crossbar between the cores and the DM. These architectures are compared with respect to power/performance trade-offs for different target workloads of online biomedical signal analysis, while exploiting near threshold computing. The results show that with respect to the single-core architecture, the multi-core solution consumes 62% less power for high computation requirements (167 MOps/s), while consuming 46% more power for extremely low computation needs when the power consumption is dominated by leakage. Additionally, the authors show that the proposed ULP processing core, using a simplified instruction set architecture (ISA), achieves energy savings of 54% compared to a reference microcontroller ISA (PIC24).","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134267848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/IET-CDS.2011.0350
Ignacio Arnaldo, J. L. Risco-Martín, J. Ayala, J. Hidalgo
Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.
{"title":"Power profiling-guided floorplanner for 3D multi-processor systems-on-chip","authors":"Ignacio Arnaldo, J. L. Risco-Martín, J. Ayala, J. Hidalgo","doi":"10.1049/IET-CDS.2011.0350","DOIUrl":"https://doi.org/10.1049/IET-CDS.2011.0350","url":null,"abstract":"Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134440071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2011.0348
H. Aghababa, A. Khosropour, A. Afzali-Kusha, B. Forouzandeh, Massoud Pedram
In this study, the authors present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale complementary metal oxide semiconductor (CMOS) technologies. The technique, which is additive with respect to the individual gate leakage values, employs a generalised extreme value (GEV) distribution. Compared with the previous methods based on (two-parameter) lognormal distribution, this method uses the GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of the circuits may be modelled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared with the case of the lognormal distribution based on the additive approach.
{"title":"Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution","authors":"H. Aghababa, A. Khosropour, A. Afzali-Kusha, B. Forouzandeh, Massoud Pedram","doi":"10.1049/iet-cds.2011.0348","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0348","url":null,"abstract":"In this study, the authors present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale complementary metal oxide semiconductor (CMOS) technologies. The technique, which is additive with respect to the individual gate leakage values, employs a generalised extreme value (GEV) distribution. Compared with the previous methods based on (two-parameter) lognormal distribution, this method uses the GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of the circuits may be modelled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared with the case of the lognormal distribution based on the additive approach.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116239324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-16DOI: 10.1049/iet-cds.2011.0369
Lars Schor, Hoeseok Yang, Iuliana Bacivarov, L. Thiele
The rapid increase in heat dissipation in real-time systems imposes various thermal issues. For instance, real-time constraints cannot be guaranteed if a certain threshold temperature is exceeded, as it would immediately reduce the system reliability and performance. Dynamic thermal management techniques are promising methods to prevent a system from overheating. However, when designing real-time systems that make use of such thermal management techniques, the designer has to be aware of their effect on both real-time constraints and worst-case peak temperature. In particular, the worst-case peak temperature of a real-time system with non-deterministic workload is the maximum possible temperature under all feasible scenarios of task arrivals. This study proposes an analytic framework to calculate the worst-case peak temperature of a system with general resource availabilities, which means that computing power might not be fully available for certain time intervals. The event and resource models are based on real-time and network calculus, and therefore, our analysis method is able to handle a broad range of uncertainties in terms of task arrivals and available computing power. Finally, we propose an indicator for the quality of the resource model with respect to worst-case peak temperature and schedulability.
{"title":"Worst-case temperature analysis for different resource models","authors":"Lars Schor, Hoeseok Yang, Iuliana Bacivarov, L. Thiele","doi":"10.1049/iet-cds.2011.0369","DOIUrl":"https://doi.org/10.1049/iet-cds.2011.0369","url":null,"abstract":"The rapid increase in heat dissipation in real-time systems imposes various thermal issues. For instance, real-time constraints cannot be guaranteed if a certain threshold temperature is exceeded, as it would immediately reduce the system reliability and performance. Dynamic thermal management techniques are promising methods to prevent a system from overheating. However, when designing real-time systems that make use of such thermal management techniques, the designer has to be aware of their effect on both real-time constraints and worst-case peak temperature. In particular, the worst-case peak temperature of a real-time system with non-deterministic workload is the maximum possible temperature under all feasible scenarios of task arrivals. This study proposes an analytic framework to calculate the worst-case peak temperature of a system with general resource availabilities, which means that computing power might not be fully available for certain time intervals. The event and resource models are based on real-time and network calculus, and therefore, our analysis method is able to handle a broad range of uncertainties in terms of task arrivals and available computing power. Finally, we propose an indicator for the quality of the resource model with respect to worst-case peak temperature and schedulability.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124882554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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