Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186076
Z. Navabi
An introduction to hardware description languages, a discussion of the emergence of VHDL as the standard HDL, and an overview of the VHDL language are given. The constructs of VHDL for design and modeling of hardware are emphasized. An overview of VHDL is given by use of a simple example which is broken into subcomponents, each of which is described at various levels of abstraction. Advanced features of VHDL are discussed, and corresponding examples are presented. These examples are used in the bottom-up design of a complete circuit.<>
{"title":"Elements of VHDL for description of hardware: a tutorial view","authors":"Z. Navabi","doi":"10.1109/ASIC.1990.186076","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186076","url":null,"abstract":"An introduction to hardware description languages, a discussion of the emergence of VHDL as the standard HDL, and an overview of the VHDL language are given. The constructs of VHDL for design and modeling of hardware are emphasized. An overview of VHDL is given by use of a simple example which is broken into subcomponents, each of which is described at various levels of abstraction. Advanced features of VHDL are discussed, and corresponding examples are presented. These examples are used in the bottom-up design of a complete circuit.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133125889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186184
A. Cron
A basic tutorial and design guide for ASIC designers building devices that conform to the IEEE Std 1149.1 architecture is presented. The circuits and concepts presented can be expanded upon for use in more complex implementations. This paper is intended to be used in conjunction with the IEEE 1149.1 specification. Implementation guidance and the specification provided rules governing proper design are presented.<>
{"title":"Designing IEEE Std 1149.1 into your semiconductor products","authors":"A. Cron","doi":"10.1109/ASIC.1990.186184","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186184","url":null,"abstract":"A basic tutorial and design guide for ASIC designers building devices that conform to the IEEE Std 1149.1 architecture is presented. The circuits and concepts presented can be expanded upon for use in more complex implementations. This paper is intended to be used in conjunction with the IEEE 1149.1 specification. Implementation guidance and the specification provided rules governing proper design are presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128323749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186121
B. Harrington
A program that automatically created emitter-coupled logic ECL and current-mode logic (CML) gate array macro models for several logic simulators is described. The program extracts the logic netlist from SPICE ECL or CML netlists, assigns timing delays supplied from external flies, optimizes the netlist and creates logic simulation models for the DAZIX's DLS, Mentor Graphic's QuickSim, and Zycad's MACH 1000 logic simulators.<>
{"title":"SPIL-a program to automatically create ASIC macro models for logic simulation","authors":"B. Harrington","doi":"10.1109/ASIC.1990.186121","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186121","url":null,"abstract":"A program that automatically created emitter-coupled logic ECL and current-mode logic (CML) gate array macro models for several logic simulators is described. The program extracts the logic netlist from SPICE ECL or CML netlists, assigns timing delays supplied from external flies, optimizes the netlist and creates logic simulation models for the DAZIX's DLS, Mentor Graphic's QuickSim, and Zycad's MACH 1000 logic simulators.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126975458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186145
Nai-Chi Lee
Analog autonomous test (AAT) is a structured design-for-testability methodology for mixed analog/digital ICs. By using analog switches and test-bus to gain controllability and observability, a chip is partitioned into testable submodules for production testing. Therefore, both test vector development period and production test time can be reduced.<>
{"title":"Autonomous test scheme for analog ASICs","authors":"Nai-Chi Lee","doi":"10.1109/ASIC.1990.186145","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186145","url":null,"abstract":"Analog autonomous test (AAT) is a structured design-for-testability methodology for mixed analog/digital ICs. By using analog switches and test-bus to gain controllability and observability, a chip is partitioned into testable submodules for production testing. Therefore, both test vector development period and production test time can be reduced.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126062289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186177
V. Immaneni, D. Puffer, S. Raman
The direct access test scheme (DATS) that eliminates the designer's burden of embedded block cell test generation is discussed. This scheme provides for testing of embedded block cells using proven test vectors. The implementation and automatic verification of DATS in ASIC designs is discussed.<>
{"title":"Direct access test scheme-implementation and verification in embedded ASIC designs","authors":"V. Immaneni, D. Puffer, S. Raman","doi":"10.1109/ASIC.1990.186177","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186177","url":null,"abstract":"The direct access test scheme (DATS) that eliminates the designer's burden of embedded block cell test generation is discussed. This scheme provides for testing of embedded block cells using proven test vectors. The implementation and automatic verification of DATS in ASIC designs is discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121854678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186206
V. Grimblatt-Hinzpeter, C. Morrison, R. S. Finley
An overview of logic synthesis and the different methodologies used in the tools realizing synthesis is presented. The objective is to show the economic implications of synthesis (performance and area of the chip, design time, silicon costs, etc.). The mainstream methodology used in synthesis tools and the possible applications are presented. Future methodologies and some ideas for the reduction of chip costs using the existing tools and possible future tools are discussed.<>
{"title":"Economic implications of logic synthesis","authors":"V. Grimblatt-Hinzpeter, C. Morrison, R. S. Finley","doi":"10.1109/ASIC.1990.186206","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186206","url":null,"abstract":"An overview of logic synthesis and the different methodologies used in the tools realizing synthesis is presented. The objective is to show the economic implications of synthesis (performance and area of the chip, design time, silicon costs, etc.). The mainstream methodology used in synthesis tools and the possible applications are presented. Future methodologies and some ideas for the reduction of chip costs using the existing tools and possible future tools are discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122025916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186088
A. Kozak, V. Little, K. Huscroft
A modular ASIC system design approach for telecommunications equipment is compared with system design utilizing conventional ASIC design approaches and standard products. The modular design approach utilizes telecom system blocks (TSBs) which are predesigned and tested telecommunication functions contained in a megacell or netlist format which represent system functions as viewed by the systems designer and have proven compliance to industry standards. The economics of each methodology are analyzed with respect to three major phases of a product's life, which include design and development, production, and cost reduction and evolution to a new generation of product.<>
{"title":"An economic comparison of telecommunication system design costs utilizing a modular design approach","authors":"A. Kozak, V. Little, K. Huscroft","doi":"10.1109/ASIC.1990.186088","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186088","url":null,"abstract":"A modular ASIC system design approach for telecommunications equipment is compared with system design utilizing conventional ASIC design approaches and standard products. The modular design approach utilizes telecom system blocks (TSBs) which are predesigned and tested telecommunication functions contained in a megacell or netlist format which represent system functions as viewed by the systems designer and have proven compliance to industry standards. The economics of each methodology are analyzed with respect to three major phases of a product's life, which include design and development, production, and cost reduction and evolution to a new generation of product.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127135413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186167
L.Y. Lu, M. D. Alston
A design methodology developed and implemented for high-pin-count cell-based BiCMOS ASIC designs is discussed. Described is the orchestration of different vendors' CAD tools via tool-specific shell scripts, macros, file reformatting/conversion software and application software to methodically place and route I/O pad cells, I/O circuit cells, and core logic megacells, rapidly completing the correct-by-construction layout of a staggered-pad, I/O-bound ASIC.<>
{"title":"An automated, structured layout methodology for staggered pad, I/O-bound ASIC design","authors":"L.Y. Lu, M. D. Alston","doi":"10.1109/ASIC.1990.186167","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186167","url":null,"abstract":"A design methodology developed and implemented for high-pin-count cell-based BiCMOS ASIC designs is discussed. Described is the orchestration of different vendors' CAD tools via tool-specific shell scripts, macros, file reformatting/conversion software and application software to methodically place and route I/O pad cells, I/O circuit cells, and core logic megacells, rapidly completing the correct-by-construction layout of a staggered-pad, I/O-bound ASIC.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129450942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186153
T.W. Moxon
The design tradeoffs encountered when implementing a ASIC design that incorporates boundary scan logic are discussed. Boundary scan logic can improve both the device- and system-level testability. The designer, however, must weigh the impact on silicon area, performance, routability, and implementation time to achieve the optimum design solution.<>
{"title":"Design trade-offs when implementing boundary scan in an application specific integrated circuit","authors":"T.W. Moxon","doi":"10.1109/ASIC.1990.186153","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186153","url":null,"abstract":"The design tradeoffs encountered when implementing a ASIC design that incorporates boundary scan logic are discussed. Boundary scan logic can improve both the device- and system-level testability. The designer, however, must weigh the impact on silicon area, performance, routability, and implementation time to achieve the optimum design solution.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127885450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186093
N. Zafar
ASIC design validation, confirming that the chips work in the system, has been the major source of risk in any ASIC development cycle. The risk is that of missing the market window. The cause is the lack of technologies to assure, before fabrication, that ASIC designs will operate properly in the target system. Innovations in the area of field programmable gate arrays have enabled an ASIC system design tool technology called reprogrammable hardware emulation. The management of risk and the economic advantage of using this technology in the ASIC design cycle is studied.<>
{"title":"Managing risk in ASIC design cycle","authors":"N. Zafar","doi":"10.1109/ASIC.1990.186093","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186093","url":null,"abstract":"ASIC design validation, confirming that the chips work in the system, has been the major source of risk in any ASIC development cycle. The risk is that of missing the market window. The cause is the lack of technologies to assure, before fabrication, that ASIC designs will operate properly in the target system. Innovations in the area of field programmable gate arrays have enabled an ASIC system design tool technology called reprogrammable hardware emulation. The management of risk and the economic advantage of using this technology in the ASIC design cycle is studied.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121039829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：