Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186197
R. B. Ravel
A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed. The architecture allows complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices.<>
{"title":"Third-generation architecture boosts speed and density of field-programmable gate arrays","authors":"R. B. Ravel","doi":"10.1109/ASIC.1990.186197","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186197","url":null,"abstract":"A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed. The architecture allows complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123830817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186144
U. Ko, S. Schenck, B. Van Eerden, W. Locke, M. Rumsey, J. Sackett
Problems in designing mixed-signal ASICs come from different simulation accuracy requirements and, as a result, different modeling approaches for analog and digital circuits. The conventional design styles for mixed-signal ASICs use two separate simulators, such as a SPICE-like simulator for analog circuits and a logic simulation for digital circuits. This approach is engineering-intensive, time-consuming, and error-prone. To solve these problems, the analog modeling package (AMP) has been developed. The authors describe how the AMP presents a systematic solution to mixed-signal simulation on a pure digital-logic simulator. In the AMP, analog behavioral models are created by connecting parameterized building blocks in a schematic capture tool with SPICE-characterized data. Then a chip-level mixed-signal design verification is implemented on one simulator to eliminate errors. An analog-signal trace file is also created for automatic test program generation. This solution significantly enhances the competitiveness of mixed-signal design and development in cost, cycle-time, and first-pass success.<>
{"title":"Mixed-signal ASIC simulation via an analog modeling package","authors":"U. Ko, S. Schenck, B. Van Eerden, W. Locke, M. Rumsey, J. Sackett","doi":"10.1109/ASIC.1990.186144","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186144","url":null,"abstract":"Problems in designing mixed-signal ASICs come from different simulation accuracy requirements and, as a result, different modeling approaches for analog and digital circuits. The conventional design styles for mixed-signal ASICs use two separate simulators, such as a SPICE-like simulator for analog circuits and a logic simulation for digital circuits. This approach is engineering-intensive, time-consuming, and error-prone. To solve these problems, the analog modeling package (AMP) has been developed. The authors describe how the AMP presents a systematic solution to mixed-signal simulation on a pure digital-logic simulator. In the AMP, analog behavioral models are created by connecting parameterized building blocks in a schematic capture tool with SPICE-characterized data. Then a chip-level mixed-signal design verification is implemented on one simulator to eliminate errors. An analog-signal trace file is also created for automatic test program generation. This solution significantly enhances the competitiveness of mixed-signal design and development in cost, cycle-time, and first-pass success.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117195532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186087
R.B. Nguyen
The elements of a successful ASIC (application-specific integrated circuit) project, from the front-end development point of view, are discussed. Personnel requirements and training, vendor and tool selection, project specification, and scheduling and budgeting are considered in detail. A successful project requires detailed planning and must be executed with strict management discipline.<>
{"title":"Managing ASIC projects","authors":"R.B. Nguyen","doi":"10.1109/ASIC.1990.186087","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186087","url":null,"abstract":"The elements of a successful ASIC (application-specific integrated circuit) project, from the front-end development point of view, are discussed. Personnel requirements and training, vendor and tool selection, project specification, and scheduling and budgeting are considered in detail. A successful project requires detailed planning and must be executed with strict management discipline.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130649414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186202
R. Puri, M. Hasan
A state machine synthesis system, named PLASMA, which can be used for the implementation of finite-state machines (FSMs) in programmable logic arrays (PLAs) is discussed. The minimization algorithm effectively prunes the tree structure of compatibles list to find the minimum form of a minimized single output change (SOC) machine. State assignment, i.e. the process of binary encoding of internal states of the FSM, has been efficiently utilized to save the silicon area occupied by PLA. The system is complete and works efficiently for incompletely specified sequential machines (ISSMs) to achieve area optimization in the PLA structure.<>
{"title":"PLASMA: a FSM design kernel","authors":"R. Puri, M. Hasan","doi":"10.1109/ASIC.1990.186202","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186202","url":null,"abstract":"A state machine synthesis system, named PLASMA, which can be used for the implementation of finite-state machines (FSMs) in programmable logic arrays (PLAs) is discussed. The minimization algorithm effectively prunes the tree structure of compatibles list to find the minimum form of a minimized single output change (SOC) machine. State assignment, i.e. the process of binary encoding of internal states of the FSM, has been efficiently utilized to save the silicon area occupied by PLA. The system is complete and works efficiently for incompletely specified sequential machines (ISSMs) to achieve area optimization in the PLA structure.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121631485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186149
T. Ritoniemi, V. Eerola, T. Karema, H. Tenhunen
The basic principles of oversampled noise-shaping analog-digital (A/D) and digital-analog (D/A) converters are presented. Basic operation and theory behind sigma-delta modulation are reviewed. The different structures of the sigma-delta converters are described, and the concepts of designing modulators and digital filters are discussed. The latest designs are reviewed.<>
{"title":"Oversampled A/D and D/A converters for VLSI system integration","authors":"T. Ritoniemi, V. Eerola, T. Karema, H. Tenhunen","doi":"10.1109/ASIC.1990.186149","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186149","url":null,"abstract":"The basic principles of oversampled noise-shaping analog-digital (A/D) and digital-analog (D/A) converters are presented. Basic operation and theory behind sigma-delta modulation are reviewed. The different structures of the sigma-delta converters are described, and the concepts of designing modulators and digital filters are discussed. The latest designs are reviewed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186137
P. Mukherjee
An efficient two-dimensional pipelined systolic architecture which can perform convolution operations in 2n+b/2 time units as opposed to O(bn) time needed for the sequential algorithm on a single processor is discussed. A very efficient pipelined multiplier, which enjoys all the merits of a systolic scheme and can be made a part of an ASIC library of medium-scale integration (MSI) cells, is also briefly discussed.<>
{"title":"An efficient two-dimensional pipeline architecture for digital signal processing operation","authors":"P. Mukherjee","doi":"10.1109/ASIC.1990.186137","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186137","url":null,"abstract":"An efficient two-dimensional pipelined systolic architecture which can perform convolution operations in 2n+b/2 time units as opposed to O(bn) time needed for the sequential algorithm on a single processor is discussed. A very efficient pipelined multiplier, which enjoys all the merits of a systolic scheme and can be made a part of an ASIC library of medium-scale integration (MSI) cells, is also briefly discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122153613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186122
S. Chung, Jam-Wem Lee, Y. Chen, Po-Chin Hsu
A lightly doped drain (LDD) MOS device model for circuit simulation in SPICE is described. UNI-MOS includes a consistent set of DC (I-V), AC (C-V), and hot electron degradation effect models. For the I-V and C-V models, results for achieving accurate and computationally efficient models of both conventional and LDD MOSFETs with submicron channel length are described. Strategies for implementing the hot electron effect in the circuit simulator for predicting the lifetime of a device or circuit in a VLSI environment are demonstrated.<>
{"title":"UNI-MOS: a unified SPICE built-in MOSFET model for circuit simulation and lifetime evaluation","authors":"S. Chung, Jam-Wem Lee, Y. Chen, Po-Chin Hsu","doi":"10.1109/ASIC.1990.186122","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186122","url":null,"abstract":"A lightly doped drain (LDD) MOS device model for circuit simulation in SPICE is described. UNI-MOS includes a consistent set of DC (I-V), AC (C-V), and hot electron degradation effect models. For the I-V and C-V models, results for achieving accurate and computationally efficient models of both conventional and LDD MOSFETs with submicron channel length are described. Strategies for implementing the hot electron effect in the circuit simulator for predicting the lifetime of a device or circuit in a VLSI environment are demonstrated.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122264632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186117
A.T. Eiriksson
A mixed behavioral- and gate-level simulator is described. The unique feature is that the gate-level modules of a design are simulated using a simulation engine, while a host computer simulates the behavioral-level modules and enforces the synchronization between the host computer and engine. The behavioral models are described using a high-level process-oriented behavioral specification language BSL. Runtime experiments show that the simulator speeds-up the simulation of systems of size ( Hash gates, Hash lines BSL) in ((25 K, 2 K), (50 K, 10 K)) by a factor of 5-7 times, compared to the compatible software simulator.<>
{"title":"Mixed-level simulation with a Zycad simulation engine","authors":"A.T. Eiriksson","doi":"10.1109/ASIC.1990.186117","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186117","url":null,"abstract":"A mixed behavioral- and gate-level simulator is described. The unique feature is that the gate-level modules of a design are simulated using a simulation engine, while a host computer simulates the behavioral-level modules and enforces the synchronization between the host computer and engine. The behavioral models are described using a high-level process-oriented behavioral specification language BSL. Runtime experiments show that the simulator speeds-up the simulation of systems of size ( Hash gates, Hash lines BSL) in ((25 K, 2 K), (50 K, 10 K)) by a factor of 5-7 times, compared to the compatible software simulator.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121033920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186077
S.S. Chung
The current status of existing simulators and their implementation techniques for VLSI circuits are reviewed. The basic algorithms upon which simulators are built are reviewed and practical implementation adopting the existing simulation program are described. Particular emphasis is placed on introducing the basics of computational techniques required for implementing DC, AC, and transient analysis as well as novel techniques for improving simulation accuracy or speed-up techniques. One specific feature is the demonstration of several experimental simulators. Some important areas for future research are also identified.<>
{"title":"Simulation techniques for VLSI circuits","authors":"S.S. Chung","doi":"10.1109/ASIC.1990.186077","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186077","url":null,"abstract":"The current status of existing simulators and their implementation techniques for VLSI circuits are reviewed. The basic algorithms upon which simulators are built are reviewed and practical implementation adopting the existing simulation program are described. Particular emphasis is placed on introducing the basics of computational techniques required for implementing DC, AC, and transient analysis as well as novel techniques for improving simulation accuracy or speed-up techniques. One specific feature is the demonstration of several experimental simulators. Some important areas for future research are also identified.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123985905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186178
R. Nelson, B. Williams, G. Westbrook
Test hardware interface requirements for testing high-pin-count ASIC TAB (tape automated bonding) products are discussed. Test solutions which have been proven in a production environment are described. Test-on-tape using the techniques illustrated has proven viable for high-speed bipolar gate arrays having 360 leads with 0.004 in lead width and 0.008 in lead pitch in the (outer lead bond) and test area. Successfully testing small pitch outer leads of TAB products requires the combination of electrical, mechanical, and thermal designs to be controlled within specific tolerances. The final testing of TAB ASICs is performed after all other value added processes have been completed. Therefore, an understanding of the factors which impact final test yield is essential.<>
{"title":"Interfacing test equipment to high density chip-on-tape","authors":"R. Nelson, B. Williams, G. Westbrook","doi":"10.1109/ASIC.1990.186178","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186178","url":null,"abstract":"Test hardware interface requirements for testing high-pin-count ASIC TAB (tape automated bonding) products are discussed. Test solutions which have been proven in a production environment are described. Test-on-tape using the techniques illustrated has proven viable for high-speed bipolar gate arrays having 360 leads with 0.004 in lead width and 0.008 in lead pitch in the (outer lead bond) and test area. Successfully testing small pitch outer leads of TAB products requires the combination of electrical, mechanical, and thermal designs to be controlled within specific tolerances. The final testing of TAB ASICs is performed after all other value added processes have been completed. Therefore, an understanding of the factors which impact final test yield is essential.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"950 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126997328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：