Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186139
L. D'Luna, W.A. Cook, R. Guidash, G.W. Brown, T. Tredwell, J. Fischer, T. Tarn
Image compression is an established means of meeting storage and transmission requirements for image data. One method is transform domain compression using the two-dimensional discrete cosine transform (DCT) on 8*8 image blocks. A 2- mu m CMOS chip that computes this transform in real-time using clocks that are no faster than the pixel rate is described. The architecture uses a distributed arithmetic processing scheme to compute two one-dimensional transforms interposed with an unconventional matrix transpose RAM. The design methodology that includes layout, simulation, verification and test, using a silicon compiler tool-set, is described.<>
图像压缩是满足图像数据存储和传输要求的常用手段。一种方法是在8*8图像块上使用二维离散余弦变换(DCT)进行变换域压缩。描述了一种2 μ m CMOS芯片，该芯片使用不超过像素率的时钟实时计算这种转换。该体系结构使用分布式算法处理方案来计算两个一维变换，并插入一个非常规矩阵转置RAM。描述了设计方法，包括布局，仿真，验证和测试，使用硅编译器工具集。
{"title":"An 8*8 discrete cosine transform chip with pixel rate clocks","authors":"L. D'Luna, W.A. Cook, R. Guidash, G.W. Brown, T. Tredwell, J. Fischer, T. Tarn","doi":"10.1109/ASIC.1990.186139","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186139","url":null,"abstract":"Image compression is an established means of meeting storage and transmission requirements for image data. One method is transform domain compression using the two-dimensional discrete cosine transform (DCT) on 8*8 image blocks. A 2- mu m CMOS chip that computes this transform in real-time using clocks that are no faster than the pixel rate is described. The architecture uses a distributed arithmetic processing scheme to compute two one-dimensional transforms interposed with an unconventional matrix transpose RAM. The design methodology that includes layout, simulation, verification and test, using a silicon compiler tool-set, is described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186135
K. Shirai, T. Ikenaga, H. Kitabatake
In order to satisfy the user's requirements which are described by a high level language, a large number of possibilities must be examined to find a good design. The case in which the architecture is restricted to that having a usual instruction set is considered. The main objective of the system is to generate a minimal set of hardware which can execute the given algorithms and also satisfy other requirements such as speed, hardware cost, and I/O condition. It realizes an integrated system which provides not only a hardware design environment but also a software one by generating automatically a higher-level language compiler which has optimization capability for the processor at the same time. As a practical example, the design of a special-purpose processor which can execute thirteen typical digital signal processing algorithms is demonstrated. It is shown that the design system can provide ASIC users a total environment to design and use special-purpose processors. The software development tools are superior to those usable for general-purpose DSPs.<>
{"title":"Design system for special purpose processor executing algorithms described by higher level language","authors":"K. Shirai, T. Ikenaga, H. Kitabatake","doi":"10.1109/ASIC.1990.186135","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186135","url":null,"abstract":"In order to satisfy the user's requirements which are described by a high level language, a large number of possibilities must be examined to find a good design. The case in which the architecture is restricted to that having a usual instruction set is considered. The main objective of the system is to generate a minimal set of hardware which can execute the given algorithms and also satisfy other requirements such as speed, hardware cost, and I/O condition. It realizes an integrated system which provides not only a hardware design environment but also a software one by generating automatically a higher-level language compiler which has optimization capability for the processor at the same time. As a practical example, the design of a special-purpose processor which can execute thirteen typical digital signal processing algorithms is demonstrated. It is shown that the design system can provide ASIC users a total environment to design and use special-purpose processors. The software development tools are superior to those usable for general-purpose DSPs.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128474283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186124
R. Rivin, J. Potts
The performance of high-speed digital signal processors (DSPs) poses a challenge to real-time in-circuit emulation. Because DSPs are optimized to perform arithmetic calculations in less than 50 ns, internal and external data buses can change at rates in excess of 20 million times per second. The capture and tracking of these signals and the control of the processor is the essence of real-time in-circuit emulation. In order to support high-performance emulation, these issues were emphasized during the specification and design of a DSP. The system-level requirements that drive design considerations to allow emulation of this VLSI circuit are discussed.<>
{"title":"Designing a VLSI microprocessor for emulation","authors":"R. Rivin, J. Potts","doi":"10.1109/ASIC.1990.186124","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186124","url":null,"abstract":"The performance of high-speed digital signal processors (DSPs) poses a challenge to real-time in-circuit emulation. Because DSPs are optimized to perform arithmetic calculations in less than 50 ns, internal and external data buses can change at rates in excess of 20 million times per second. The capture and tracking of these signals and the control of the processor is the essence of real-time in-circuit emulation. In order to support high-performance emulation, these issues were emphasized during the specification and design of a DSP. The system-level requirements that drive design considerations to allow emulation of this VLSI circuit are discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"695 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122981273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186147
T. Gabara, D. Thompson
The operation and design of 200-MHz 100 K ECL output buffers for CMOS ASICs are described. It is shown how the components of the buffer output driver transistor, gate voltage generator, and low skew input drivers are combined into unique clock and data output buffers. A section on unity gain op-amp design describes how a number of these buffers are used on an ASIC. Application guidelines (curves) to illustrate the tradeoff between the buffer frequency and the number of buffers on an ASIC application are presented. The advantages that this input buffer provides in the area of low ground bounce generation is presented. Waveforms from an ASIC with 24 balanced and 16 single ended ECL output buffers are presented.<>
{"title":"A 200 MHz 100 K ECL output buffer for CMOS ASICs","authors":"T. Gabara, D. Thompson","doi":"10.1109/ASIC.1990.186147","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186147","url":null,"abstract":"The operation and design of 200-MHz 100 K ECL output buffers for CMOS ASICs are described. It is shown how the components of the buffer output driver transistor, gate voltage generator, and low skew input drivers are combined into unique clock and data output buffers. A section on unity gain op-amp design describes how a number of these buffers are used on an ASIC. Application guidelines (curves) to illustrate the tradeoff between the buffer frequency and the number of buffers on an ASIC application are presented. The advantages that this input buffer provides in the area of low ground bounce generation is presented. Waveforms from an ASIC with 24 balanced and 16 single ended ECL output buffers are presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114628360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186130
R. Munoz
An artificial-intelligence (AI)-based timing analysis and standard cell optimization CAD tool, TASCO, for standard cell-based circuits is described. TASCO executes a circuit timing analysis, finds the critical paths, the critical gates responsible, and optimizes the critical gates. It has done this in less than 60 minutes for most circuits, depending on the complexity of the circuit and how far the original circuit was from meeting the timing requirement. The only limitation encountered with the tool is a circuit complexity constraint in C-Prolog. Regardless, TASCO should prove to be a significant boost toward the goal of automating the timing verification phase of a standard cell-based design. This approach shortens the design interval and relieves the designer from a tedious and repetitive analysis.<>
{"title":"An AI approach to timing analysis and optimization for standard cell based ASICs","authors":"R. Munoz","doi":"10.1109/ASIC.1990.186130","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186130","url":null,"abstract":"An artificial-intelligence (AI)-based timing analysis and standard cell optimization CAD tool, TASCO, for standard cell-based circuits is described. TASCO executes a circuit timing analysis, finds the critical paths, the critical gates responsible, and optimizes the critical gates. It has done this in less than 60 minutes for most circuits, depending on the complexity of the circuit and how far the original circuit was from meeting the timing requirement. The only limitation encountered with the tool is a circuit complexity constraint in C-Prolog. Regardless, TASCO should prove to be a significant boost toward the goal of automating the timing verification phase of a standard cell-based design. This approach shortens the design interval and relieves the designer from a tedious and repetitive analysis.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122617956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186186
S. Roy, H. Nagle, M.G. McNamer, W. Krakow
The design of a real-time heart rate monitor implemented as a single application-specific integrated circuit (ASIC) is presented. The goal of the project was to implement a QRS detection algorithm into a single-chip environment. The testability strategies used to increase device reliability, including the implementation of built-in-self test (BIST) features, are described.<>
{"title":"QRS/BIST: a reliable heart rate monitor ASIC","authors":"S. Roy, H. Nagle, M.G. McNamer, W. Krakow","doi":"10.1109/ASIC.1990.186186","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186186","url":null,"abstract":"The design of a real-time heart rate monitor implemented as a single application-specific integrated circuit (ASIC) is presented. The goal of the project was to implement a QRS detection algorithm into a single-chip environment. The testability strategies used to increase device reliability, including the implementation of built-in-self test (BIST) features, are described.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122839698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186168
J. Ellis, M. McManus, R. Weir
How parameterization impacts the design of module generators from initial parameter selection and architectural definition, to circuit-level design, characterization, and verification is discussed. In the design process it is desired to maximize the design space of the module to allow for the broadest possible range of applications but within certain constraints. The selection of parameters and their ranges can be crucial in achieving a large design space without major sacrifices to design goals. These parameters define the design space, and have three important aspects: granularity is the increment with which a parameter may change; continuity is a measure of the consistency of the parameterization effort through the entire scope of the parameter; and coupling indicates how a parameter's effort is impacted by changes in other parameters. Speed, power, and area are too tightly coupled to be considered for parameterization. Selection of other parameters should be made based on the impact that they have on the effort required for procedural-level coding, verification, characterization, and maintenance.<>
{"title":"Impact of parameterization on the design of module generators","authors":"J. Ellis, M. McManus, R. Weir","doi":"10.1109/ASIC.1990.186168","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186168","url":null,"abstract":"How parameterization impacts the design of module generators from initial parameter selection and architectural definition, to circuit-level design, characterization, and verification is discussed. In the design process it is desired to maximize the design space of the module to allow for the broadest possible range of applications but within certain constraints. The selection of parameters and their ranges can be crucial in achieving a large design space without major sacrifices to design goals. These parameters define the design space, and have three important aspects: granularity is the increment with which a parameter may change; continuity is a measure of the consistency of the parameterization effort through the entire scope of the parameter; and coupling indicates how a parameter's effort is impacted by changes in other parameters. Speed, power, and area are too tightly coupled to be considered for parameterization. Selection of other parameters should be made based on the impact that they have on the effort required for procedural-level coding, verification, characterization, and maintenance.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124831354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186189
Y.-I. Hsieh
The establishment of the engineering rules to create the executable and synthesizable (and/or testable) specification for an ASIC design in an ASIC CAD environment is discussed. The Intel 8253 programmable timer/counter was selected as a test example to illustrate the strengths and weaknesses of this CAD technology. The need for a high-performance cell-based ASIC/IC CAD system is critical for this application.<>
{"title":"An Intel 18253 ASIC chip design","authors":"Y.-I. Hsieh","doi":"10.1109/ASIC.1990.186189","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186189","url":null,"abstract":"The establishment of the engineering rules to create the executable and synthesizable (and/or testable) specification for an ASIC design in an ASIC CAD environment is discussed. The Intel 8253 programmable timer/counter was selected as a test example to illustrate the strengths and weaknesses of this CAD technology. The need for a high-performance cell-based ASIC/IC CAD system is critical for this application.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130218026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186187
A. Grasso
The specification, design, and development of an electronic identification system are discussed. The system has the advantages of long-read-range, orientation-independent, low-cost, passive tags, which are easy to manufacture, require simple installation procedures, and are suitable for use in many countries, over a wide and diverse set of application areas.<>
{"title":"Electronic remote identification-a case study","authors":"A. Grasso","doi":"10.1109/ASIC.1990.186187","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186187","url":null,"abstract":"The specification, design, and development of an electronic identification system are discussed. The system has the advantages of long-read-range, orientation-independent, low-cost, passive tags, which are easy to manufacture, require simple installation procedures, and are suitable for use in many countries, over a wide and diverse set of application areas.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125288015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186180
K. Perrey, M. Manley
Two schemes for testing user logic in a microcontroller-based ASIC are described. The direct access method consists of multiplexing primary signals with the microcontroller's signals at the interface with user logic. Multiplexing allows the designer to mimic the microcontroller core's application of stimuli to user logic using a predefined test mode. During test mode, the designer has both the controllability and the observability to directly test the user logic. This method bypasses whatever method is used for testing the microcontroller core and peripherals. Alternatively, the core access method utilizes the microcontroller core to test user logic. To reduce the customer's burden, the standard microcontroller assembler has been enhanced to aid in test vector generation. The extended assembler allows customers to generate stimuli and monitor responses which are synchronized with the bus cycles of the microcontroller core. This method of testing user logic is complementary to and dependent on the method of testing the microcontroller core and peripherals. Advantages and disadvantages of each approach are described. Three examples are explored to compare and contrast these two testing methods.<>
{"title":"An assembler approach to the automation of test vector generation","authors":"K. Perrey, M. Manley","doi":"10.1109/ASIC.1990.186180","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186180","url":null,"abstract":"Two schemes for testing user logic in a microcontroller-based ASIC are described. The direct access method consists of multiplexing primary signals with the microcontroller's signals at the interface with user logic. Multiplexing allows the designer to mimic the microcontroller core's application of stimuli to user logic using a predefined test mode. During test mode, the designer has both the controllability and the observability to directly test the user logic. This method bypasses whatever method is used for testing the microcontroller core and peripherals. Alternatively, the core access method utilizes the microcontroller core to test user logic. To reduce the customer's burden, the standard microcontroller assembler has been enhanced to aid in test vector generation. The extended assembler allows customers to generate stimuli and monitor responses which are synchronized with the bus cycles of the microcontroller core. This method of testing user logic is complementary to and dependent on the method of testing the microcontroller core and peripherals. Advantages and disadvantages of each approach are described. Three examples are explored to compare and contrast these two testing methods.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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