Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186140
K. Hsu, L. D'Luna, H. Yeh, W.A. Cook, G.W. Brown
A VLSI chip that can perform either 3*3 matrix multiplication or 3*3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2- mu m CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time video and image processing applications.<>
讨论了一种可以进行3*3矩阵乘法和3*3数字卷积的VLSI芯片。内置自检(BIST)技术已纳入芯片，以确保高故障覆盖率。该芯片采用2 μ m CMOS技术，采用硅编译器进行物理布局。该设备的设计工作频率为14.3 MHz，适用于实时视频和图像处理应用。
{"title":"A pipelined ASIC for color matrixing and convolution","authors":"K. Hsu, L. D'Luna, H. Yeh, W.A. Cook, G.W. Brown","doi":"10.1109/ASIC.1990.186140","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186140","url":null,"abstract":"A VLSI chip that can perform either 3*3 matrix multiplication or 3*3 digital convolution is discussed. Built-in self-test (BIST) techniques have been incorporated into the chip to ensure high fault coverage. The chip is designed in a 2- mu m CMOS technology using a silicon compiler for physical layout. The device is designed to operate at 14.3 MHz, making it suitable for real-time video and image processing applications.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186181
A. Criado
The MOSart comprehensive CAD/CAE system for the design and development of cell-based ASICs and full custom VLSI circuits. The MOSart design environment encompasses a wide variety of applications, i.e. design tools with which a design team can implement an ASIC. The computer-aided-engineering capabilities of MOSart through which the analysis of simulation results, along with the automated generation of ATE-compatible test vector patterns, are obtained. Three of MOSart's application tools, namely, VECTORGEN, SIMGEN and LAS, are considered. VECTORGEN and SIMGEN are application tools developed specifically to assist with the task of verifying a given ASIC design. With the aid of VECTORGEN and SIMGEN, simulator stimuli and the creation of ATE-compatible test vector patterns are accomplished. LAS (logic analysis system) provides systematic and automated procedures that facilitate the analysis of the behavior of a given logic block including the top level block of a completed design.<>
{"title":"ASIC VLSI design and development in MOSart-a focus on logic analysis and automated test vector generation","authors":"A. Criado","doi":"10.1109/ASIC.1990.186181","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186181","url":null,"abstract":"The MOSart comprehensive CAD/CAE system for the design and development of cell-based ASICs and full custom VLSI circuits. The MOSart design environment encompasses a wide variety of applications, i.e. design tools with which a design team can implement an ASIC. The computer-aided-engineering capabilities of MOSart through which the analysis of simulation results, along with the automated generation of ATE-compatible test vector patterns, are obtained. Three of MOSart's application tools, namely, VECTORGEN, SIMGEN and LAS, are considered. VECTORGEN and SIMGEN are application tools developed specifically to assist with the task of verifying a given ASIC design. With the aid of VECTORGEN and SIMGEN, simulator stimuli and the creation of ATE-compatible test vector patterns are accomplished. LAS (logic analysis system) provides systematic and automated procedures that facilitate the analysis of the behavior of a given logic block including the top level block of a completed design.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128769351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186182
T.A. Horvath, N. H. Kreitzer
A commercially available hardware emulation system and its expected capabilities are described, and results of an evaluation using an existing VLSI chip are reviewed. Based on this experience, the potential of the emulation system in ASIC design is assessed and areas of improvement are suggested. A forecast is also given of possible evolution of hardware emulation.<>
{"title":"Hardware emulation of VLSI designs","authors":"T.A. Horvath, N. H. Kreitzer","doi":"10.1109/ASIC.1990.186182","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186182","url":null,"abstract":"A commercially available hardware emulation system and its expected capabilities are described, and results of an evaluation using an existing VLSI chip are reviewed. Based on this experience, the potential of the emulation system in ASIC design is assessed and areas of improvement are suggested. A forecast is also given of possible evolution of hardware emulation.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125950989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186152
D. D'souza
The autodiagnosis technique that uses scan design is described and its relation to the IEEE Joint Test Action Group (JTAG) boundary scan is pointed out. The similarities between autodiagnosis and the JTAG boundary scan are emphasized. JTAG and the tradeoffs in such a conversion are discussed.<>
{"title":"JTAG and Hitachi's autodiagnosis","authors":"D. D'souza","doi":"10.1109/ASIC.1990.186152","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186152","url":null,"abstract":"The autodiagnosis technique that uses scan design is described and its relation to the IEEE Joint Test Action Group (JTAG) boundary scan is pointed out. The similarities between autodiagnosis and the JTAG boundary scan are emphasized. JTAG and the tradeoffs in such a conversion are discussed.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121494850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186204
M.V. Bapst
The ideal multiplier compiler is defined as one which produces a product that achieves high performance and high density and is also portable to different technologies. In addition, such a compiler should support multiple data formats and extend to any data size. It should be reconfigurable and evolvable, and it should incorporate automatic test vector generation (ATVG). The multiplier presented meets all of these requirements.<>
{"title":"The ideal multiplier compiler","authors":"M.V. Bapst","doi":"10.1109/ASIC.1990.186204","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186204","url":null,"abstract":"The ideal multiplier compiler is defined as one which produces a product that achieves high performance and high density and is also portable to different technologies. In addition, such a compiler should support multiple data formats and extend to any data size. It should be reconfigurable and evolvable, and it should incorporate automatic test vector generation (ATVG). The multiplier presented meets all of these requirements.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123206484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186111
F. Blitzer, J. Samson
A methodology which has yielded excellent results in identifying critical device needs for complex military systems is described. This methodology is illustrated using examples derived from advanced satellite and other processing system studies. The microelectronic device selection process begins with the identification of mission requirements. The system designer then identifies the system functions necessary to perform the mission and allocates these functions to architectural elements within the system. At some level in this allocation is the processing system (hardware and software). From this point, the synthesis of possible processing concepts and configurations is initiated. This iterative process includes functional, technology, and packaging trade studies which establish the parameters of the trade space(s) involved and identify design sensitivities. From these analyses, the designer and his customer identify tradeoff criteria so that the lower level trades can be made to isolate technology needs. These needs may be satisfied with mature technology or, if schedule permits, the development of new or maturing technology. The key elements of this selection process are technology and risk assessment. Particular emphasis is placed on these two aspects of the process.<>
{"title":"The microelectronic device selection process","authors":"F. Blitzer, J. Samson","doi":"10.1109/ASIC.1990.186111","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186111","url":null,"abstract":"A methodology which has yielded excellent results in identifying critical device needs for complex military systems is described. This methodology is illustrated using examples derived from advanced satellite and other processing system studies. The microelectronic device selection process begins with the identification of mission requirements. The system designer then identifies the system functions necessary to perform the mission and allocates these functions to architectural elements within the system. At some level in this allocation is the processing system (hardware and software). From this point, the synthesis of possible processing concepts and configurations is initiated. This iterative process includes functional, technology, and packaging trade studies which establish the parameters of the trade space(s) involved and identify design sensitivities. From these analyses, the designer and his customer identify tradeoff criteria so that the lower level trades can be made to isolate technology needs. These needs may be satisfied with mature technology or, if schedule permits, the development of new or maturing technology. The key elements of this selection process are technology and risk assessment. Particular emphasis is placed on these two aspects of the process.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131816872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186092
E. Vopni
An approach to managing the complexities of ASIC design within a telecommunications design and manufacturing company is described. The approach is based on the use of a limited number of approved ASIC vendors, a unified multiple vendor/technology design system, centralized application support, and a central forum for information exchange. The Logic Array Design System (LADS) was developed to provide a consistent design and test methodology across multiple ASIC vendors and technologies.<>
{"title":"A common design and test strategy for merchant ASICs","authors":"E. Vopni","doi":"10.1109/ASIC.1990.186092","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186092","url":null,"abstract":"An approach to managing the complexities of ASIC design within a telecommunications design and manufacturing company is described. The approach is based on the use of a limited number of approved ASIC vendors, a unified multiple vendor/technology design system, centralized application support, and a central forum for information exchange. The Logic Array Design System (LADS) was developed to provide a consistent design and test methodology across multiple ASIC vendors and technologies.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131665414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186075
P.V.C.V. Reddy
The ever-increasing complexity of very large scale integration (VLSI) has a considerable impact on the design and implementation of fault-tolerant circuits and systems. The techniques of fault-tolerance are well established. VLSI, however, introduces problems in fault-tolerant design. An overview of the design and implementation of fault-tolerant systems in a VLSI environment is presented.<>
{"title":"Fault-tolerant design of VLSI circuits and systems","authors":"P.V.C.V. Reddy","doi":"10.1109/ASIC.1990.186075","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186075","url":null,"abstract":"The ever-increasing complexity of very large scale integration (VLSI) has a considerable impact on the design and implementation of fault-tolerant circuits and systems. The techniques of fault-tolerance are well established. VLSI, however, introduces problems in fault-tolerant design. An overview of the design and implementation of fault-tolerant systems in a VLSI environment is presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186082
T. Wong
Summary form only given, as follows. ASIC is the technology driver for advanced packaging. This includes high-pin-count surface mount devices, high-performance ceramic packages, tape automated bonding (TAB) packages, and multichip modules (MCM). Emphasis is placed on fine-pitch technology (FPT) and the advantages and limitations of quad flat packs (QFP). Limitations due to power dissipation, ability to handle large die sizes, pin pitch below 0.4 mm, and coplanarity issues are addressed. Future trends in ASIC packaging are covered. A short introduction to multichip modules is also presented.<>
{"title":"The realities of ASIC packaging","authors":"T. Wong","doi":"10.1109/ASIC.1990.186082","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186082","url":null,"abstract":"Summary form only given, as follows. ASIC is the technology driver for advanced packaging. This includes high-pin-count surface mount devices, high-performance ceramic packages, tape automated bonding (TAB) packages, and multichip modules (MCM). Emphasis is placed on fine-pitch technology (FPT) and the advantages and limitations of quad flat packs (QFP). Limitations due to power dissipation, ability to handle large die sizes, pin pitch below 0.4 mm, and coplanarity issues are addressed. Future trends in ASIC packaging are covered. A short introduction to multichip modules is also presented.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133082204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186129
W. McKinley, M. Scaggs
A creative method for integration of complex cell functions is developed and implemented for several different circuit implementations. Although this method does not solve all integration problems, it is ideal in some applications. The risks of such a method are presented, along with support tool methods of verification. It allows for greater flexibility in designing a complex cell function into an ASIC. In addition, this value-added, customer-owned tooling (COT) manufacturing methodology can potentially reduce time-to-market.<>
{"title":"Matching ASIC design methodologies to the manufacturing environment","authors":"W. McKinley, M. Scaggs","doi":"10.1109/ASIC.1990.186129","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186129","url":null,"abstract":"A creative method for integration of complex cell functions is developed and implemented for several different circuit implementations. Although this method does not solve all integration problems, it is ideal in some applications. The risks of such a method are presented, along with support tool methods of verification. It allows for greater flexibility in designing a complex cell function into an ASIC. In addition, this value-added, customer-owned tooling (COT) manufacturing methodology can potentially reduce time-to-market.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133363085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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