Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186205
A. Herrigel
A global-routing-driven floorplanning technique that is based on a top-down approach is presented. Rectangular cells such as in macrocell design are considered. The topics discussed include: (1) a model for the prediction of shape functions which enables consideration of a more general class of floorplan representations, (2) an improved two-dimensional partitioning procedure, and (3) a dynamic updating scheme that considers interconnect area around each cell during the floorplan assembly.<>
{"title":"GRCA: a global approach for floorplanning synthesis","authors":"A. Herrigel","doi":"10.1109/ASIC.1990.186205","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186205","url":null,"abstract":"A global-routing-driven floorplanning technique that is based on a top-down approach is presented. Rectangular cells such as in macrocell design are considered. The topics discussed include: (1) a model for the prediction of shape functions which enables consideration of a more general class of floorplan representations, (2) an improved two-dimensional partitioning procedure, and (3) a dynamic updating scheme that considers interconnect area around each cell during the floorplan assembly.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133058694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186095
M. Thompson, J. Luecke
A configurable, high-speed application-specific integrated circuit (ASIC) which is the key demodulation element in NASA's newest generation of tracking and data relay satellite system (TDRSS) ground communication equipment is discussed. The technical details of the system application and implementation of this CMOS device are included. Driven by operating speed requirements, emphasis is placed on the tradeoffs which lead to the final high-speed design.<>
{"title":"Configurable demodulator ASIC for the TDRSS communication system","authors":"M. Thompson, J. Luecke","doi":"10.1109/ASIC.1990.186095","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186095","url":null,"abstract":"A configurable, high-speed application-specific integrated circuit (ASIC) which is the key demodulation element in NASA's newest generation of tracking and data relay satellite system (TDRSS) ground communication equipment is discussed. The technical details of the system application and implementation of this CMOS device are included. Driven by operating speed requirements, emphasis is placed on the tradeoffs which lead to the final high-speed design.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115576104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186112
S. A. Coogan
The different microelectronics packaging approaches currently available and in development are summarized for system engineers. Some of the important attributes the various approaches are pointed out. Some of the packaging issues a system engineer should consider when attempting to baseline a packaging approach are discussed. Four major categories of advanced packaging techniques are considered. They are: high I/O single-chip packages, multichip modules, chip-on-board, and monolithic wafer scale integration.<>
{"title":"Systems engineering: a summary of electronics packaging techniques available for present and future systems","authors":"S. A. Coogan","doi":"10.1109/ASIC.1990.186112","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186112","url":null,"abstract":"The different microelectronics packaging approaches currently available and in development are summarized for system engineers. Some of the important attributes the various approaches are pointed out. Some of the packaging issues a system engineer should consider when attempting to baseline a packaging approach are discussed. Four major categories of advanced packaging techniques are considered. They are: high I/O single-chip packages, multichip modules, chip-on-board, and monolithic wafer scale integration.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122984021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186195
D. Chakravarty, S. Pal
BiCMOS technology and product architecture trends are examined. These trends are focused onto the emerging needs of systems architectures. Advantages and disadvantages of bipolar and CMOS technologies are discussed, demonstrating the ideal compromise that BiCMOS technology offers the systems designer. A systems perspective emphasizes BiCMOS technology as the solution to an environment that demands high performance as well as drive capability. Based on this BiCMOS technology, product, cost, and CAD support directions are projected.<>
{"title":"BiCMOS ASIC trends-from a systems perspective","authors":"D. Chakravarty, S. Pal","doi":"10.1109/ASIC.1990.186195","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186195","url":null,"abstract":"BiCMOS technology and product architecture trends are examined. These trends are focused onto the emerging needs of systems architectures. Advantages and disadvantages of bipolar and CMOS technologies are discussed, demonstrating the ideal compromise that BiCMOS technology offers the systems designer. A systems perspective emphasizes BiCMOS technology as the solution to an environment that demands high performance as well as drive capability. Based on this BiCMOS technology, product, cost, and CAD support directions are projected.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125233098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186154
J. Koeter
A design that was described and simulated behaviorally in Verilog, and synthesized and optimized using Synopsys, is discussed., IEEE 1149.1-compatible (Scope) logic was added to the optimized design and Mentor gate-level simulations were performed. The performance and area impact on the chip of the Scope logic is examined and synthesis is used to minimize it.<>
{"title":"Designing IEEE 1149.1 compatible boundary-scan logic into an ASIC using Texas Instrument's Scope architecture","authors":"J. Koeter","doi":"10.1109/ASIC.1990.186154","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186154","url":null,"abstract":"A design that was described and simulated behaviorally in Verilog, and synthesized and optimized using Synopsys, is discussed., IEEE 1149.1-compatible (Scope) logic was added to the optimized design and Mentor gate-level simulations were performed. The performance and area impact on the chip of the Scope logic is examined and synthesis is used to minimize it.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129701366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186162
L.-M. Dahl, G. Djaja, L. Mah, D. Schucker
An important factor in bringing a new product to market for a successful ASIC business is the generation of design data related to macrocells, such as graphic symbols, logic simulation models, input-to-output path delays, and timing parameters for the ASIC CAD system so that ASIC customers can begin designing with the new ASIC product. Logic model generation, transition from logic to circuit simulation, circuit design with estimated parasitics, circuit verification of physical layout, and encapsulation of the macrocell design CAD flow are considered.<>
{"title":"Development of an ASIC macrocell design CAD system","authors":"L.-M. Dahl, G. Djaja, L. Mah, D. Schucker","doi":"10.1109/ASIC.1990.186162","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186162","url":null,"abstract":"An important factor in bringing a new product to market for a successful ASIC business is the generation of design data related to macrocells, such as graphic symbols, logic simulation models, input-to-output path delays, and timing parameters for the ASIC CAD system so that ASIC customers can begin designing with the new ASIC product. Logic model generation, transition from logic to circuit simulation, circuit design with estimated parasitics, circuit verification of physical layout, and encapsulation of the macrocell design CAD flow are considered.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131379774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186188
M. Conrath, B. Andrietti, J. Couleur
A case study of the use of ASIC technology by an original equipment manufacturer (OEM) is presented. The development process of a complex ASIC is described. The authors include the reasons for choosing an ASIC approach, the criteria for selecting and ASIC vendor, and the design cycle.<>
{"title":"System designer's realization of a core-based ASIC in a comfortable environment (microcontrollers)","authors":"M. Conrath, B. Andrietti, J. Couleur","doi":"10.1109/ASIC.1990.186188","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186188","url":null,"abstract":"A case study of the use of ASIC technology by an original equipment manufacturer (OEM) is presented. The development process of a complex ASIC is described. The authors include the reasons for choosing an ASIC approach, the criteria for selecting and ASIC vendor, and the design cycle.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116795498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186183
V. LaBuda, R. Youngblood
High-pin-count testers for silicon employing design-for-testability (DFT) techniques are examined as they relate to facilitating low-cost test of application-specific integrated circuits (ASICs). One test methodology takes advantage of DFT schemes emerging in silicon to provide inexpensive testing. Implementation of DFT as part of this low-cost test approach is presented, along with the resulting DFT versus tester flexibility tradeoffs. An evaluation of this synergy is given by looking at how key issues (e.g. test speed, silicon overhead, etc.) facing both designer and test vendor are handled.<>
{"title":"DFT standards allow optimized tester configuration to reduce cost of test","authors":"V. LaBuda, R. Youngblood","doi":"10.1109/ASIC.1990.186183","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186183","url":null,"abstract":"High-pin-count testers for silicon employing design-for-testability (DFT) techniques are examined as they relate to facilitating low-cost test of application-specific integrated circuits (ASICs). One test methodology takes advantage of DFT schemes emerging in silicon to provide inexpensive testing. Implementation of DFT as part of this low-cost test approach is presented, along with the resulting DFT versus tester flexibility tradeoffs. An evaluation of this synergy is given by looking at how key issues (e.g. test speed, silicon overhead, etc.) facing both designer and test vendor are handled.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132562335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186133
G. Lewicki
The FORESIGHT program holds regularly scheduled multiproject runs capable of providing ASIC designers prototype numbers of 1.2-, 1.5- and 2.0- mu m CMOS parts in turnarounds of four to five weeks at a fraction of the cost of a run dedicated to just one part. FORESIGHT's low cost and fast turnaround gives designers the opportunity of developing their own design libraries, as well as characterizing completed designs prior to production.<>
FORESIGHT计划定期进行多项目运行，能够在四到五周的时间内为ASIC设计人员提供1.2、1.5和2.0 μ m CMOS部件的原型数量，而成本仅为一个部件的一小部分。FORESIGHT的低成本和快速周转为设计师提供了开发自己的设计库的机会，以及在生产之前表征完成的设计。
{"title":"FORESIGHT: a fast turn-around and low cost ASIC prototyping alternative","authors":"G. Lewicki","doi":"10.1109/ASIC.1990.186133","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186133","url":null,"abstract":"The FORESIGHT program holds regularly scheduled multiproject runs capable of providing ASIC designers prototype numbers of 1.2-, 1.5- and 2.0- mu m CMOS parts in turnarounds of four to five weeks at a fraction of the cost of a run dedicated to just one part. FORESIGHT's low cost and fast turnaround gives designers the opportunity of developing their own design libraries, as well as characterizing completed designs prior to production.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131749844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186101
R. Eisenstadt
Design efforts to implement a 3-D graphics chip set are presented. The set contains designs ranging from a 10000-gate 1.5-micron gate array to a 208-pin, 50000+-gate 1.0-micron silicon compiled design containing RAM and datapath structures. The resulting graphics system contains 85 ASIC chips representing 10 different designs. Overviews of design entry, logic synthesis, physical design, package selection, vector generation, simulation, and test program development are provided. Further information reflecting hardware requirements, and design cycle times is included.<>
{"title":"Case study of a high speed three-dimensional graphics chip set","authors":"R. Eisenstadt","doi":"10.1109/ASIC.1990.186101","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186101","url":null,"abstract":"Design efforts to implement a 3-D graphics chip set are presented. The set contains designs ranging from a 10000-gate 1.5-micron gate array to a 208-pin, 50000+-gate 1.0-micron silicon compiled design containing RAM and datapath structures. The resulting graphics system contains 85 ASIC chips representing 10 different designs. Overviews of design entry, logic synthesis, physical design, package selection, vector generation, simulation, and test program development are provided. Further information reflecting hardware requirements, and design cycle times is included.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125636782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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