Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186166
Mark R. Rencher, N. Cung, L. Kasel, M. Azhar, A. Fok, B. Burns, I. Miller, R. Hester
An integrated geometric driven bipolar analog/digital standard cells and semicustom design environment is presented. The semicustom design environment consists of schematic entry, circuit simulation, statistical simulation, schematic-driven symbolic cell/block layout, and verification, while the standard cell design environment contains schematic entry, behavioral simulation, verification, and place and route.<>
{"title":"An integrated geometric driven bipolar analog/digital standard cell and semi custom design environment","authors":"Mark R. Rencher, N. Cung, L. Kasel, M. Azhar, A. Fok, B. Burns, I. Miller, R. Hester","doi":"10.1109/ASIC.1990.186166","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186166","url":null,"abstract":"An integrated geometric driven bipolar analog/digital standard cells and semicustom design environment is presented. The semicustom design environment consists of schematic entry, circuit simulation, statistical simulation, schematic-driven symbolic cell/block layout, and verification, while the standard cell design environment contains schematic entry, behavioral simulation, verification, and place and route.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"71 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186131
M. Tokuda, Z. Oka, H. Nakayama, H. Kobayashi
A quick turn-around time (QTAT) approach to ASIC design using a rule-based expert system called Knowledge Based Silicon Compiler (KBSC) is described. KBSC provides ASIC designers with an interactive graphic interface for flow chart entry to automatic logic synthesis. KBSC took approximately 1/5 the time required by non-KBSC methods.<>
{"title":"Quick turn around time ASIC design using KBSC","authors":"M. Tokuda, Z. Oka, H. Nakayama, H. Kobayashi","doi":"10.1109/ASIC.1990.186131","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186131","url":null,"abstract":"A quick turn-around time (QTAT) approach to ASIC design using a rule-based expert system called Knowledge Based Silicon Compiler (KBSC) is described. KBSC provides ASIC designers with an interactive graphic interface for flow chart entry to automatic logic synthesis. KBSC took approximately 1/5 the time required by non-KBSC methods.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116746264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186071
J. Lewis, S. Carlson, J. Rau
Following a brief introduction to hardware description language (HDL) synthesis and logic synthesis, the impact of synthesis technology on the various aspects of an ASIC product's lifecycle is enumerated. An ASIC synthesis cost model is presented along with the various assumptions and associated justification that have been made. A partial empirical test of the model is made via a set of actual design case studies.<>
{"title":"ASIC synthesis cost model","authors":"J. Lewis, S. Carlson, J. Rau","doi":"10.1109/ASIC.1990.186071","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186071","url":null,"abstract":"Following a brief introduction to hardware description language (HDL) synthesis and logic synthesis, the impact of synthesis technology on the various aspects of an ASIC product's lifecycle is enumerated. An ASIC synthesis cost model is presented along with the various assumptions and associated justification that have been made. A partial empirical test of the model is made via a set of actual design case studies.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186127
D. Artz, R. Rebello
Netpar, a netlist partitioner tool developed to speed up and automate the process of layout partitioning and preparation is described. The Netpar partitioning commands allow the user to quickly convert the netlist into a good layout hierarchy. Instead of recapturing schematics, the user can easily direct Netpar to restructure the netlist for layout compatibility. Additionally, an automatic partitioner is available that attempts to equalize block sizes and minimize interconnect. This implements well-documented and tested algorithms for generating optimally partitioned netlists. Netpar's automatic and manual commands can be used to quickly modify hierarchy to improve design performance, turnaround times, and densities.<>
{"title":"A solution to mapping an ASIC design hierarchy into an efficient block-place-and-route layout hierarchy","authors":"D. Artz, R. Rebello","doi":"10.1109/ASIC.1990.186127","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186127","url":null,"abstract":"Netpar, a netlist partitioner tool developed to speed up and automate the process of layout partitioning and preparation is described. The Netpar partitioning commands allow the user to quickly convert the netlist into a good layout hierarchy. Instead of recapturing schematics, the user can easily direct Netpar to restructure the netlist for layout compatibility. Additionally, an automatic partitioner is available that attempts to equalize block sizes and minimize interconnect. This implements well-documented and tested algorithms for generating optimally partitioned netlists. Netpar's automatic and manual commands can be used to quickly modify hierarchy to improve design performance, turnaround times, and densities.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123020681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186102
B. Paratore, J. C. Crichton
The design methodology used for development of a spread spectrum preprocessor (SSPP) is described. The SSPP in conjunction with a digital signal processor (DSP) functions as a digital demodulator for satellite communications. The key element of the design process was the combination or circuit-level and system-level functional verification. This approach ensured that the ASIC architecture supported the required DSP algorithms, and that the hardware implementation performed as intended. As a result, subtle flaws were detected early, the development was smooth, the layout was efficient, and this ASIC was a first silicon success.<>
{"title":"Spread spectrum pre-processor ASIC design: a case study","authors":"B. Paratore, J. C. Crichton","doi":"10.1109/ASIC.1990.186102","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186102","url":null,"abstract":"The design methodology used for development of a spread spectrum preprocessor (SSPP) is described. The SSPP in conjunction with a digital signal processor (DSP) functions as a digital demodulator for satellite communications. The key element of the design process was the combination or circuit-level and system-level functional verification. This approach ensured that the ASIC architecture supported the required DSP algorithms, and that the hardware implementation performed as intended. As a result, subtle flaws were detected early, the development was smooth, the layout was efficient, and this ASIC was a first silicon success.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131151784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186104
E. Parrella
A configurable multichip memory module designed in silicon-on-silicon hybrid form is discussed. The memory controller IC, which has been implemented in a CMOS gate array, also functions as an in-circuit tester for the memory chips. This capability, supplemented by the controller's own scan-path and boundary-scan features, results in increased in-field testability as well as greatly reduced production test costs.<>
{"title":"Testability features in a high-density memory module","authors":"E. Parrella","doi":"10.1109/ASIC.1990.186104","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186104","url":null,"abstract":"A configurable multichip memory module designed in silicon-on-silicon hybrid form is discussed. The memory controller IC, which has been implemented in a CMOS gate array, also functions as an in-circuit tester for the memory chips. This capability, supplemented by the controller's own scan-path and boundary-scan features, results in increased in-field testability as well as greatly reduced production test costs.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131520965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186118
S. Cravatta
Following a discussion of several approaches to logic cell emulation in ASIC in-circuit emulators (ICE) programmable logic components (PLCs) are selected as the recommended approach to the problem. User-programmable logic components allow ASIC ICE units to maintain flexibility through reprogrammability. Since they are reusable, PLCs inherently become cost-effective. Over the past five years PLC densities have grown four-fold, further reducing costs. Utilizing these programmable logic devices for logic cell emulation allows ASIC ICE units to provide full-chip emulation capability for use in many ASIC applications.<>
{"title":"Logic cell emulation for ASIC in-circuit emulators","authors":"S. Cravatta","doi":"10.1109/ASIC.1990.186118","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186118","url":null,"abstract":"Following a discussion of several approaches to logic cell emulation in ASIC in-circuit emulators (ICE) programmable logic components (PLCs) are selected as the recommended approach to the problem. User-programmable logic components allow ASIC ICE units to maintain flexibility through reprogrammability. Since they are reusable, PLCs inherently become cost-effective. Over the past five years PLC densities have grown four-fold, further reducing costs. Utilizing these programmable logic devices for logic cell emulation allows ASIC ICE units to provide full-chip emulation capability for use in many ASIC applications.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132582244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186138
C. Ditzen, J. Haight
Various implementations for ASIC construction of infinite impulse response (IIR) filters are examined. Tradeoffs for size, speed, stability, power, ease of design, and versatility in the light of the parameterizability possible in an ASIC environment are also studied.<>
{"title":"A parameterizable biquad clock for IIR filters in ASICs: implementations and motivations","authors":"C. Ditzen, J. Haight","doi":"10.1109/ASIC.1990.186138","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186138","url":null,"abstract":"Various implementations for ASIC construction of infinite impulse response (IIR) filters are examined. Tradeoffs for size, speed, stability, power, ease of design, and versatility in the light of the parameterizability possible in an ASIC environment are also studied.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133919083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186084
J. Tanner, A. Adke, D. Lipin
Recent advances in design hardware, software, and prototypes that allow affordable ASIC design are discussed. The topics discussed include economics of ASIC use and fabrication, affordable design platforms, affordable design tools, traditional gate array and standard cell technologies, field programmable gate arrays, affordable prototypes through multi-project wafers, and affordable volume production.<>
{"title":"Affordable ASIC design","authors":"J. Tanner, A. Adke, D. Lipin","doi":"10.1109/ASIC.1990.186084","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186084","url":null,"abstract":"Recent advances in design hardware, software, and prototypes that allow affordable ASIC design are discussed. The topics discussed include economics of ASIC use and fabrication, affordable design platforms, affordable design tools, traditional gate array and standard cell technologies, field programmable gate arrays, affordable prototypes through multi-project wafers, and affordable volume production.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-17DOI: 10.1109/ASIC.1990.186097
L. R. Ferreira
A set of ICs that can execute the bearer functions of one user network in an ISDN has been developed. This set consists of two chips for treatment of the physical layer (layer 1 of the OSI Reference Model) of the S and U interfaces, one chip for terminal adaptation and one chip for treatment of the link layer protocol carried by the D channel, the so called LAPD. The development of two of these chips is discussed. The first is the U interface layer 1 chip. The second, called TB22, is for the treatment of the signaling layer 2 function at D channel. Designed as a full custom ASIC, TB22 uses CMOS 1.25- mu m technology and has around 50000 transistors. A large demand for this device is expected.<>
{"title":"A complete VLSI treatment for the LAPD protocol (ISDN level 2)","authors":"L. R. Ferreira","doi":"10.1109/ASIC.1990.186097","DOIUrl":"https://doi.org/10.1109/ASIC.1990.186097","url":null,"abstract":"A set of ICs that can execute the bearer functions of one user network in an ISDN has been developed. This set consists of two chips for treatment of the physical layer (layer 1 of the OSI Reference Model) of the S and U interfaces, one chip for terminal adaptation and one chip for treatment of the link layer protocol carried by the D channel, the so called LAPD. The development of two of these chips is discussed. The first is the U interface layer 1 chip. The second, called TB22, is for the treatment of the signaling layer 2 function at D channel. Designed as a full custom ASIC, TB22 uses CMOS 1.25- mu m technology and has around 50000 transistors. A large demand for this device is expected.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"19 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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