Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043383
S. Kazeminia, K. Hadidi, A. Khoei, M. Azarmanesh
In this paper the equations of basic bandgap reference (BGR) voltage circuits are reconstructed considering dependency of bandgap energy (Eg) to absolute temperature. Notice that previous works all consider Eg as a constant, independent of temperature variations. Dependence of bandgap energy to absolute temperature is firstly approximated by a second-degree polynomial using Lagrangian interpolating polynomial method in temperature range of 2°C to 92°C. Then the simplified polynomial is used to calculate the modified thermal coefficient (TC) of the base-emitter voltage (VBE) in BJT transistors. Accurate analysis of the resulted equations reveals that the TC of VBE must be corrected to −1.7mV/°K at 27°C ambient temperature which has been formerly reported about −1.5mV/°K ([2], [5]), −2mV/°K ([3], [9], [10]) and −2.2mV/°K ([4], [8]) where Eg was assumed as a temperature-independent constant. More important, TC of VBE is derived to be −1.5mV/°K at 92°C rather than previously reported, −1.2mV/°K, a 20% error originated from constant Eg assumption.
{"title":"Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage","authors":"S. Kazeminia, K. Hadidi, A. Khoei, M. Azarmanesh","doi":"10.1109/ECCTD.2011.6043383","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043383","url":null,"abstract":"In this paper the equations of basic bandgap reference (BGR) voltage circuits are reconstructed considering dependency of bandgap energy (E<inf>g</inf>) to absolute temperature. Notice that previous works all consider E<inf>g</inf> as a constant, independent of temperature variations. Dependence of bandgap energy to absolute temperature is firstly approximated by a second-degree polynomial using Lagrangian interpolating polynomial method in temperature range of 2°C to 92°C. Then the simplified polynomial is used to calculate the modified thermal coefficient (TC) of the base-emitter voltage (V<inf>BE</inf>) in BJT transistors. Accurate analysis of the resulted equations reveals that the TC of V<inf>BE</inf> must be corrected to −1.7mV/°K at 27°C ambient temperature which has been formerly reported about −1.5mV/°K ([2], [5]), −2mV/°K ([3], [9], [10]) and −2.2mV/°K ([4], [8]) where E<inf>g</inf> was assumed as a temperature-independent constant. More important, TC of V<inf>BE</inf> is derived to be −1.5mV/°K at 92°C rather than previously reported, −1.2mV/°K, a 20% error originated from constant E<inf>g</inf> assumption.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130212663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043637
J. Dobes, D. Cerny, D. Biolek
In the paper, an efficient and reliable algorithm for solving the circuit algebraic-differential equations is characterized first, which is based on a sophisticated arrangement of the Newton interpolation polynomial. For enhancing the efficiency of repeated solutions of linear systems necessary in the Newton-Raphson method, a novel modification of the Markowitz criterion is suggested, which is compatible with the fast modes of the LU factorization. The modified criterion consists in an estimation of probabilities of the fill-in enlargement. The probabilities are determined for all columns of the system matrix before the LU factorization, where the column probability is calculated as the average value of the probabilities for all the column elements. Finally, the columns are reordered so that first and last should be those with the minimum and maximum probabilities, respectively. As a verification of the proposed algorithm, a comprehensive set of numerical tests has been performed.
{"title":"Efficient procedure for solving circuit algebraic-differential equations with modified sparse LU factorization improving fill-in suppression","authors":"J. Dobes, D. Cerny, D. Biolek","doi":"10.1109/ECCTD.2011.6043637","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043637","url":null,"abstract":"In the paper, an efficient and reliable algorithm for solving the circuit algebraic-differential equations is characterized first, which is based on a sophisticated arrangement of the Newton interpolation polynomial. For enhancing the efficiency of repeated solutions of linear systems necessary in the Newton-Raphson method, a novel modification of the Markowitz criterion is suggested, which is compatible with the fast modes of the LU factorization. The modified criterion consists in an estimation of probabilities of the fill-in enlargement. The probabilities are determined for all columns of the system matrix before the LU factorization, where the column probability is calculated as the average value of the probabilities for all the column elements. Finally, the columns are reordered so that first and last should be those with the minimum and maximum probabilities, respectively. As a verification of the proposed algorithm, a comprehensive set of numerical tests has been performed.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127851563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043630
Shakeel Ahmad, J. Dabrowski
Application of the ΣΔ modulation technique to the on-chip spectral test for high-speed A/D converters is presented. The harmonic HD2/HD3 and intermodulation IM2/IM3 test is obtained with one-bit ΣΔ sequence stored in a cyclic memory or generated on line, and applied to an ADC under test through a driving buffer and a simple reconstruction filter. To achieve a dynamic range (DR) suitable for high-performance spectral measurements a frequency plan is used taking into account the type of ΣΔ modulation (low-pass and band-pass) including the FFT processing gain. Higher order modulation schemes are avoided to manage the ΣΔ quantization noise without resorting to a more complicated filter. For spectral measurements up to the Nyquist frequency, we propose a dedicated low-pass/band-pass ΣΔ modulation scheme that limits spreading of the low-frequency quantization noise by ADC under test that tends to obstruct the test measurements at high frequencies. Correction technique for NRTZ encoding suitable for ADCs with very high clock frequencies is put in perspective. The presented technique is illustrated by simulation examples of a Nyquist-rate ADC under test.
{"title":"On-chip spectral test for high-speed ADCs by ΣΔ technique","authors":"Shakeel Ahmad, J. Dabrowski","doi":"10.1109/ECCTD.2011.6043630","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043630","url":null,"abstract":"Application of the ΣΔ modulation technique to the on-chip spectral test for high-speed A/D converters is presented. The harmonic HD2/HD3 and intermodulation IM2/IM3 test is obtained with one-bit ΣΔ sequence stored in a cyclic memory or generated on line, and applied to an ADC under test through a driving buffer and a simple reconstruction filter. To achieve a dynamic range (DR) suitable for high-performance spectral measurements a frequency plan is used taking into account the type of ΣΔ modulation (low-pass and band-pass) including the FFT processing gain. Higher order modulation schemes are avoided to manage the ΣΔ quantization noise without resorting to a more complicated filter. For spectral measurements up to the Nyquist frequency, we propose a dedicated low-pass/band-pass ΣΔ modulation scheme that limits spreading of the low-frequency quantization noise by ADC under test that tends to obstruct the test measurements at high frequencies. Correction technique for NRTZ encoding suitable for ADCs with very high clock frequencies is put in perspective. The presented technique is illustrated by simulation examples of a Nyquist-rate ADC under test.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124571494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043307
G. Budzyń, T. Podzorny, J. Rzepka
This article describes a two-dimensional, quadrature, sinusoidal type signal correction. Such signals are widely popular e.g. in motor control, laser interferometry and sensors applications. It is proved that in some situations it is necessary to improve the quality of the signals in order to obtain the required parameters. We show that the optimum solution is a combination of hardware and software correction mechanisms. We report the signal improvement of a factor of more than a hundred. The proposed unique construction is also characterized by a very fast dynamic response in the range of single microseconds. This feature makes the circuit suitable for wide range of applications.
{"title":"Two-dimensional sinusoidal signal quality improvement by combined software and hardware means","authors":"G. Budzyń, T. Podzorny, J. Rzepka","doi":"10.1109/ECCTD.2011.6043307","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043307","url":null,"abstract":"This article describes a two-dimensional, quadrature, sinusoidal type signal correction. Such signals are widely popular e.g. in motor control, laser interferometry and sensors applications. It is proved that in some situations it is necessary to improve the quality of the signals in order to obtain the required parameters. We show that the optimum solution is a combination of hardware and software correction mechanisms. We report the signal improvement of a factor of more than a hundred. The proposed unique construction is also characterized by a very fast dynamic response in the range of single microseconds. This feature makes the circuit suitable for wide range of applications.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114680631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043623
Z. Galias, Xinghuo Yu
Discretization effects of second order terminal sliding mode control systems are studied. The existence of periodic solutions is investigated. Complete classification of period-2 orbits is given. The influence of system's parameters on the size of the steady state solution is studied. Theoretical results are illustrated with simulation examples.
{"title":"Periodic behaviors in discretized second-order terminal sliding mode control systems","authors":"Z. Galias, Xinghuo Yu","doi":"10.1109/ECCTD.2011.6043623","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043623","url":null,"abstract":"Discretization effects of second order terminal sliding mode control systems are studied. The existence of periodic solutions is investigated. Complete classification of period-2 orbits is given. The influence of system's parameters on the size of the steady state solution is studied. Theoretical results are illustrated with simulation examples.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116330523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043840
T. Yasuno, H. Fujisaka, T. Kamio, K. Haeiwa
A digital wave filter operating on bandpass sigma-delta (SD) modulated signals is presented in this paper. The filter is obtained by a z-domain transformation of a baseband SD domain filter which is a binary-quantized discrete model of an analog distributed parameter filter (ADPF). Thus, the design properties of various ADPFs can be utilized for constructing the presented type of digital filters. A single-flux quantum filter circuit built of superconductive Josephson junctions was found to have a potential to operate at 10GHz by circuit simulation.
{"title":"A bandpass sigma-delta domain single-flux quantum wave filter","authors":"T. Yasuno, H. Fujisaka, T. Kamio, K. Haeiwa","doi":"10.1109/ECCTD.2011.6043840","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043840","url":null,"abstract":"A digital wave filter operating on bandpass sigma-delta (SD) modulated signals is presented in this paper. The filter is obtained by a z-domain transformation of a baseband SD domain filter which is a binary-quantized discrete model of an analog distributed parameter filter (ADPF). Thus, the design properties of various ADPFs can be utilized for constructing the presented type of digital filters. A single-flux quantum filter circuit built of superconductive Josephson junctions was found to have a potential to operate at 10GHz by circuit simulation.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043362
Popong Effendrik, Wenlong Jiang, M. V. D. Gevel, Frank Verwaal, R. Staszewski
WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and high band, respectively. A key component of the ADPLL is a time-to-digital converter (TDC), which replaces the traditional phase/frequency detector and charge-pump. The TDC implementation in 40-nm CMOS technology is chosen and presented in this paper. The TDC architecture is based on a pseudo-differential structure. The TDC system has been verified at 1.2 V of power supply, 33.868 MHz frequency reference (FREF) clock and 4.25 GHz output RF frequency. It is found that the power consumption is about 2.99 mW without a clock gating scheme, but is expected to be reduced to 0.78 mW with the clock gating scheme. The INL and DNL of the TDC is lower than 0.4 LSB. The TDC resolution is between 10.84–12.55 ps. At the worst case condition, the TDC resolution of 12.55 ps will produce the in-band phase noise better than −95 dBc/Hz as required by WiMAX ADPLL system. The TDC core layout has a silicon area of only 125×11 µm2.
{"title":"Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS","authors":"Popong Effendrik, Wenlong Jiang, M. V. D. Gevel, Frank Verwaal, R. Staszewski","doi":"10.1109/ECCTD.2011.6043362","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043362","url":null,"abstract":"WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and high band, respectively. A key component of the ADPLL is a time-to-digital converter (TDC), which replaces the traditional phase/frequency detector and charge-pump. The TDC implementation in 40-nm CMOS technology is chosen and presented in this paper. The TDC architecture is based on a pseudo-differential structure. The TDC system has been verified at 1.2 V of power supply, 33.868 MHz frequency reference (FREF) clock and 4.25 GHz output RF frequency. It is found that the power consumption is about 2.99 mW without a clock gating scheme, but is expected to be reduced to 0.78 mW with the clock gating scheme. The INL and DNL of the TDC is lower than 0.4 LSB. The TDC resolution is between 10.84–12.55 ps. At the worst case condition, the TDC resolution of 12.55 ps will produce the in-band phase noise better than −95 dBc/Hz as required by WiMAX ADPLL system. The TDC core layout has a silicon area of only 125×11 µm2.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122050454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043290
A. López-Martín, Fermin Esparza-Alfaro, J. Ramírez-Angulo, R. Carvajal
A CMOS voltage-to-current converter is presented. It is based on a class AB current mirror with very low input resistance and a passive resistor connected to the input for voltage-to-current conversion. Class AB operation is achieved without extra supply voltage requirements or static power consumption, using Quasi-Floating Gate techniques. Measurement results of a differential configuration for a 0.5µm CMOS test chip prototype are presented. A measured harmonic distortion at 1MHz of −59dB is achieved for current signals 20 times larger than the bias currents. The circuit consumes 265µW using a supply voltage of ±1.65V and requires a silicon area of 0.04mm2.
{"title":"Accurate micropower class AB CMOS voltage-to-current converter","authors":"A. López-Martín, Fermin Esparza-Alfaro, J. Ramírez-Angulo, R. Carvajal","doi":"10.1109/ECCTD.2011.6043290","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043290","url":null,"abstract":"A CMOS voltage-to-current converter is presented. It is based on a class AB current mirror with very low input resistance and a passive resistor connected to the input for voltage-to-current conversion. Class AB operation is achieved without extra supply voltage requirements or static power consumption, using Quasi-Floating Gate techniques. Measurement results of a differential configuration for a 0.5µm CMOS test chip prototype are presented. A measured harmonic distortion at 1MHz of −59dB is achieved for current signals 20 times larger than the bias currents. The circuit consumes 265µW using a supply voltage of ±1.65V and requires a silicon area of 0.04mm2.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122104287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043350
Keisuke Ishizawa, T. Miyata, N. Aikawa
In this paper, we propose a design method for a variable two-channel nonuniform-division FIR filter bank. The proposed filter bank can change the notch frequency in the stopband for each filter to reduce these noise. For changing notch frequencies, filter coefficients are approximated by polynomials using variable parameters in the proposed filter bank. In addition, the proposed filter bank satisfies approximately perfect reconstruction condition, and the filter bank exhibits quasi-equiripple characteristics in the passband and stopband. Linear programming is used to design the proposed filter bank in the frequency domain. The usefulness of the proposed filter bank is demonstrated through an example.
{"title":"Designing two-channel nonuniform-division FIR filter banks with variable notches","authors":"Keisuke Ishizawa, T. Miyata, N. Aikawa","doi":"10.1109/ECCTD.2011.6043350","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043350","url":null,"abstract":"In this paper, we propose a design method for a variable two-channel nonuniform-division FIR filter bank. The proposed filter bank can change the notch frequency in the stopband for each filter to reduce these noise. For changing notch frequencies, filter coefficients are approximated by polynomials using variable parameters in the proposed filter bank. In addition, the proposed filter bank satisfies approximately perfect reconstruction condition, and the filter bank exhibits quasi-equiripple characteristics in the passband and stopband. Linear programming is used to design the proposed filter bank in the frequency domain. The usefulness of the proposed filter bank is demonstrated through an example.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125771874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043355
Andreas Krinke, J. Lienig
The design of integrated circuits involves the consideration of a large number of constraints of various types. In addition to the definition of these constraints in a constraint-driven design flow, the declaration of new, yet unknown constraint types might be necessary.
{"title":"An ontology for constraints in custom IC design","authors":"Andreas Krinke, J. Lienig","doi":"10.1109/ECCTD.2011.6043355","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043355","url":null,"abstract":"The design of integrated circuits involves the consideration of a large number of constraints of various types. In addition to the definition of these constraints in a constraint-driven design flow, the declaration of new, yet unknown constraint types might be necessary.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128292720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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