Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043366
F. Kaçar, H. Kuntman
In this paper, a new floating frequency dependent negative resistor (FDNR) simulator circuit is presented. The proposed circuits consist of two second generation negative current conveyors (CCII-) and two capacitor and one resistor. The presented topology enables the simulation of ideal floating FDNR. The performance of the proposed floating FDNR is demonstrated on a sixth order band pass filter. The proposed floating FDNR is simulated using CMOS TSMC 0.35µm technology. Simulation results are given to confirm the theoretical analysis.
{"title":"New realization of FDNR and sixth order band pass filter application","authors":"F. Kaçar, H. Kuntman","doi":"10.1109/ECCTD.2011.6043366","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043366","url":null,"abstract":"In this paper, a new floating frequency dependent negative resistor (FDNR) simulator circuit is presented. The proposed circuits consist of two second generation negative current conveyors (CCII-) and two capacitor and one resistor. The presented topology enables the simulation of ideal floating FDNR. The performance of the proposed floating FDNR is demonstrated on a sixth order band pass filter. The proposed floating FDNR is simulated using CMOS TSMC 0.35µm technology. Simulation results are given to confirm the theoretical analysis.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116441961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043374
O. Ecin, R. Viga, B. Hosticka, A. Grabmaier
This article describes a pulsed thermal Time-of-Flight (TTOF) flow sensor system as two subsystems i.e., a pulsed-wire system and a heat flow system. The entire flow sensor is regarded system-theoretically as a linear time-invariant (LTI) system and is described by its transfer function or impulse response. The characterization of the thermo-fluid dynamic signals obtained by a pulsed-wire and by a heat flow is strived. Hence, the impulse response of both pulsed-wire and heat flow is analyzed according to the flow velocity. Experimental and theoretical results are compared in a flow velocity range in air between 0.1 m/s and 1.4 m/s.
{"title":"Signal characterization of a pulsed-wire and heat flow system at a flow sensor","authors":"O. Ecin, R. Viga, B. Hosticka, A. Grabmaier","doi":"10.1109/ECCTD.2011.6043374","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043374","url":null,"abstract":"This article describes a pulsed thermal Time-of-Flight (TTOF) flow sensor system as two subsystems i.e., a pulsed-wire system and a heat flow system. The entire flow sensor is regarded system-theoretically as a linear time-invariant (LTI) system and is described by its transfer function or impulse response. The characterization of the thermo-fluid dynamic signals obtained by a pulsed-wire and by a heat flow is strived. Hence, the impulse response of both pulsed-wire and heat flow is analyzed according to the flow velocity. Experimental and theoretical results are compared in a flow velocity range in air between 0.1 m/s and 1.4 m/s.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123542325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043843
S. Dikmese, M. Renfors, H. Di̇nçer
As wireless communication devices have increased rapidly, much attention has been paid to the spectrum resources. Cognitive Radio (CR) technology has received increasing attention as a potential approach to utilize more effectively the radio frequency bands. CRs need to dynamically and reliably determine spectral holes which could be used for secondary transmissions. In this study, wideband multichannel spectrum sensing techniques are considered, using either FFT or filter bank based spectrum analysis. We focus on detecting spectral gaps between OFDM-based WLAN signals in the 2.4 GHz ISM band. It is found out that the limited spectral purity of WLAN signals, allowed by the 802.11g specifications, significantly restricts the ability to detect possible weaker signals in the spectral gaps between WLAN channels. Improved spectral purity of the primary signals greatly enhances the sensitivity of spectrum sensing, provided that spectrally well-contained filter bank based spectrum analysis methods are used.
{"title":"FFT and filter bank based spectrum sensing for WLAN signals","authors":"S. Dikmese, M. Renfors, H. Di̇nçer","doi":"10.1109/ECCTD.2011.6043843","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043843","url":null,"abstract":"As wireless communication devices have increased rapidly, much attention has been paid to the spectrum resources. Cognitive Radio (CR) technology has received increasing attention as a potential approach to utilize more effectively the radio frequency bands. CRs need to dynamically and reliably determine spectral holes which could be used for secondary transmissions. In this study, wideband multichannel spectrum sensing techniques are considered, using either FFT or filter bank based spectrum analysis. We focus on detecting spectral gaps between OFDM-based WLAN signals in the 2.4 GHz ISM band. It is found out that the limited spectral purity of WLAN signals, allowed by the 802.11g specifications, significantly restricts the ability to detect possible weaker signals in the spectral gaps between WLAN channels. Improved spectral purity of the primary signals greatly enhances the sensitivity of spectrum sensing, provided that spectrally well-contained filter bank based spectrum analysis methods are used.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128656681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043323
A. Slavova, Victoria Rashkova
The nonlinear diffusion PDE have been broadly applied in image processing. In this paper we propose a convection - diffusion filter by adding a convection term in the modified diffusion equation as a physical interpretation for removing the noise. We study the dynamics of such equations by the discretization of this convection - diffusion model via Cellular Nonlinear Networks (CNN). Numerical experiments show that our method is reasonably better in removing noise.
{"title":"A novel CNN based image denoising model","authors":"A. Slavova, Victoria Rashkova","doi":"10.1109/ECCTD.2011.6043323","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043323","url":null,"abstract":"The nonlinear diffusion PDE have been broadly applied in image processing. In this paper we propose a convection - diffusion filter by adding a convection term in the modified diffusion equation as a physical interpretation for removing the noise. We study the dynamics of such equations by the discretization of this convection - diffusion model via Cellular Nonlinear Networks (CNN). Numerical experiments show that our method is reasonably better in removing noise.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131103778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043344
J. Ramos, J. L. Ausín, J. F. Duque-Carrillo, G. Torelli
This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process and mismatch variations was designed in 0.35-µm CMOS technology to operate over a dc-to-20-MHz bandwidth. The proposed limiting amplifier draws 280 µA from a 2-V supply and achieves a voltage gain of 75 dB.
{"title":"Design considerations on CMOS limiting amplifiers for wearable biomedical systems","authors":"J. Ramos, J. L. Ausín, J. F. Duque-Carrillo, G. Torelli","doi":"10.1109/ECCTD.2011.6043344","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043344","url":null,"abstract":"This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process and mismatch variations was designed in 0.35-µm CMOS technology to operate over a dc-to-20-MHz bandwidth. The proposed limiting amplifier draws 280 µA from a 2-V supply and achieves a voltage gain of 75 dB.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124742235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043626
A. Tsuneda, Takashi Yoshida
In CDMA communications with radio waves, binary spreading sequences are used as bipolar codes taking +1 or −1. On the other hand, in on-off keying modulation such as optical communications, spreading sequences are used as unipolar codes taking 1 or 0. In this paper, performances of asynchronous SIK (sequence inversion keyed) DS/CDMA systems using unipolar codes are evaluated and compared with normal CDMA systems using bipolar codes.
{"title":"Performance evaluation of asynchronous DS/CDMA communications using unipolar codes","authors":"A. Tsuneda, Takashi Yoshida","doi":"10.1109/ECCTD.2011.6043626","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043626","url":null,"abstract":"In CDMA communications with radio waves, binary spreading sequences are used as bipolar codes taking +1 or −1. On the other hand, in on-off keying modulation such as optical communications, spreading sequences are used as unipolar codes taking 1 or 0. In this paper, performances of asynchronous SIK (sequence inversion keyed) DS/CDMA systems using unipolar codes are evaluated and compared with normal CDMA systems using bipolar codes.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043820
D. Shen, Yi-Ming Tsai
This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth preventing the requirement of bias current sources in linear amplification. This bias-less ADC adopts 1.2 V for core circuits and 1.8 V for clocking with power dissipation of 80 mW. Simulation result indicates that the SNDR achieves 35.84 dB and the maximum INL and DNL are 0.4 LSB and 0.5 LSB, respectively.
{"title":"A 6-bit bias-less pipelined ADC with open-loop amplifiers","authors":"D. Shen, Yi-Ming Tsai","doi":"10.1109/ECCTD.2011.6043820","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043820","url":null,"abstract":"This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth preventing the requirement of bias current sources in linear amplification. This bias-less ADC adopts 1.2 V for core circuits and 1.8 V for clocking with power dissipation of 80 mW. Simulation result indicates that the SNDR achieves 35.84 dB and the maximum INL and DNL are 0.4 LSB and 0.5 LSB, respectively.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127509844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043385
Chuang Bi, P. Curran, O. Feely
In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs). The behaviour of CP-PLLs in the steady state is analysed and an important feature is developed. The nonlinear state equations of CP-PLLs are linearized around the equilibrium point. The linearized discrete-time model is finally verified using behavioral simulations in Matlab and PSpice.
{"title":"Linearized discrete-time model of higher order Charge-Pump PLLs","authors":"Chuang Bi, P. Curran, O. Feely","doi":"10.1109/ECCTD.2011.6043385","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043385","url":null,"abstract":"In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs). The behaviour of CP-PLLs in the steady state is analysed and an important feature is developed. The nonlinear state equations of CP-PLLs are linearized around the equilibrium point. The linearized discrete-time model is finally verified using behavioral simulations in Matlab and PSpice.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131294291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043837
J. Saleem, A. Majid, R. Ambatipudi, H. B. Kotte, K. Bertilsson
In designing switch mode power supply (SMPS), the desirable feature is to have an efficient and compact design. The main idea is to increase the switching frequency and reduce the bulky magnetic parts of the converter. This leads to a compact size, less weight, reduced cost and increased power density of the converter. This paper presents a high frequency full bridge DC to DC converter, using a multilayer coreless printed circuit board (PCB) step-up power transformer. The converter was simulated and also implemented on the PCB. The pulse width modulated (PWM) signals were generated, using a microcontroller, to switch the Metal oxide semiconductor field effect transistor (MOSFET). The design of the converter is tested up to the power levels of 5 Watts with the switching frequency in 2 to 3MHz range. The energy efficiency of the converter is 74.86% at 2.4 MHz.
{"title":"High frequency full bridge converter using multilayer coreless printed circuit board step up power transformer","authors":"J. Saleem, A. Majid, R. Ambatipudi, H. B. Kotte, K. Bertilsson","doi":"10.1109/ECCTD.2011.6043837","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043837","url":null,"abstract":"In designing switch mode power supply (SMPS), the desirable feature is to have an efficient and compact design. The main idea is to increase the switching frequency and reduce the bulky magnetic parts of the converter. This leads to a compact size, less weight, reduced cost and increased power density of the converter. This paper presents a high frequency full bridge DC to DC converter, using a multilayer coreless printed circuit board (PCB) step-up power transformer. The converter was simulated and also implemented on the PCB. The pulse width modulated (PWM) signals were generated, using a microcontroller, to switch the Metal oxide semiconductor field effect transistor (MOSFET). The design of the converter is tested up to the power levels of 5 Watts with the switching frequency in 2 to 3MHz range. The energy efficiency of the converter is 74.86% at 2.4 MHz.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"62 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122379068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043373
P. Maj, P. Grybos, R. Szczygiel
This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 × 32 pixels with the size of 100µm × 100µm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16-bit ripple counters. The nominal power consumption per pixel is 42 µW. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 µV/e− or 64 µV/e− in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e− rms and rises to 106 e− rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to a 12 e− rms at the input. A dead time in the front-end as low as 117 ns (paralyzable model) can be set. The chip can operate in the continuous readout mode and in readout mode separate from exposure. The ideas of building large area detector using through silicon via is also presented.
{"title":"Development of a fast readout chip in deep submicron technology for pixel hybrid detectors","authors":"P. Maj, P. Grybos, R. Szczygiel","doi":"10.1109/ECCTD.2011.6043373","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043373","url":null,"abstract":"This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 × 32 pixels with the size of 100µm × 100µm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16-bit ripple counters. The nominal power consumption per pixel is 42 µW. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 µV/e<sup>−</sup> or 64 µV/e<sup>−</sup> in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e<sup>−</sup> rms and rises to 106 e<sup>−</sup> rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to a 12 e<sup>−</sup> rms at the input. A dead time in the front-end as low as 117 ns (paralyzable model) can be set. The chip can operate in the continuous readout mode and in readout mode separate from exposure. The ideas of building large area detector using through silicon via is also presented.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124211922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：