Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043366
F. Kaçar, H. Kuntman
In this paper, a new floating frequency dependent negative resistor (FDNR) simulator circuit is presented. The proposed circuits consist of two second generation negative current conveyors (CCII-) and two capacitor and one resistor. The presented topology enables the simulation of ideal floating FDNR. The performance of the proposed floating FDNR is demonstrated on a sixth order band pass filter. The proposed floating FDNR is simulated using CMOS TSMC 0.35µm technology. Simulation results are given to confirm the theoretical analysis.
{"title":"New realization of FDNR and sixth order band pass filter application","authors":"F. Kaçar, H. Kuntman","doi":"10.1109/ECCTD.2011.6043366","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043366","url":null,"abstract":"In this paper, a new floating frequency dependent negative resistor (FDNR) simulator circuit is presented. The proposed circuits consist of two second generation negative current conveyors (CCII-) and two capacitor and one resistor. The presented topology enables the simulation of ideal floating FDNR. The performance of the proposed floating FDNR is demonstrated on a sixth order band pass filter. The proposed floating FDNR is simulated using CMOS TSMC 0.35µm technology. Simulation results are given to confirm the theoretical analysis.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116441961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043301
L. Nicolosi, R. Tetzlaff, A. Blug, H. Höfler, D. Carl, F. Abt, A. Heider
This paper deals with the realization of a visual monitoring system for the real time detection of spatters in laser beam welding (LBW). Spatters deteriorate the corrosion resistance and the aesthetics of the welding result. Therefore, the real time detection of spatters allows providing on-line quality information about the process, thus reducing material waste in production chains. The proposed Cellular Neural Network (CNN) based algorithm has been implemented in the Eye-RIS vision system (VS). Monitoring rates up to 15 kHz have been reached, allowing the integration of the spatter detection with the evaluation of additional image features, e.g. the full penetration hole (FPH).
{"title":"A monitoring system for laser beam welding based on an algorithm for spatter detection","authors":"L. Nicolosi, R. Tetzlaff, A. Blug, H. Höfler, D. Carl, F. Abt, A. Heider","doi":"10.1109/ECCTD.2011.6043301","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043301","url":null,"abstract":"This paper deals with the realization of a visual monitoring system for the real time detection of spatters in laser beam welding (LBW). Spatters deteriorate the corrosion resistance and the aesthetics of the welding result. Therefore, the real time detection of spatters allows providing on-line quality information about the process, thus reducing material waste in production chains. The proposed Cellular Neural Network (CNN) based algorithm has been implemented in the Eye-RIS vision system (VS). Monitoring rates up to 15 kHz have been reached, allowing the integration of the spatter detection with the evaluation of additional image features, e.g. the full penetration hole (FPH).","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125115007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043820
D. Shen, Yi-Ming Tsai
This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth preventing the requirement of bias current sources in linear amplification. This bias-less ADC adopts 1.2 V for core circuits and 1.8 V for clocking with power dissipation of 80 mW. Simulation result indicates that the SNDR achieves 35.84 dB and the maximum INL and DNL are 0.4 LSB and 0.5 LSB, respectively.
{"title":"A 6-bit bias-less pipelined ADC with open-loop amplifiers","authors":"D. Shen, Yi-Ming Tsai","doi":"10.1109/ECCTD.2011.6043820","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043820","url":null,"abstract":"This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth preventing the requirement of bias current sources in linear amplification. This bias-less ADC adopts 1.2 V for core circuits and 1.8 V for clocking with power dissipation of 80 mW. Simulation result indicates that the SNDR achieves 35.84 dB and the maximum INL and DNL are 0.4 LSB and 0.5 LSB, respectively.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127509844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043626
A. Tsuneda, Takashi Yoshida
In CDMA communications with radio waves, binary spreading sequences are used as bipolar codes taking +1 or −1. On the other hand, in on-off keying modulation such as optical communications, spreading sequences are used as unipolar codes taking 1 or 0. In this paper, performances of asynchronous SIK (sequence inversion keyed) DS/CDMA systems using unipolar codes are evaluated and compared with normal CDMA systems using bipolar codes.
{"title":"Performance evaluation of asynchronous DS/CDMA communications using unipolar codes","authors":"A. Tsuneda, Takashi Yoshida","doi":"10.1109/ECCTD.2011.6043626","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043626","url":null,"abstract":"In CDMA communications with radio waves, binary spreading sequences are used as bipolar codes taking +1 or −1. On the other hand, in on-off keying modulation such as optical communications, spreading sequences are used as unipolar codes taking 1 or 0. In this paper, performances of asynchronous SIK (sequence inversion keyed) DS/CDMA systems using unipolar codes are evaluated and compared with normal CDMA systems using bipolar codes.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043385
Chuang Bi, P. Curran, O. Feely
In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs). The behaviour of CP-PLLs in the steady state is analysed and an important feature is developed. The nonlinear state equations of CP-PLLs are linearized around the equilibrium point. The linearized discrete-time model is finally verified using behavioral simulations in Matlab and PSpice.
{"title":"Linearized discrete-time model of higher order Charge-Pump PLLs","authors":"Chuang Bi, P. Curran, O. Feely","doi":"10.1109/ECCTD.2011.6043385","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043385","url":null,"abstract":"In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs). The behaviour of CP-PLLs in the steady state is analysed and an important feature is developed. The nonlinear state equations of CP-PLLs are linearized around the equilibrium point. The linearized discrete-time model is finally verified using behavioral simulations in Matlab and PSpice.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131294291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043631
Michael Soudan, C. Vogel
In this paper, a low complexity algorithm for the design of a time-varying correction filter of finite impulse response (FIR) type is presented. Using the obtained filter design to correct a preceding time-varying system, a correction performance in the least-squares sense can be ensured. The adaptation of the filter design requires a moderate computational complexity and is suitable for real-time applications. Thus, a correction of non-periodically time-varying systems can be achieved where design methods, which rely on computationally intensive operations, e.g. numerical integration, can not be applied. At the same time, its application is not limited to weakly time-varying systems as iterative solutions are, which can correct for weakly time-varying behavior by gradually reducing the induced signal error over multiple stages.
{"title":"Low complexity least-squares filter design for the correction of linear time-varying systems","authors":"Michael Soudan, C. Vogel","doi":"10.1109/ECCTD.2011.6043631","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043631","url":null,"abstract":"In this paper, a low complexity algorithm for the design of a time-varying correction filter of finite impulse response (FIR) type is presented. Using the obtained filter design to correct a preceding time-varying system, a correction performance in the least-squares sense can be ensured. The adaptation of the filter design requires a moderate computational complexity and is suitable for real-time applications. Thus, a correction of non-periodically time-varying systems can be achieved where design methods, which rely on computationally intensive operations, e.g. numerical integration, can not be applied. At the same time, its application is not limited to weakly time-varying systems as iterative solutions are, which can correct for weakly time-varying behavior by gradually reducing the induced signal error over multiple stages.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133460708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043353
M. Blok
In this paper the practical aspects of the extracted window method applied to the nearly optimal fractional sample delay (FSD) filter design has been investigated. As the window method is one of the most numerically efficient digital filter design methods, this approach is well suited for variable fractional sample delay (VFSD) filter implementations which require frequent impulse response recalculation. On the other hand, the use of symmetric window extracted from the optimal filter (minimax or least squared error) solves the problem of window selection and results in nearly optimal high performance VFSD filters. However, the design procedure requires additional gain correction dependent on fractional delay. As the optimal gain correction factor computation should not be performed at runtime, low order polynomial approximation has been investigated in this paper. Additionally, performance loss resulting from limited word length in fixed-point arithmetic has also been discussed.
{"title":"On practical aspects of optimal FSD filter design using extracted window method","authors":"M. Blok","doi":"10.1109/ECCTD.2011.6043353","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043353","url":null,"abstract":"In this paper the practical aspects of the extracted window method applied to the nearly optimal fractional sample delay (FSD) filter design has been investigated. As the window method is one of the most numerically efficient digital filter design methods, this approach is well suited for variable fractional sample delay (VFSD) filter implementations which require frequent impulse response recalculation. On the other hand, the use of symmetric window extracted from the optimal filter (minimax or least squared error) solves the problem of window selection and results in nearly optimal high performance VFSD filters. However, the design procedure requires additional gain correction dependent on fractional delay. As the optimal gain correction factor computation should not be performed at runtime, low order polynomial approximation has been investigated in this paper. Additionally, performance loss resulting from limited word length in fixed-point arithmetic has also been discussed.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132168661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043335
Nadeem Afzal, M. Sadeghifar, J. Wikner
In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.
{"title":"A study on power consumption of modified noise-shaper architectures for ΣΔ DACs","authors":"Nadeem Afzal, M. Sadeghifar, J. Wikner","doi":"10.1109/ECCTD.2011.6043335","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043335","url":null,"abstract":"In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133948247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043837
J. Saleem, A. Majid, R. Ambatipudi, H. B. Kotte, K. Bertilsson
In designing switch mode power supply (SMPS), the desirable feature is to have an efficient and compact design. The main idea is to increase the switching frequency and reduce the bulky magnetic parts of the converter. This leads to a compact size, less weight, reduced cost and increased power density of the converter. This paper presents a high frequency full bridge DC to DC converter, using a multilayer coreless printed circuit board (PCB) step-up power transformer. The converter was simulated and also implemented on the PCB. The pulse width modulated (PWM) signals were generated, using a microcontroller, to switch the Metal oxide semiconductor field effect transistor (MOSFET). The design of the converter is tested up to the power levels of 5 Watts with the switching frequency in 2 to 3MHz range. The energy efficiency of the converter is 74.86% at 2.4 MHz.
{"title":"High frequency full bridge converter using multilayer coreless printed circuit board step up power transformer","authors":"J. Saleem, A. Majid, R. Ambatipudi, H. B. Kotte, K. Bertilsson","doi":"10.1109/ECCTD.2011.6043837","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043837","url":null,"abstract":"In designing switch mode power supply (SMPS), the desirable feature is to have an efficient and compact design. The main idea is to increase the switching frequency and reduce the bulky magnetic parts of the converter. This leads to a compact size, less weight, reduced cost and increased power density of the converter. This paper presents a high frequency full bridge DC to DC converter, using a multilayer coreless printed circuit board (PCB) step-up power transformer. The converter was simulated and also implemented on the PCB. The pulse width modulated (PWM) signals were generated, using a microcontroller, to switch the Metal oxide semiconductor field effect transistor (MOSFET). The design of the converter is tested up to the power levels of 5 Watts with the switching frequency in 2 to 3MHz range. The energy efficiency of the converter is 74.86% at 2.4 MHz.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122379068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043373
P. Maj, P. Grybos, R. Szczygiel
This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 × 32 pixels with the size of 100µm × 100µm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16-bit ripple counters. The nominal power consumption per pixel is 42 µW. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 µV/e− or 64 µV/e− in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e− rms and rises to 106 e− rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to a 12 e− rms at the input. A dead time in the front-end as low as 117 ns (paralyzable model) can be set. The chip can operate in the continuous readout mode and in readout mode separate from exposure. The ideas of building large area detector using through silicon via is also presented.
{"title":"Development of a fast readout chip in deep submicron technology for pixel hybrid detectors","authors":"P. Maj, P. Grybos, R. Szczygiel","doi":"10.1109/ECCTD.2011.6043373","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043373","url":null,"abstract":"This paper presents a design and measurements of multichannel integrated circuits in 90 nm CMOS dedicated to readout of hybrid pixels detectors in imaging applications. The chip contains a matrix of 40 × 32 pixels with the size of 100µm × 100µm. Each pixel contains a charge sensitive amplifier, a main amplifier stage, two discriminators with trim DACs and two 16-bit ripple counters. The nominal power consumption per pixel is 42 µW. The effective peaking time at the discriminator input is 28 ns and it is mainly determined by the time constants of the CSA. The gain is equal to 32 µV/e<sup>−</sup> or 64 µV/e<sup>−</sup> in the low and the high gain mode respectively. In the high gain mode the ENC without the detector is 91 e<sup>−</sup> rms and rises to 106 e<sup>−</sup> rms with stud bump-bonded pixel detector. The effective threshold spread at the discriminator input is only 0.76 mV (at one sigma level, with 7-bit trim DACs enabled), which corresponds to a 12 e<sup>−</sup> rms at the input. A dead time in the front-end as low as 117 ns (paralyzable model) can be set. The chip can operate in the continuous readout mode and in readout mode separate from exposure. The ideas of building large area detector using through silicon via is also presented.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124211922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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