Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043302
Shafqat Ali, S. Tanner, P. Farine
A novel topology for a high speed voltage level shifter (VLS) is presented. It features a built-in short circuit current reduction which increases the speed and reduces the power consumption. Unlike the conventional VLSs, the proposed VLS does not need complex digital timing signals. The simplicity of its operation results into robustness of operation, high speed and low power. The VLS was designed in CMOS 0.18um process. Simulation results, at the layout extraction level, are presented to validate the design concept. The speed and energy consumption of the VLS are compared with the state of the art VLSs. The proposed VLS proves to be better in both the speed and power aspects than the state of the art VLSs.
{"title":"A robust, low power, high speed voltage level shifter with built-in short circuit current reduction","authors":"Shafqat Ali, S. Tanner, P. Farine","doi":"10.1109/ECCTD.2011.6043302","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043302","url":null,"abstract":"A novel topology for a high speed voltage level shifter (VLS) is presented. It features a built-in short circuit current reduction which increases the speed and reduces the power consumption. Unlike the conventional VLSs, the proposed VLS does not need complex digital timing signals. The simplicity of its operation results into robustness of operation, high speed and low power. The VLS was designed in CMOS 0.18um process. Simulation results, at the layout extraction level, are presented to validate the design concept. The speed and energy consumption of the VLS are compared with the state of the art VLSs. The proposed VLS proves to be better in both the speed and power aspects than the state of the art VLSs.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122192476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043359
Tao Xu, Xingyu Zhou, Linyong Shen, M. Condon
A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N PLL and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed SPLL.
{"title":"A design methodology to enable sampling PLLs to synthesise fractional-N frequencies","authors":"Tao Xu, Xingyu Zhou, Linyong Shen, M. Condon","doi":"10.1109/ECCTD.2011.6043359","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043359","url":null,"abstract":"A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N PLL and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed SPLL.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116056404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043833
M. Sayginer, M. Yazgi, A. Toker, H. Kuntman, B. Virdee
This paper presents two integrated class-A travelling wave medium power amplifiers employing 0.35µm SiGe HBT process. The first amplifier realized is a 1.3×1mm2 device comprising of a single-stage configuration using a single transistor that exhibits an average small-signal gain of 7dB and power level of 14dBm between 0.25 to 2.5GHz while maintaining power-added efficiency in the range 30% to 10%. The second amplifier is 1.8×2.3mm2 device comprising of a driver stage cascaded with two identical amplifier stages in a parallel configuration whose outputs are combined together to enhance the devices output power by 3dB across the wideband frequency range. This amplifier's unique topology is implemented using a version of the first amplifier. The amplifier's measured output power was approximately 18dBm, the average small-signal gain was 21dB, and efficiency between 30% to 10% across 0.2–2.2GHz.
本文介绍了两种采用0.35 μ m SiGe HBT工艺的集成a类行波中功率放大器。实现的第一个放大器是1.3×1mm2器件，由单级配置组成，使用单晶体管，在0.25至2.5GHz之间显示出7dB的平均小信号增益和14dBm的功率水平，同时保持30%至10%的功率附加效率。第二个放大器是1.8×2.3mm2装置，包括一个驱动器级联两个相同的并联配置的放大器级，其输出组合在一起，以在宽带频率范围内提高3dB的设备输出功率。该放大器的独特拓扑是使用第一个放大器的一个版本来实现的。放大器的测量输出功率约为18dBm，平均小信号增益为21dB，在0.2-2.2GHz范围内效率在30%至10%之间。
{"title":"Decade bandwidth single and cascaded travelling wave medium power amplifiers using sige hbts","authors":"M. Sayginer, M. Yazgi, A. Toker, H. Kuntman, B. Virdee","doi":"10.1109/ECCTD.2011.6043833","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043833","url":null,"abstract":"This paper presents two integrated class-A travelling wave medium power amplifiers employing 0.35µm SiGe HBT process. The first amplifier realized is a 1.3×1mm2 device comprising of a single-stage configuration using a single transistor that exhibits an average small-signal gain of 7dB and power level of 14dBm between 0.25 to 2.5GHz while maintaining power-added efficiency in the range 30% to 10%. The second amplifier is 1.8×2.3mm2 device comprising of a driver stage cascaded with two identical amplifier stages in a parallel configuration whose outputs are combined together to enhance the devices output power by 3dB across the wideband frequency range. This amplifier's unique topology is implemented using a version of the first amplifier. The amplifier's measured output power was approximately 18dBm, the average small-signal gain was 21dB, and efficiency between 30% to 10% across 0.2–2.2GHz.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":" 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113946265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043827
Yoshihiro Kato, Yasuhiro Ueda, Y. Uwate, Y. Nishio
Human's retina has the capability to identify color and luminosity. The cell identifies color is called a cone cell and identifies luminosity is called a rod cell. The color image processing using CNN was proposed by Roska et al. Additionally, Inoue et al. have used three-layer CNN based on cone cell, and performed edge enhancement. They have confirmed that edge had been detected under three-layer CNN influencing each other. However, the edge of a low luminosity portion is not detected. In this study, we propose four-layer cellular neural networks in consideration of three primary colors of light and luminosity, respectively. In this research, we show some edge detection results and confirm that the proposed CNN is effective compared with the conventional CNN and the existing CNN.
{"title":"Four-layer cellular neural networks in consideration of color and luminosity","authors":"Yoshihiro Kato, Yasuhiro Ueda, Y. Uwate, Y. Nishio","doi":"10.1109/ECCTD.2011.6043827","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043827","url":null,"abstract":"Human's retina has the capability to identify color and luminosity. The cell identifies color is called a cone cell and identifies luminosity is called a rod cell. The color image processing using CNN was proposed by Roska et al. Additionally, Inoue et al. have used three-layer CNN based on cone cell, and performed edge enhancement. They have confirmed that edge had been detected under three-layer CNN influencing each other. However, the edge of a low luminosity portion is not detected. In this study, we propose four-layer cellular neural networks in consideration of three primary colors of light and luminosity, respectively. In this research, we show some edge detection results and confirm that the proposed CNN is effective compared with the conventional CNN and the existing CNN.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122700815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043593
P. Meinerzhagen, O. Andersson, Yasser Sherazi, A. Burg, J. Rodrigues
Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-VT analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized at nominal supply voltage. Both analysis methods are able to predict the energy minimum supply voltage (EMV) of any given design. Next, the results of a sub-VT synthesis at EMV using re-characterized SCLs are compared to the initial synthesis results. Finally, the results of timing-driven synthesis in both the above-VT and the sub-VT domain are compared to the results of power-driven synthesis.
{"title":"Synthesis strategies for sub-VT systems","authors":"P. Meinerzhagen, O. Andersson, Yasser Sherazi, A. Burg, J. Rodrigues","doi":"10.1109/ECCTD.2011.6043593","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043593","url":null,"abstract":"Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-VT analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized at nominal supply voltage. Both analysis methods are able to predict the energy minimum supply voltage (EMV) of any given design. Next, the results of a sub-VT synthesis at EMV using re-characterized SCLs are compared to the initial synthesis results. Finally, the results of timing-driven synthesis in both the above-VT and the sub-VT domain are compared to the results of power-driven synthesis.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133198636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043344
J. Ramos, J. L. Ausín, J. F. Duque-Carrillo, G. Torelli
This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process and mismatch variations was designed in 0.35-µm CMOS technology to operate over a dc-to-20-MHz bandwidth. The proposed limiting amplifier draws 280 µA from a 2-V supply and achieves a voltage gain of 75 dB.
{"title":"Design considerations on CMOS limiting amplifiers for wearable biomedical systems","authors":"J. Ramos, J. L. Ausín, J. F. Duque-Carrillo, G. Torelli","doi":"10.1109/ECCTD.2011.6043344","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043344","url":null,"abstract":"This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process and mismatch variations was designed in 0.35-µm CMOS technology to operate over a dc-to-20-MHz bandwidth. The proposed limiting amplifier draws 280 µA from a 2-V supply and achieves a voltage gain of 75 dB.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124742235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043614
M. Poolakkaparambil, J. Mathew, A. Jabir, D. Pradhan
Galois field arithmetic circuits find wide variety of application in cryptography. Thus they faces majority of the hardware based attacks for malicious gain. Though there are many approaches that have been proposed to mitigate such malicious attacks, most of them are inappropriate for practical applicability due to various design drawbacks. It is noted that Galois field multipliers are one among the many core arithmetic modules that are inevitable in the cryptography processors. Among them Montgomery multipliers are studied and implemented in applications like Elliptical Curve Cryptography arithmetic. However, a multiple bit error correctable Montgomery multiplier has not yet been implemented to this end. In this paper, we propose a novel multiple bit error correctable bit-parallel Montgomery multipliers with dynamic error detection and correction. First we present the BCH code based multiple bit error correctable Montgomery multiplier design architecture. Then we propose a novel scheme for reducing the recurrent delay when no transient malicious attack is present. In comparison with the existing multiple bit error correctable bit parallel multiplier structures, our novel technique significantly reduces the delay and improves the performance.
{"title":"A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields","authors":"M. Poolakkaparambil, J. Mathew, A. Jabir, D. Pradhan","doi":"10.1109/ECCTD.2011.6043614","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043614","url":null,"abstract":"Galois field arithmetic circuits find wide variety of application in cryptography. Thus they faces majority of the hardware based attacks for malicious gain. Though there are many approaches that have been proposed to mitigate such malicious attacks, most of them are inappropriate for practical applicability due to various design drawbacks. It is noted that Galois field multipliers are one among the many core arithmetic modules that are inevitable in the cryptography processors. Among them Montgomery multipliers are studied and implemented in applications like Elliptical Curve Cryptography arithmetic. However, a multiple bit error correctable Montgomery multiplier has not yet been implemented to this end. In this paper, we propose a novel multiple bit error correctable bit-parallel Montgomery multipliers with dynamic error detection and correction. First we present the BCH code based multiple bit error correctable Montgomery multiplier design architecture. Then we propose a novel scheme for reducing the recurrent delay when no transient malicious attack is present. In comparison with the existing multiple bit error correctable bit parallel multiplier structures, our novel technique significantly reduces the delay and improves the performance.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124781018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043374
O. Ecin, R. Viga, B. Hosticka, A. Grabmaier
This article describes a pulsed thermal Time-of-Flight (TTOF) flow sensor system as two subsystems i.e., a pulsed-wire system and a heat flow system. The entire flow sensor is regarded system-theoretically as a linear time-invariant (LTI) system and is described by its transfer function or impulse response. The characterization of the thermo-fluid dynamic signals obtained by a pulsed-wire and by a heat flow is strived. Hence, the impulse response of both pulsed-wire and heat flow is analyzed according to the flow velocity. Experimental and theoretical results are compared in a flow velocity range in air between 0.1 m/s and 1.4 m/s.
{"title":"Signal characterization of a pulsed-wire and heat flow system at a flow sensor","authors":"O. Ecin, R. Viga, B. Hosticka, A. Grabmaier","doi":"10.1109/ECCTD.2011.6043374","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043374","url":null,"abstract":"This article describes a pulsed thermal Time-of-Flight (TTOF) flow sensor system as two subsystems i.e., a pulsed-wire system and a heat flow system. The entire flow sensor is regarded system-theoretically as a linear time-invariant (LTI) system and is described by its transfer function or impulse response. The characterization of the thermo-fluid dynamic signals obtained by a pulsed-wire and by a heat flow is strived. Hence, the impulse response of both pulsed-wire and heat flow is analyzed according to the flow velocity. Experimental and theoretical results are compared in a flow velocity range in air between 0.1 m/s and 1.4 m/s.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123542325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043843
S. Dikmese, M. Renfors, H. Di̇nçer
As wireless communication devices have increased rapidly, much attention has been paid to the spectrum resources. Cognitive Radio (CR) technology has received increasing attention as a potential approach to utilize more effectively the radio frequency bands. CRs need to dynamically and reliably determine spectral holes which could be used for secondary transmissions. In this study, wideband multichannel spectrum sensing techniques are considered, using either FFT or filter bank based spectrum analysis. We focus on detecting spectral gaps between OFDM-based WLAN signals in the 2.4 GHz ISM band. It is found out that the limited spectral purity of WLAN signals, allowed by the 802.11g specifications, significantly restricts the ability to detect possible weaker signals in the spectral gaps between WLAN channels. Improved spectral purity of the primary signals greatly enhances the sensitivity of spectrum sensing, provided that spectrally well-contained filter bank based spectrum analysis methods are used.
{"title":"FFT and filter bank based spectrum sensing for WLAN signals","authors":"S. Dikmese, M. Renfors, H. Di̇nçer","doi":"10.1109/ECCTD.2011.6043843","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043843","url":null,"abstract":"As wireless communication devices have increased rapidly, much attention has been paid to the spectrum resources. Cognitive Radio (CR) technology has received increasing attention as a potential approach to utilize more effectively the radio frequency bands. CRs need to dynamically and reliably determine spectral holes which could be used for secondary transmissions. In this study, wideband multichannel spectrum sensing techniques are considered, using either FFT or filter bank based spectrum analysis. We focus on detecting spectral gaps between OFDM-based WLAN signals in the 2.4 GHz ISM band. It is found out that the limited spectral purity of WLAN signals, allowed by the 802.11g specifications, significantly restricts the ability to detect possible weaker signals in the spectral gaps between WLAN channels. Improved spectral purity of the primary signals greatly enhances the sensitivity of spectrum sensing, provided that spectrally well-contained filter bank based spectrum analysis methods are used.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128656681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043323
A. Slavova, Victoria Rashkova
The nonlinear diffusion PDE have been broadly applied in image processing. In this paper we propose a convection - diffusion filter by adding a convection term in the modified diffusion equation as a physical interpretation for removing the noise. We study the dynamics of such equations by the discretization of this convection - diffusion model via Cellular Nonlinear Networks (CNN). Numerical experiments show that our method is reasonably better in removing noise.
{"title":"A novel CNN based image denoising model","authors":"A. Slavova, Victoria Rashkova","doi":"10.1109/ECCTD.2011.6043323","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043323","url":null,"abstract":"The nonlinear diffusion PDE have been broadly applied in image processing. In this paper we propose a convection - diffusion filter by adding a convection term in the modified diffusion equation as a physical interpretation for removing the noise. We study the dynamics of such equations by the discretization of this convection - diffusion model via Cellular Nonlinear Networks (CNN). Numerical experiments show that our method is reasonably better in removing noise.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131103778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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