Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043331
Akiko Takahashi, K. Tsumoto, K. Aihara, T. Kousaka
Impact oscillators appear in various fields such as nervous system, ecological system, and mechanical system. These systems have a characteristic property that the dynamics discontinuously behaves due to jumps at hitting borders in the state space. In general, it is difficult to obtain analytical solutions in this class. Thus a numerical method is indispensable for the bifurcation analysis in the impact oscillators; however, unfortunately, it has not been established. Therefore, we proposed a numerical method for the bifurcation analyses in the impact oscillator with a fixed border and applied the proposed method to the Rayleigh-type oscillator.
{"title":"Numerical method for bifurcation analysis in an impact oscillator with fixed border","authors":"Akiko Takahashi, K. Tsumoto, K. Aihara, T. Kousaka","doi":"10.1109/ECCTD.2011.6043331","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043331","url":null,"abstract":"Impact oscillators appear in various fields such as nervous system, ecological system, and mechanical system. These systems have a characteristic property that the dynamics discontinuously behaves due to jumps at hitting borders in the state space. In general, it is difficult to obtain analytical solutions in this class. Thus a numerical method is indispensable for the bifurcation analysis in the impact oscillators; however, unfortunately, it has not been established. Therefore, we proposed a numerical method for the bifurcation analyses in the impact oscillator with a fixed border and applied the proposed method to the Rayleigh-type oscillator.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133488972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043347
M. Crescentini, M. Bennati, M. Serafini, M. Tartagni
Current sensing amplifier is one of the basic blocks in biosensing interfaces as current-related phenomena are at the base of biological and chemical interfaces. A wide number of papers have been published in literature on the subject showing both continuous time (CT) and discrete time (DT) approaches. Among them, CT solutions show better performance in terms of input-referred noise floor due to the white noise folding problem with respect to DT schemes. However, the DT design offers an easier approach to structured design and better performance with respect to the scaling trend in CMOS process. This paper shows a new technique to reduce folding process in CMOS DT current amplifiers by decoupling basic noise constraints so as to compete with CT solutions.
{"title":"Noise folding reduction in discrete-time current sensing","authors":"M. Crescentini, M. Bennati, M. Serafini, M. Tartagni","doi":"10.1109/ECCTD.2011.6043347","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043347","url":null,"abstract":"Current sensing amplifier is one of the basic blocks in biosensing interfaces as current-related phenomena are at the base of biological and chemical interfaces. A wide number of papers have been published in literature on the subject showing both continuous time (CT) and discrete time (DT) approaches. Among them, CT solutions show better performance in terms of input-referred noise floor due to the white noise folding problem with respect to DT schemes. However, the DT design offers an easier approach to structured design and better performance with respect to the scaling trend in CMOS process. This paper shows a new technique to reduce folding process in CMOS DT current amplifiers by decoupling basic noise constraints so as to compete with CT solutions.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121905352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043628
S. Darfeuille, C. Kelma
Testing an RF device in Production is expensive and technically difficult. At Wafer Test level, the RF probing technologies hardly fulfil the industrial test requirements in terms of accuracy, reliability and cost. At Package test level testing the RF parameters requires expensive RF equipments (RF automated test equipments (ATE)) and for complex RF transceivers, which address multi-modes (RF multi-paths and/or requiring different impedance matchings), it usually leads to prohibitive test time.
{"title":"Production test of an RF receiver chain based on ATM combining RF BIST and machine learning algorithm","authors":"S. Darfeuille, C. Kelma","doi":"10.1109/ECCTD.2011.6043628","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043628","url":null,"abstract":"Testing an RF device in Production is expensive and technically difficult. At Wafer Test level, the RF probing technologies hardly fulfil the industrial test requirements in terms of accuracy, reliability and cost. At Package test level testing the RF parameters requires expensive RF equipments (RF automated test equipments (ATE)) and for complex RF transceivers, which address multi-modes (RF multi-paths and/or requiring different impedance matchings), it usually leads to prohibitive test time.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125786834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043629
O. Ekekon, Samed Maltabas, M. Margala
This paper proposes a new Built-In Self Test architecture to detect time interval errors (TIE) of Phase-Locked Loops. A transient current sensor utilizing Flipped Voltage Follower (FVF) is used with a comparison block in the proposed topology. It is designed and verified for IBM 65nm technology using 1 V supply voltage and capable of detecting both steady-state and transient currents up to 150 µA and 2 GHz frequency with a good accuracy. The proposed topology relies on the output voltage difference of transient sensors. Thus, it can be scalable as the technology shrinks and still be an effective method to detect new emerging faults.
{"title":"A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies","authors":"O. Ekekon, Samed Maltabas, M. Margala","doi":"10.1109/ECCTD.2011.6043629","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043629","url":null,"abstract":"This paper proposes a new Built-In Self Test architecture to detect time interval errors (TIE) of Phase-Locked Loops. A transient current sensor utilizing Flipped Voltage Follower (FVF) is used with a comparison block in the proposed topology. It is designed and verified for IBM 65nm technology using 1 V supply voltage and capable of detecting both steady-state and transient currents up to 150 µA and 2 GHz frequency with a good accuracy. The proposed topology relies on the output voltage difference of transient sensors. Thus, it can be scalable as the technology shrinks and still be an effective method to detect new emerging faults.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123417514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043354
A. Unutulmaz, Günhan Dündar, Francisco V. Fernández
Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine these approaches. However, a new type of router is required for such a combination; namely, the template router. This paper presents a template router and discusses how routing is coded and how this code is generated using the well known A* Algorithm.
{"title":"A template router","authors":"A. Unutulmaz, Günhan Dündar, Francisco V. Fernández","doi":"10.1109/ECCTD.2011.6043354","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043354","url":null,"abstract":"Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine these approaches. However, a new type of router is required for such a combination; namely, the template router. This paper presents a template router and discusses how routing is coded and how this code is generated using the well known A* Algorithm.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123791379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043616
F. Corinto, V. Lanza, A. Ascoli, M. Gilli
Networks made up of bio-inspired neuron oscillatory circuits with nanoscale memristors may achieve the large connectivity and highly parallel processing power of biological systems. Memristor also has potential to reproduce the behavior of a biological synapse. As in a living creature the weight of a synapse is adapted by ionic flow through it, so the conductance of a memristor is controlled by flux across or charge through it. In order to point out the role of memristor as biological synapse, we focus on a simple bio-inspired network composed of two FitzHugh-Nagumo (FHN) neurons coupled via a memristor. In particular, we investigate how the dynamics of memristor can influence the interactions among neurons and their synchronization.
{"title":"Synchronization in networks of FitzHugh-Nagumo neurons with memristor synapses","authors":"F. Corinto, V. Lanza, A. Ascoli, M. Gilli","doi":"10.1109/ECCTD.2011.6043616","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043616","url":null,"abstract":"Networks made up of bio-inspired neuron oscillatory circuits with nanoscale memristors may achieve the large connectivity and highly parallel processing power of biological systems. Memristor also has potential to reproduce the behavior of a biological synapse. As in a living creature the weight of a synapse is adapted by ionic flow through it, so the conductance of a memristor is controlled by flux across or charge through it. In order to point out the role of memristor as biological synapse, we focus on a simple bio-inspired network composed of two FitzHugh-Nagumo (FHN) neurons coupled via a memristor. In particular, we investigate how the dynamics of memristor can influence the interactions among neurons and their synchronization.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130311928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043821
Marc Joliveau, M. Gendreau, F. Gagnon, C. Thibeault
Current methods used to design multiplierless digital filter have demonstrated their potential to construct low complexity circuits from multiplier blocks with few adders in order to replace the multipliers of standard Finite Impulse Response structures. However, the traditional approach only provides a local optimization as it need to rely to defined circuit architectures, such as the direct form structure. This paper presents a population-based metaheuristic that constructs multiplierless non-recursive filters without referring to any circuit topology. Simulations demonstrate that our algorithm is able to design typical digital filters, such as low-pass and high-pass filters, that can be used in communication systems and that need a significantly reduced amount of power to process the signal.
{"title":"Low complexity low power non-recursive digital filters with unconstrained topology","authors":"Marc Joliveau, M. Gendreau, F. Gagnon, C. Thibeault","doi":"10.1109/ECCTD.2011.6043821","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043821","url":null,"abstract":"Current methods used to design multiplierless digital filter have demonstrated their potential to construct low complexity circuits from multiplier blocks with few adders in order to replace the multipliers of standard Finite Impulse Response structures. However, the traditional approach only provides a local optimization as it need to rely to defined circuit architectures, such as the direct form structure. This paper presents a population-based metaheuristic that constructs multiplierless non-recursive filters without referring to any circuit topology. Simulations demonstrate that our algorithm is able to design typical digital filters, such as low-pass and high-pass filters, that can be used in communication systems and that need a significantly reduced amount of power to process the signal.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130293339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043295
D. Moro-Frías, M. T. Sanz, C. A. D. L. Cruz-Blas
In this paper a novel Winner-Take-All (WTA) topology is presented which shows good trade-off between resolution and resolution speed, at the cost of some increase in power consumption. The proposed WTA is compared with other current-mode WTAs found in literature based on the same operation principle. All the topologies were designed in a 0.13µm CMOS process and characterized in terms of resolution, resolution speed, supply voltage, compactness and power consumption. The novel WTA shows the highest resolution speed and the best trade-off between performance parameters.
本文提出了一种新的赢家通吃(WTA)拓扑结构，它在分辨率和分辨率速度之间取得了很好的平衡，但代价是功耗的增加。基于相同的工作原理，将所提出的WTA与文献中发现的其他电流模式WTA进行了比较。所有拓扑结构均采用0.13 μ m CMOS工艺设计，并在分辨率、分辨率速度、电源电压、紧凑性和功耗方面进行了表征。新的WTA显示出最高的分辨率速度和性能参数之间的最佳权衡。
{"title":"A novel current-mode Winner-Take-All topology","authors":"D. Moro-Frías, M. T. Sanz, C. A. D. L. Cruz-Blas","doi":"10.1109/ECCTD.2011.6043295","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043295","url":null,"abstract":"In this paper a novel Winner-Take-All (WTA) topology is presented which shows good trade-off between resolution and resolution speed, at the cost of some increase in power consumption. The proposed WTA is compared with other current-mode WTAs found in literature based on the same operation principle. All the topologies were designed in a 0.13µm CMOS process and characterized in terms of resolution, resolution speed, supply voltage, compactness and power consumption. The novel WTA shows the highest resolution speed and the best trade-off between performance parameters.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129520975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043288
Ali Baradaranrezaeii, Roozbeh Abdollahi, K. Hadidi, A. Khoei
A high speed comparator based on a high DC-gain folded-cascode amplifier is presented. Four switches rearrange the structure to speed up the comparison process and prevent kickback noise with a simple set of controlling signals. The circuit is a rail-to-rail folded-cascode amplifier during reset/evaluation period which transforms into two back-to-back inverters during the latch period to speed up the settling. The reset and the evaluation sequences are merged due to the special structure presented. This means that higher speed is achieved while reset time can be increased to erase the previous data completely. The comparator has been simulated in different conditions such as: temperature fluctuation, variations in process corners, power supply noise of 250mVp-p, clock skew of 80ps and applying the input signal in the most critical case. Results confirm that 1GS/s with 6-bit resolution is achieved for 1.6Vp-p and 10mV offset voltage while the power consumption is about 1mW. The most of the power supply noise is rejected while kickback noise and clock feed-through is reduced as well. Using the minimum size devices leads to a compact layout and die size of about 250(µm)2.
{"title":"A 1GS/s low-power low-kickback noise comparator in CMOS process","authors":"Ali Baradaranrezaeii, Roozbeh Abdollahi, K. Hadidi, A. Khoei","doi":"10.1109/ECCTD.2011.6043288","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043288","url":null,"abstract":"A high speed comparator based on a high DC-gain folded-cascode amplifier is presented. Four switches rearrange the structure to speed up the comparison process and prevent kickback noise with a simple set of controlling signals. The circuit is a rail-to-rail folded-cascode amplifier during reset/evaluation period which transforms into two back-to-back inverters during the latch period to speed up the settling. The reset and the evaluation sequences are merged due to the special structure presented. This means that higher speed is achieved while reset time can be increased to erase the previous data completely. The comparator has been simulated in different conditions such as: temperature fluctuation, variations in process corners, power supply noise of 250mVp-p, clock skew of 80ps and applying the input signal in the most critical case. Results confirm that 1GS/s with 6-bit resolution is achieved for 1.6Vp-p and 10mV offset voltage while the power consumption is about 1mW. The most of the power supply noise is rejected while kickback noise and clock feed-through is reduced as well. Using the minimum size devices leads to a compact layout and die size of about 250(µm)2.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129699949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043618
M.Simsek Murat Simsek
Artificial neural networks have been used as an important technique in modeling and optimization for engineering design. In this work, 3-step modeling strategy based on knowledge based techniques is proposed to develop new efficient modeling instead of conventional artificial neural network (ANN) modeling. The knowledge based artificial neural networks are constructed by incorporating the existing knowledge such as empirical formulas, equivalent circuit models and semi-analytical equations in neural network structures. In this new technique, required knowledge is created in the first step and used in the second step as a coarse model. Therefore each model shows better performance than former. In this strategy, conventional ANN, prior knowledge input and prior knowledge input with difference techniques are utilized not only to improve modeling accuracy but also to reduce time consumption during modeling. The advantages of using 3-step modeling are demonstrated on Branin function modeling application.
{"title":"Developing 3-step modeling strategy exploiting knowledge based techniques","authors":"M.Simsek Murat Simsek","doi":"10.1109/ECCTD.2011.6043618","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043618","url":null,"abstract":"Artificial neural networks have been used as an important technique in modeling and optimization for engineering design. In this work, 3-step modeling strategy based on knowledge based techniques is proposed to develop new efficient modeling instead of conventional artificial neural network (ANN) modeling. The knowledge based artificial neural networks are constructed by incorporating the existing knowledge such as empirical formulas, equivalent circuit models and semi-analytical equations in neural network structures. In this new technique, required knowledge is created in the first step and used in the second step as a coarse model. Therefore each model shows better performance than former. In this strategy, conventional ANN, prior knowledge input and prior knowledge input with difference techniques are utilized not only to improve modeling accuracy but also to reduce time consumption during modeling. The advantages of using 3-step modeling are demonstrated on Branin function modeling application.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129736174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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