Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043340
Stephan Bannwarth, A. Wenzler, W. Mathis
This paper derives ƒs/2 modulation from signal and system theory of complex signals. It is presented, how the In phase and the Quadrature phase are reduced to a single phase, while all properties of complex signaling are maintained. Further, it is derived, that the remaining phase is predestinated for ΣΔ modulation. Finally, simulation results prove the theoretically derived offset-elimination property.
{"title":"Offset elimination in ΣΔ analog to digital converters by ƒs/2 modulation","authors":"Stephan Bannwarth, A. Wenzler, W. Mathis","doi":"10.1109/ECCTD.2011.6043340","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043340","url":null,"abstract":"This paper derives ƒs/2 modulation from signal and system theory of complex signals. It is presented, how the In phase and the Quadrature phase are reduced to a single phase, while all properties of complex signaling are maintained. Further, it is derived, that the remaining phase is predestinated for ΣΔ modulation. Finally, simulation results prove the theoretically derived offset-elimination property.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124235431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043402
A. Wardzinska, W. Bandurski
The scattering parameters can be powerful description of interconnect parameters. In the paper we present the closed form formulas for the scattering parameters for low loss interconnect. The method bases on multiple scales method and expands the voltage and current in series of losses parameter. The first order approximation calculate the lossless line response. The impact of losses is included in constants of solution of differential equation. The proposed formulas for scattering parameters are compared with exact calculations in frequency domain.
{"title":"VLSI low loss interconnects scattering parameters","authors":"A. Wardzinska, W. Bandurski","doi":"10.1109/ECCTD.2011.6043402","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043402","url":null,"abstract":"The scattering parameters can be powerful description of interconnect parameters. In the paper we present the closed form formulas for the scattering parameters for low loss interconnect. The method bases on multiple scales method and expands the voltage and current in series of losses parameter. The first order approximation calculate the lossless line response. The impact of losses is included in constants of solution of differential equation. The proposed formulas for scattering parameters are compared with exact calculations in frequency domain.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129291906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043310
M. Yildiz, I. C. Göknar, S. Minaei, E. Deniz
A recently built IC which implements a CMOS tunable classifier circuit is introduced and test results of an application are presented. The classifier circuit parameters are determined for Iris data set with an algorithm based on Fisher's linear discriminant analysis (LDA); the data is first soft then hard classified. The proposed circuit was fabricated using CMOS AMS 0.35 µm process parameters and its performance experimentally tested with Iris data. The layout of the IC also includes current conveyors and current buffers.
{"title":"DU-TCC 1209: A CMOS IC classifier and its application to IRIS data","authors":"M. Yildiz, I. C. Göknar, S. Minaei, E. Deniz","doi":"10.1109/ECCTD.2011.6043310","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043310","url":null,"abstract":"A recently built IC which implements a CMOS tunable classifier circuit is introduced and test results of an application are presented. The classifier circuit parameters are determined for Iris data set with an algorithm based on Fisher's linear discriminant analysis (LDA); the data is first soft then hard classified. The proposed circuit was fabricated using CMOS AMS 0.35 µm process parameters and its performance experimentally tested with Iris data. The layout of the IC also includes current conveyors and current buffers.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115898310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043361
Muhammad Touqir Pasha, M. Vesterbacka
An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre. Based on simulation results the different control schemes are characterized in terms power consumption, tuning range and noise performance so as to guide the designer about the control scheme selection.
{"title":"Frequency control schemes for single-ended ring oscillators","authors":"Muhammad Touqir Pasha, M. Vesterbacka","doi":"10.1109/ECCTD.2011.6043361","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043361","url":null,"abstract":"An analysis of frequency control techniques for inverter based ring oscillators is presented. The aim of this study is to aid the circuit designer in architecture selection appropriate for a specific application. A brief discussion on ring oscillators is presented followed by an overview of the various control schemes. The circuits are realized in a 40 nm CMOS technology and simulated using Spectre. Based on simulation results the different control schemes are characterized in terms power consumption, tuning range and noise performance so as to guide the designer about the control scheme selection.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043304
I. Vornicu, L. Goras
The paper discusses the possibility of using the dynamics of a class of Cellular Neural Networks (CNN's) for electrocardiogram (ECG) signals classification. The main idea is that of segmentation and transformation of the temporal signal into a 1D spatial one which is further processed by means of a bank of linear spatial filters using a parallel architecture of CNN type. A major advantage of the proposed solution is the independence of the filters spatial frequency characteristics on the number of samples of the ECG pattern, which allows dealing very easily with the heart rate variability. The principle of the proposed architecture is briefly discussed and the design of a bank of spatial filters for ECG classification is presented. Transistor level simulation and considerations regarding the architecture reconfiguration are given as well.
{"title":"On the design of a class of CNN's for ECG classification","authors":"I. Vornicu, L. Goras","doi":"10.1109/ECCTD.2011.6043304","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043304","url":null,"abstract":"The paper discusses the possibility of using the dynamics of a class of Cellular Neural Networks (CNN's) for electrocardiogram (ECG) signals classification. The main idea is that of segmentation and transformation of the temporal signal into a 1D spatial one which is further processed by means of a bank of linear spatial filters using a parallel architecture of CNN type. A major advantage of the proposed solution is the independence of the filters spatial frequency characteristics on the number of samples of the ECG pattern, which allows dealing very easily with the heart rate variability. The principle of the proposed architecture is briefly discussed and the design of a bank of spatial filters for ECG classification is presented. Transistor level simulation and considerations regarding the architecture reconfiguration are given as well.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114483039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043610
S. Liang, W. Redman-White
A ring oscillator is designed and implemented on standard 130nm CMOS technology for wide range frequency tuning purpose in a spectrum monitor receiver used in cognitive radio applications. The three-stage differential ring oscillator is tuned by an array of MOS varactors, which is controlled by a novel staggered voltage offset system for improved tuning linearity. The proposed ring oscillator achieves a measured tuning range from 4.85GHz to 7.15GHz, consuming 4.2mA current from a 1.2V supply voltage. The measured phase noise is −82.5 dBc/Hz at 1MHz offset from an operating frequency of 4.88GHz. The die area of the oscillator core is about 70µm×50µm.
{"title":"A linear tuning ring VCO for spectrum monitor receiver in cognitive radio applications","authors":"S. Liang, W. Redman-White","doi":"10.1109/ECCTD.2011.6043610","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043610","url":null,"abstract":"A ring oscillator is designed and implemented on standard 130nm CMOS technology for wide range frequency tuning purpose in a spectrum monitor receiver used in cognitive radio applications. The three-stage differential ring oscillator is tuned by an array of MOS varactors, which is controlled by a novel staggered voltage offset system for improved tuning linearity. The proposed ring oscillator achieves a measured tuning range from 4.85GHz to 7.15GHz, consuming 4.2mA current from a 1.2V supply voltage. The measured phase noise is −82.5 dBc/Hz at 1MHz offset from an operating frequency of 4.88GHz. The die area of the oscillator core is about 70µm×50µm.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115440293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043832
Quoc-Tai Duong, J. Dabrowski
A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 – 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 < −14 dB while the total power consumption is 3.9 mW for 1.2 V supply.
{"title":"Low noise transconductance amplifier design for continuous-time ΣΔ wideband frontend","authors":"Quoc-Tai Duong, J. Dabrowski","doi":"10.1109/ECCTD.2011.6043832","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043832","url":null,"abstract":"A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity of maximum IIP3 = 13.6 dBm over 0.8 – 5 GHz band. The maximum transconductance Gm = 11.6 mS, the return loss S11 < −14 dB while the total power consumption is 3.9 mW for 1.2 V supply.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125245748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043595
B. Jonsson
An empirical design optimization approach is explored for A/D-converter area efficiency. The die area consumption of commonly used ADC architectures is surveyed. Based on trends observed in a large set of empirical data, the area normalized to number of effective quantization steps is proposed as a generic measure of area efficiency. It is seen that state-of-the-art absolute area has a strong correlation with resolution and CMOS node, whereas the proposed measure does not. The state-of-the-art envelopes for normalized area vs. speed, resolution and noise-floor are extracted for each analyzed architecture. Empirically derived guidelines for area-optimal architecture selection based on speed-resolution requirements are given.
{"title":"Area efficiency of ADC architectures","authors":"B. Jonsson","doi":"10.1109/ECCTD.2011.6043595","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043595","url":null,"abstract":"An empirical design optimization approach is explored for A/D-converter area efficiency. The die area consumption of commonly used ADC architectures is surveyed. Based on trends observed in a large set of empirical data, the area normalized to number of effective quantization steps is proposed as a generic measure of area efficiency. It is seen that state-of-the-art absolute area has a strong correlation with resolution and CMOS node, whereas the proposed measure does not. The state-of-the-art envelopes for normalized area vs. speed, resolution and noise-floor are extracted for each analyzed architecture. Empirically derived guidelines for area-optimal architecture selection based on speed-resolution requirements are given.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125367545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043379
R. Staszewski
One of the most important developments in the wireless industry within the last decade was the digitization of RF circuitry. This was in response to the incredible advancements of the mainstream CMOS technology in both processing speed and circuit density, as well as the relentless push to reduce total solution costs through integration of RF, analog and digital circuitry. Since the digital baseband part of a wireless communication channel has been traditionally implemented in the most advanced CMOS technology available at a given time for mass production, the need for single-chip CMOS integration has forced permanent changes to the way RF circuits are fundamentally designed. In this low-voltage nanometer-scale CMOS environment, the high-performance RF circuits must exploit the time-domain design paradigm and heavily rely on digital assistance. This paper revisits the digitization journey of RF circuits.
{"title":"Digital RF architectures for wireless transceivers (invited)","authors":"R. Staszewski","doi":"10.1109/ECCTD.2011.6043379","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043379","url":null,"abstract":"One of the most important developments in the wireless industry within the last decade was the digitization of RF circuitry. This was in response to the incredible advancements of the mainstream CMOS technology in both processing speed and circuit density, as well as the relentless push to reduce total solution costs through integration of RF, analog and digital circuitry. Since the digital baseband part of a wireless communication channel has been traditionally implemented in the most advanced CMOS technology available at a given time for mass production, the need for single-chip CMOS integration has forced permanent changes to the way RF circuits are fundamentally designed. In this low-voltage nanometer-scale CMOS environment, the high-performance RF circuits must exploit the time-domain design paradigm and heavily rely on digital assistance. This paper revisits the digitization journey of RF circuits.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125444848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043627
L. Abdallah, H. Stratigopoulos, S. Mir
Testing the analog functions of a system-on-chip makes up the major portion of test cost - up to 50% according to anecdotal evidence - although analog circuits occupy less than 5% of the die area. Furthermore, cases have been reported where the test cost actually surpasses the overall manufacturing cost. This shows that analog test is in the coming years an area for industry focus, innovation and improvement.
{"title":"Implicit test of high-speed analog circuits using non-intrusive sensors","authors":"L. Abdallah, H. Stratigopoulos, S. Mir","doi":"10.1109/ECCTD.2011.6043627","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043627","url":null,"abstract":"Testing the analog functions of a system-on-chip makes up the major portion of test cost - up to 50% according to anecdotal evidence - although analog circuits occupy less than 5% of the die area. Furthermore, cases have been reported where the test cost actually surpasses the overall manufacturing cost. This shows that analog test is in the coming years an area for industry focus, innovation and improvement.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125456078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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