Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043338
S. Consul-Pacareu, J. Albó-Canals, Xavier Vilasís-Cardona, J. Riera-Babures
In this paper we present a complete study on the balance between high performance image processing and low power consumption without using expensive components. Our proposal consists in implementing a Discrete Time Cellular Neural Network (DT-CNN) on a low power Actel IGLOO nano Field Programmable Gate Array (FPGA). This is a definitive step further from previous work to obtain an intelligent camera device for robots. Applications in Robot Guidance have rapidly increased in the last years as robots break in different fields of everyday live, which most of this robotic devices need sensors for navigation. Our proposed low cost solution avoids highly complex architectures, expensive smart sensors and low performance navigation systems.
{"title":"High performance DT-CNN camera device design on ACTEL IGLOO low power FPGA","authors":"S. Consul-Pacareu, J. Albó-Canals, Xavier Vilasís-Cardona, J. Riera-Babures","doi":"10.1109/ECCTD.2011.6043338","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043338","url":null,"abstract":"In this paper we present a complete study on the balance between high performance image processing and low power consumption without using expensive components. Our proposal consists in implementing a Discrete Time Cellular Neural Network (DT-CNN) on a low power Actel IGLOO nano Field Programmable Gate Array (FPGA). This is a definitive step further from previous work to obtain an intelligent camera device for robots. Applications in Robot Guidance have rapidly increased in the last years as robots break in different fields of everyday live, which most of this robotic devices need sensors for navigation. Our proposed low cost solution avoids highly complex architectures, expensive smart sensors and low performance navigation systems.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043845
Emil Nilsson, C. Svensson
This paper presents analytical expressions for the sensitivity of a low power envelope detector driven by a weak RF signal in the presence of a blocking signal. The envelope detector has been proposed for low power Wake-Up radios in applications such as RFID and wireless sensor systems. The theoretical results are verified with simulations of a modern short channel MOS transistor in a commonly used circuit topology. A discussion around a tutorial example of a radio frontend, consisting of an LNA and a detector, is presented. It is shown that the sensitivity of a low power envelope detector can reach −62 dBm with a low power LNA and in presence of a CW blocker.
{"title":"Envelope detector sensitivity and blocking characteristics","authors":"Emil Nilsson, C. Svensson","doi":"10.1109/ECCTD.2011.6043845","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043845","url":null,"abstract":"This paper presents analytical expressions for the sensitivity of a low power envelope detector driven by a weak RF signal in the presence of a blocking signal. The envelope detector has been proposed for low power Wake-Up radios in applications such as RFID and wireless sensor systems. The theoretical results are verified with simulations of a modern short channel MOS transistor in a commonly used circuit topology. A discussion around a tutorial example of a radio frontend, consisting of an LNA and a detector, is presented. It is shown that the sensitivity of a low power envelope detector can reach −62 dBm with a low power LNA and in presence of a CW blocker.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129143637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043296
A. Lesellier, O. Jamin, J. Bercher, O. Venard
This paper presents a two-channel Hybrid Filter Bank (HFB) Analog-to-Digital Converter (ADC) that targets broadband digitization, for Cognitive Radio (CR) applications. The proposed architecture partitioning uses low-cost third order Butterworth analog filters and fourth order digital IIR filters. The optimization algorithm combines direct simplex search, minimax methods and a perturbation strategy to avoid local minima. A sensitivity study of the analog filters quantifies the impact of poles and zeros spread on system performance. Finally, the experimental results obtained from our concrete realization are reported. The measurements show the aliasing rejection provided by HFB structure and confirms the parallel architecture sensitivity to analog mismatches.
{"title":"Design, optimization and realization of an HFB-based ADC","authors":"A. Lesellier, O. Jamin, J. Bercher, O. Venard","doi":"10.1109/ECCTD.2011.6043296","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043296","url":null,"abstract":"This paper presents a two-channel Hybrid Filter Bank (HFB) Analog-to-Digital Converter (ADC) that targets broadband digitization, for Cognitive Radio (CR) applications. The proposed architecture partitioning uses low-cost third order Butterworth analog filters and fourth order digital IIR filters. The optimization algorithm combines direct simplex search, minimax methods and a perturbation strategy to avoid local minima. A sensitivity study of the analog filters quantifies the impact of poles and zeros spread on system performance. Finally, the experimental results obtained from our concrete realization are reported. The measurements show the aliasing rejection provided by HFB structure and confirms the parallel architecture sensitivity to analog mismatches.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043817
L. Chruszczyk, D. Grzechca
This article presents maximisation of components tolerance together with finding optimal frequency of a periodic excitation in fault diagnosis of analogue electronic circuits. Addi-tionally classical two-stage “detection → location” diagnosis se-quence is merged into single step in order to reduce test time. Presented optimisation problems are solved by means of a ge-netic algorithm.
{"title":"Tolerance maximisation in fault diagnosis of analogue electronic circuits","authors":"L. Chruszczyk, D. Grzechca","doi":"10.1109/ECCTD.2011.6043817","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043817","url":null,"abstract":"This article presents maximisation of components tolerance together with finding optimal frequency of a periodic excitation in fault diagnosis of analogue electronic circuits. Addi-tionally classical two-stage “detection → location” diagnosis se-quence is merged into single step in order to reduce test time. Presented optimisation problems are solved by means of a ge-netic algorithm.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043643
M. Faust, Chip-Hong Chang
The optimization of fixed coefficient FIR filter implementation has been focused mainly on the multiplier block where full precision fixed point arithmetic is normally used. Recently, an optimization method was proposed for the structural adders in FIR filters. This paper further proposes a method for gradually reducing the number of fractional bits within the structural adder block such that the output has the same number of fractional bits as the input signal. The resulting output signal is very close to the rounded signal obtained from full-precision calculation. This is achieved by applying truncation and round-half-up operations on the inputs to the structural adders. The proposed method reduces the area of FIR filter implementation and the magnitude of the error is not larger than one LSB. Example filters were synthesized and the simulation results show an error mean of less than 0.25% of the LSB and a variance of less than 15% of the LSB. Overall, the areas of the example filters have been reduced by up to 12.42%.
{"title":"Low error bit width reduction for structural adders of FIR filters","authors":"M. Faust, Chip-Hong Chang","doi":"10.1109/ECCTD.2011.6043643","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043643","url":null,"abstract":"The optimization of fixed coefficient FIR filter implementation has been focused mainly on the multiplier block where full precision fixed point arithmetic is normally used. Recently, an optimization method was proposed for the structural adders in FIR filters. This paper further proposes a method for gradually reducing the number of fractional bits within the structural adder block such that the output has the same number of fractional bits as the input signal. The resulting output signal is very close to the rounded signal obtained from full-precision calculation. This is achieved by applying truncation and round-half-up operations on the inputs to the structural adders. The proposed method reduces the area of FIR filter implementation and the magnitude of the error is not larger than one LSB. Example filters were synthesized and the simulation results show an error mean of less than 0.25% of the LSB and a variance of less than 15% of the LSB. Overall, the areas of the example filters have been reduced by up to 12.42%.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129251031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043321
X. Vilasís-Cardona
Ring Imaging Cherenkov detectors (RICH) are a class of particle detectors used for particle identification whose principle involves a pattern recognition problem: identifying circles from a short number of their points. A real image hosts several circles which may eventually overlap. Actual techniques solving this problem are mainly non-local algorithms implemented on software requiring large computing time and resources. This point limits the use of RICH detectors in the trigger system of large experiments such as LHCb. An alternative solution, based on a cellular approach, is proposed. A list of possible templates from the standard library is established and considerations on the requirements for the hardware implementation in FPGAs are given. From the conceptual point of view, the cellular technique solution looks promising while the hardware implementation in FPGAs lays in the verge of the actual technical limitations if response times are to be in the order of the microsecond as required in the LHCb hardware trigger.
{"title":"Cellular techniques for Ring Imaging Cherenkov detector image processing","authors":"X. Vilasís-Cardona","doi":"10.1109/ECCTD.2011.6043321","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043321","url":null,"abstract":"Ring Imaging Cherenkov detectors (RICH) are a class of particle detectors used for particle identification whose principle involves a pattern recognition problem: identifying circles from a short number of their points. A real image hosts several circles which may eventually overlap. Actual techniques solving this problem are mainly non-local algorithms implemented on software requiring large computing time and resources. This point limits the use of RICH detectors in the trigger system of large experiments such as LHCb. An alternative solution, based on a cellular approach, is proposed. A list of possible templates from the standard library is established and considerations on the requirements for the hardware implementation in FPGAs are given. From the conceptual point of view, the cellular technique solution looks promising while the hardware implementation in FPGAs lays in the verge of the actual technical limitations if response times are to be in the order of the microsecond as required in the LHCb hardware trigger.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125516525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043314
Manuel Suárez-Cambre, V. Brea, D. Cabello, F. Pozas-Flores, R. Carmona-Galán, Á. Rodríguez-Vázquez
In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. Every new scale is the result of a smoothing operator on a former scale. In image processing, scale-space filtering is widely used in feature extractors as the Scale-Invariant Feature Transform (SIFT) algorithm. RC networks are posed as valid scale-space generators in focal-plane processing. Switched-capacitor networks are another alternative, as different topologies and switching rate offer a great flexibility. This work examines the parallel and the bilinear implementations as two different switched-capacitor network topologies for scale-space filtering. The paper assesses the validity of both topologies as scale-space generators in focal-plane processing through object detection with the SIFT algorithm.
{"title":"Switched-capacitor networks for scale-space generation","authors":"Manuel Suárez-Cambre, V. Brea, D. Cabello, F. Pozas-Flores, R. Carmona-Galán, Á. Rodríguez-Vázquez","doi":"10.1109/ECCTD.2011.6043314","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043314","url":null,"abstract":"In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. Every new scale is the result of a smoothing operator on a former scale. In image processing, scale-space filtering is widely used in feature extractors as the Scale-Invariant Feature Transform (SIFT) algorithm. RC networks are posed as valid scale-space generators in focal-plane processing. Switched-capacitor networks are another alternative, as different topologies and switching rate offer a great flexibility. This work examines the parallel and the bilinear implementations as two different switched-capacitor network topologies for scale-space filtering. The paper assesses the validity of both topologies as scale-space generators in focal-plane processing through object detection with the SIFT algorithm.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123139957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043316
M. Noack, C. Mayr, J. Partzsch, R. Schüffny
Neuromorphic realizations of the short-term dynamics at a synapse often use simplistic circuit models. In this paper, we present a more biologically realistic VLSI implementation of these mechanisms. Our circuit approach is analytically derived from a model of neurotransmitter release, so that it can be directly related to simulation results and biological measurements. We present a reduced implementation of this approach that is highly configurable, allowing for an individual adjustment of all model parameters. Furthermore, it achieves a high robustness against process variations and successfully reproduces biological paired-pulse depression experiments.
{"title":"Synapse dynamics in CMOS derived from a model of neurotransmitter release","authors":"M. Noack, C. Mayr, J. Partzsch, R. Schüffny","doi":"10.1109/ECCTD.2011.6043316","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043316","url":null,"abstract":"Neuromorphic realizations of the short-term dynamics at a synapse often use simplistic circuit models. In this paper, we present a more biologically realistic VLSI implementation of these mechanisms. Our circuit approach is analytically derived from a model of neurotransmitter release, so that it can be directly related to simulation results and biological measurements. We present a reduced implementation of this approach that is highly configurable, allowing for an individual adjustment of all model parameters. Furthermore, it achieves a high robustness against process variations and successfully reproduces biological paired-pulse depression experiments.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121468210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043842
Alban Gruget, Morgan Roger, V. Nguyen, C. Lelandais-Perrault, P. Bénabès, P. Loumeau
This article presents the optimization process for a new architecture of digital-enhanced radio frequency receiver. This receiver is based on combining charge sampling filters and hybrid filter banks techniques. We describe the structure optimization based on a compromise between performance and implementation constraints. We then show the performances evaluation in system-level and electrical level simulations.
{"title":"Optimization of bandpass charge sampling filters in hybrid filter banks converters for cognitive radio applications","authors":"Alban Gruget, Morgan Roger, V. Nguyen, C. Lelandais-Perrault, P. Bénabès, P. Loumeau","doi":"10.1109/ECCTD.2011.6043842","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043842","url":null,"abstract":"This article presents the optimization process for a new architecture of digital-enhanced radio frequency receiver. This receiver is based on combining charge sampling filters and hybrid filter banks techniques. We describe the structure optimization based on a compromise between performance and implementation constraints. We then show the performances evaluation in system-level and electrical level simulations.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043302
Shafqat Ali, S. Tanner, P. Farine
A novel topology for a high speed voltage level shifter (VLS) is presented. It features a built-in short circuit current reduction which increases the speed and reduces the power consumption. Unlike the conventional VLSs, the proposed VLS does not need complex digital timing signals. The simplicity of its operation results into robustness of operation, high speed and low power. The VLS was designed in CMOS 0.18um process. Simulation results, at the layout extraction level, are presented to validate the design concept. The speed and energy consumption of the VLS are compared with the state of the art VLSs. The proposed VLS proves to be better in both the speed and power aspects than the state of the art VLSs.
{"title":"A robust, low power, high speed voltage level shifter with built-in short circuit current reduction","authors":"Shafqat Ali, S. Tanner, P. Farine","doi":"10.1109/ECCTD.2011.6043302","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043302","url":null,"abstract":"A novel topology for a high speed voltage level shifter (VLS) is presented. It features a built-in short circuit current reduction which increases the speed and reduces the power consumption. Unlike the conventional VLSs, the proposed VLS does not need complex digital timing signals. The simplicity of its operation results into robustness of operation, high speed and low power. The VLS was designed in CMOS 0.18um process. Simulation results, at the layout extraction level, are presented to validate the design concept. The speed and energy consumption of the VLS are compared with the state of the art VLSs. The proposed VLS proves to be better in both the speed and power aspects than the state of the art VLSs.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122192476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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