Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043289
E. Calandra, M. Caruso, Daniele Lupo
The problem of the correct evaluation of Q-factor appearing in Adler's equation for injection-locking is addressed. Investigation has shown that recent results presented in the literature, while extending applicability of the original method, do not completely account for nonlinear effects occurring when two-port active devices are involved. To overcome such limitation, use can be made of a newly developed theory in the dynamical complex envelope domain, capable of providing first-approximation exact dynamical models of driven quasi-sinusoidal oscillators. Some preliminary results are presented here concerning a class of injection-locked oscillators with single-loop feedback type configuration. The proposed procedure permits evaluation of the nonlinear oscillator Q-factor, either analytically or numerically, depending on the complexity of the nonlinear active device model involved. The example worked out, a MOST-equipped driven Colpitts scheme, clearly illustrates the accuracy improvement achieved in the determination of the locking bandwidth stemming from the newly defined effective Q-factor, without the need to resort to the very time consuming full numerical transient envelope simulations otherwise required to this purpose.
{"title":"Influence of active device nonlinearities on the determination of Adler's injection-locking Q-factor","authors":"E. Calandra, M. Caruso, Daniele Lupo","doi":"10.1109/ECCTD.2011.6043289","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043289","url":null,"abstract":"The problem of the correct evaluation of Q-factor appearing in Adler's equation for injection-locking is addressed. Investigation has shown that recent results presented in the literature, while extending applicability of the original method, do not completely account for nonlinear effects occurring when two-port active devices are involved. To overcome such limitation, use can be made of a newly developed theory in the dynamical complex envelope domain, capable of providing first-approximation exact dynamical models of driven quasi-sinusoidal oscillators. Some preliminary results are presented here concerning a class of injection-locked oscillators with single-loop feedback type configuration. The proposed procedure permits evaluation of the nonlinear oscillator Q-factor, either analytically or numerically, depending on the complexity of the nonlinear active device model involved. The example worked out, a MOST-equipped driven Colpitts scheme, clearly illustrates the accuracy improvement achieved in the determination of the locking bandwidth stemming from the newly defined effective Q-factor, without the need to resort to the very time consuming full numerical transient envelope simulations otherwise required to this purpose.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129326456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043818
Tero Nieminen, K. Halonen
This paper compares one- and two stage operational transconductance amplifiers (OTAs) to be used in an 8-bit high speed (440-MS/s) deep submicron CMOS (130nm) low voltage (1.2V) pipelined Analogue to Digital Converter (ADC) based on an 1.5-bit double sampling Multiplying Digital to Analogue Converter (MDAC). The main emphasis is put on the OTA DC-gain, gain-bandwidth (GBW), differential linear output range VOPP and power consumption. Most basic OTAs are compared through the calculations and simulations. In the potential topologies (regulated single stage or two stage), single stage OTA has a better phase response and a lower power consumption, whereas two stage OTA achieves larger linear range.
{"title":"Single and two-stage OTAs for high-speed CMOS pipelined ADCs","authors":"Tero Nieminen, K. Halonen","doi":"10.1109/ECCTD.2011.6043818","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043818","url":null,"abstract":"This paper compares one- and two stage operational transconductance amplifiers (OTAs) to be used in an 8-bit high speed (440-MS/s) deep submicron CMOS (130nm) low voltage (1.2V) pipelined Analogue to Digital Converter (ADC) based on an 1.5-bit double sampling Multiplying Digital to Analogue Converter (MDAC). The main emphasis is put on the OTA DC-gain, gain-bandwidth (GBW), differential linear output range VOPP and power consumption. Most basic OTAs are compared through the calculations and simulations. In the potential topologies (regulated single stage or two stage), single stage OTA has a better phase response and a lower power consumption, whereas two stage OTA achieves larger linear range.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124744938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043602
L. Aksoy, E. Costa, P. Flores, J. Monteiro
This paper addresses the problem of optimizing gate-level area in a pipelined Multiple Constant Multiplications (MCM) operation and introduces a high-level synthesis algorithm, called HCUB-DC+ILP. In the HCUB-DC+ILP algorithm, initially, a solution with the fewest number of operations under a minimum delay constraint is found by the Hcub-DC algorithm. Then, the area around this local minimum point is explored exactly using a 0–1 Integer Linear Programming (ILP) technique that considers the gate-level implementation of the pipelined MCM operation. The experimental results at both high-level and gate-level clearly show the efficiency of HCUB-DC+ILP over previously proposed prominent MCM algorithms.
{"title":"Optimization of gate-level area in high throughput Multiple Constant Multiplications","authors":"L. Aksoy, E. Costa, P. Flores, J. Monteiro","doi":"10.1109/ECCTD.2011.6043602","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043602","url":null,"abstract":"This paper addresses the problem of optimizing gate-level area in a pipelined Multiple Constant Multiplications (MCM) operation and introduces a high-level synthesis algorithm, called HCUB-DC+ILP. In the HCUB-DC+ILP algorithm, initially, a solution with the fewest number of operations under a minimum delay constraint is found by the Hcub-DC algorithm. Then, the area around this local minimum point is explored exactly using a 0–1 Integer Linear Programming (ILP) technique that considers the gate-level implementation of the pipelined MCM operation. The experimental results at both high-level and gate-level clearly show the efficiency of HCUB-DC+ILP over previously proposed prominent MCM algorithms.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043612
M. Ionita, D. Cordeau, J. Paillot, M. Iordache
This paper considers the analysis and the design of an array of two NMOS differential oscillators coupled through a resistor. A new writing of the nonlinear equations proposed by R. York to describe the oscillators' locked states but limited for the specific case of a resistive coupling is presented. The new system permits the calculation of the free-running frequencies of the oscillators when a specific phase shift is desired. This has led to the modeling of the two coupled NMOS differential oscillators as two coupled differential Van der Pol oscillators, with a resistive coupling network. A good agreement between the circuit, the model and the theory was found, giving some design considerations for a network of two differential oscillators coupled through one resistor.
{"title":"Analysis and design of an array of two differential oscillators coupled through a resistive network","authors":"M. Ionita, D. Cordeau, J. Paillot, M. Iordache","doi":"10.1109/ECCTD.2011.6043612","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043612","url":null,"abstract":"This paper considers the analysis and the design of an array of two NMOS differential oscillators coupled through a resistor. A new writing of the nonlinear equations proposed by R. York to describe the oscillators' locked states but limited for the specific case of a resistive coupling is presented. The new system permits the calculation of the free-running frequencies of the oscillators when a specific phase shift is desired. This has led to the modeling of the two coupled NMOS differential oscillators as two coupled differential Van der Pol oscillators, with a resistive coupling network. A good agreement between the circuit, the model and the theory was found, giving some design considerations for a network of two differential oscillators coupled through one resistor.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114110293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043633
Carl Ingemarsson, O. Gustafsson
Matrix inversion is sensitive towards the number representation used. In this paper simulations of matrix inversion with numbers represented in the fixed-point and logarithmic number systems (LNS) are presented. A software framework has been implemented to allow extensive simulation of finite wordlength matrix inversion. Six different algorithms have been used and results on matrix condition number, wordlength, and to some extent matrix size are presented. The simulations among other things show that the wordlength requirements differ significantly between different algorithms in both fixed-point and LNS representations. The results can be used as a starting point for a matrix inversion hardware implementation.
{"title":"Finite wordlength properties of matrix inversion algorithms in fixed-point and logarithmic number systems","authors":"Carl Ingemarsson, O. Gustafsson","doi":"10.1109/ECCTD.2011.6043633","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043633","url":null,"abstract":"Matrix inversion is sensitive towards the number representation used. In this paper simulations of matrix inversion with numbers represented in the fixed-point and logarithmic number systems (LNS) are presented. A software framework has been implemented to allow extensive simulation of finite wordlength matrix inversion. Six different algorithms have been used and results on matrix condition number, wordlength, and to some extent matrix size are presented. The simulations among other things show that the wordlength requirements differ significantly between different algorithms in both fixed-point and LNS representations. The results can be used as a starting point for a matrix inversion hardware implementation.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114563810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043653
M. Renfors, F. Harris
FFT-IFFT configuration, or more generally a forward-inverse orthogonal transform pair, offers a way to implement a digital filter whose frequency-domain characteristics can be straightforwardly tuned by adjusting the complex gains of the frequency bins. Using filter banks (FBs) for the transform pair, sharp transition bands can be obtained for low-pass/bandpass/highpass type filter designs. However, FBs suffer from relatively high implementation complexity. Fast convolution based multirate FBs constitute and alternative approach which is able to reach high spectral containment together with high flexibility and conceptual simplicity. In this paper we consider a fast convolution based highly tunable analysis FB configuration and show that nearly perfect-reconstruction FB systems can be implemented using this approach. Further, the channel filters of the analysis FB are easily configurable for different bandwidths, center frequencies and output sampling rates.
{"title":"Highly adjustable multirate digital filters based on fast convolution","authors":"M. Renfors, F. Harris","doi":"10.1109/ECCTD.2011.6043653","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043653","url":null,"abstract":"FFT-IFFT configuration, or more generally a forward-inverse orthogonal transform pair, offers a way to implement a digital filter whose frequency-domain characteristics can be straightforwardly tuned by adjusting the complex gains of the frequency bins. Using filter banks (FBs) for the transform pair, sharp transition bands can be obtained for low-pass/bandpass/highpass type filter designs. However, FBs suffer from relatively high implementation complexity. Fast convolution based multirate FBs constitute and alternative approach which is able to reach high spectral containment together with high flexibility and conceptual simplicity. In this paper we consider a fast convolution based highly tunable analysis FB configuration and show that nearly perfect-reconstruction FB systems can be implemented using this approach. Further, the channel filters of the analysis FB are easily configurable for different bandwidths, center frequencies and output sampling rates.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121504934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043294
C. Sánchez-Azqueta, S. Celma
This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang phase detectors, a scheme of phase delay sensing is proposed that eliminates the need to sample the data stream close to data transitions in the locked state. Behavioural simulations are provided comparing the performance of the proposed phase detector with that of a conventional bang-bang phase detector.
{"title":"A phase detection scheme for clock and data recovery applications","authors":"C. Sánchez-Azqueta, S. Celma","doi":"10.1109/ECCTD.2011.6043294","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043294","url":null,"abstract":"This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang phase detectors, a scheme of phase delay sensing is proposed that eliminates the need to sample the data stream close to data transitions in the locked state. Behavioural simulations are provided comparing the performance of the proposed phase detector with that of a conventional bang-bang phase detector.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114752172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043297
B. Nikolić
Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, architecture, and implementation techniques that trade off performance for power savings. Energy-efficient design is often achieved for designs that are sensitive to technology and design parameters. On the other hand, increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Sources of variability in scaled technologies are reviewed, along with models and methods for their capture in design. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Methods of desensitizing the digital logic and SRAM to variability at low supply voltages are demonstrated.
{"title":"Managing variability for ultimate energy efficiency","authors":"B. Nikolić","doi":"10.1109/ECCTD.2011.6043297","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043297","url":null,"abstract":"Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, architecture, and implementation techniques that trade off performance for power savings. Energy-efficient design is often achieved for designs that are sensitive to technology and design parameters. On the other hand, increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Sources of variability in scaled technologies are reviewed, along with models and methods for their capture in design. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Methods of desensitizing the digital logic and SRAM to variability at low supply voltages are demonstrated.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124497787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043365
Hiroki Sato, Zhishan Xu, R. Nicodimus, S. Takagi
This paper proposes an approach to realize a leapfrog filter with transmission zeros by using OTA-C integrators and resistor-based addition circuit instead of OTAs. This method has advantages of reduced number of active elements and spread of element values. A tenth-order bandpass filter is presented as a design example.
{"title":"Low-power leapfrog bandpass filter with transmission zeros using integrators and resistor-based addition circuits","authors":"Hiroki Sato, Zhishan Xu, R. Nicodimus, S. Takagi","doi":"10.1109/ECCTD.2011.6043365","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043365","url":null,"abstract":"This paper proposes an approach to realize a leapfrog filter with transmission zeros by using OTA-C integrators and resistor-based addition circuit instead of OTAs. This method has advantages of reduced number of active elements and spread of element values. A tenth-order bandpass filter is presented as a design example.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126253273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043609
Bo Zhang, Weiwei Pan, Yongjun Zheng, Zheng Shi, Xiaolang Yan
During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable test chip development procedure. Based on components for automation, this procedure is fully integrated and able to reduce layout time to 10% and eliminate much of the potential for human error. A 32×32 array on a 45nm technology has been designed and manufactured with this procedure; the silicon test data further prove the reliability and effectiveness of this procedure.
{"title":"A fully automated large-scale addressable test chip design with high reliability","authors":"Bo Zhang, Weiwei Pan, Yongjun Zheng, Zheng Shi, Xiaolang Yan","doi":"10.1109/ECCTD.2011.6043609","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043609","url":null,"abstract":"During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper, we present a novel large-scale addressable test chip development procedure. Based on components for automation, this procedure is fully integrated and able to reduce layout time to 10% and eliminate much of the potential for human error. A 32×32 array on a 45nm technology has been designed and manufactured with this procedure; the silicon test data further prove the reliability and effectiveness of this procedure.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132210977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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