Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523633
V. Hu, M. Fan, P. Su, C. Chuang
A comparative analysis of Germanium-on-Insulator FinFET (GeOI FinFET) and Germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit level with respect to Si counterparts is presented. GeOI FinFET shows larger leakage current than Ge bulk FinFET due to the parasitic bipolar effect triggered by the band-to-band tunneling (BTBT) leakage. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOI and Ge bulk FinFET circuits and SRAMs. An optimum asymmetric underlap design in SRAM using asymmetric underlap pull-up and access transistors (PUAX-asym) is proposed. GeOI and Ge bulk FinFETs with asymmetric underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.
{"title":"Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates","authors":"V. Hu, M. Fan, P. Su, C. Chuang","doi":"10.1109/ISQED.2013.6523633","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523633","url":null,"abstract":"A comparative analysis of Germanium-on-Insulator FinFET (GeOI FinFET) and Germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit level with respect to Si counterparts is presented. GeOI FinFET shows larger leakage current than Ge bulk FinFET due to the parasitic bipolar effect triggered by the band-to-band tunneling (BTBT) leakage. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOI and Ge bulk FinFET circuits and SRAMs. An optimum asymmetric underlap design in SRAM using asymmetric underlap pull-up and access transistors (PUAX-asym) is proposed. GeOI and Ge bulk FinFETs with asymmetric underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523681
B. Kaur, S. Miryala, S. Manhas, B. Anand
Accurate estimation of delay is a major challenge in current nanometer regime using Non Linear Delay Model (NLDM) due to issues such as parametric variation, nonlinear capacitance value etc. It demands a large number of simulations to be performed for getting the accurate delay values. To partly solve this issue, people have started using Effective Current Source Model (ECSM), which stores certain predefined Threshold Crossing Point (TCP) of the output voltage waveform with respect to different input transition time (TR) values and load capacitance (Cl). In this work, we propose an analytical timing model relating 10% - 90% TCPs with Cl and TR values. We also derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (TR, Cl) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum relative error of 2.5%. We verified the proposed model with technology scaling. We use this model and the relationships to reduce the number of simulations in ECSM library characterization.
{"title":"An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies","authors":"B. Kaur, S. Miryala, S. Manhas, B. Anand","doi":"10.1109/ISQED.2013.6523681","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523681","url":null,"abstract":"Accurate estimation of delay is a major challenge in current nanometer regime using Non Linear Delay Model (NLDM) due to issues such as parametric variation, nonlinear capacitance value etc. It demands a large number of simulations to be performed for getting the accurate delay values. To partly solve this issue, people have started using Effective Current Source Model (ECSM), which stores certain predefined Threshold Crossing Point (TCP) of the output voltage waveform with respect to different input transition time (TR) values and load capacitance (Cl). In this work, we propose an analytical timing model relating 10% - 90% TCPs with Cl and TR values. We also derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (TR, Cl) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum relative error of 2.5%. We verified the proposed model with technology scaling. We use this model and the relationships to reduce the number of simulations in ECSM library characterization.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129094789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523600
V. Viswanath, R. Muralidhar, Harinarayanan Seshadri, J. Abraham
We present a novel and highly automated technique for dynamic system level power management of System-on-a-Chip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs. There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a self-checking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.
{"title":"On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs","authors":"V. Viswanath, R. Muralidhar, Harinarayanan Seshadri, J. Abraham","doi":"10.1109/ISQED.2013.6523600","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523600","url":null,"abstract":"We present a novel and highly automated technique for dynamic system level power management of System-on-a-Chip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs. There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a self-checking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129228815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523630
Jifeng Chen, M. Tehranipoor
Negative bias temperature instability (NBTI) has emerged as a major concern not only to the functional circuits, but also to the clock tree. Further aggravated by process variations, aging-induced reliability issue becomes more challenging when technology further scales. Development of effective solutions for reducing clock skew and compensating aging effect under process variations remains as a challenge. Taking the impact from NBTI and process variations into account, we propose a novel flow for reducing clock skew by selectively replacing standard-Vth clock buffers with their high-Vth counterparts. An extended “divide and conquer” algorithm is developed to identify the critical clock buffers for replacement. The area overhead of our proposed flow is negligible, and the power consumption is reduced as well. Simulation results show that the proposed flow can effectively reduce the clock skew by at least 20% by replacing only 1.08% clock buffers on average for 10 years of degradation, even under an extremely constrained condition. The efficiency of our flow will be higher when the clock tree structure has a higher depth, rendering it more favorable for large-scale industry designs.
{"title":"A novel flow for reducing clock skew considering NBTI effect and process variations","authors":"Jifeng Chen, M. Tehranipoor","doi":"10.1109/ISQED.2013.6523630","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523630","url":null,"abstract":"Negative bias temperature instability (NBTI) has emerged as a major concern not only to the functional circuits, but also to the clock tree. Further aggravated by process variations, aging-induced reliability issue becomes more challenging when technology further scales. Development of effective solutions for reducing clock skew and compensating aging effect under process variations remains as a challenge. Taking the impact from NBTI and process variations into account, we propose a novel flow for reducing clock skew by selectively replacing standard-Vth clock buffers with their high-Vth counterparts. An extended “divide and conquer” algorithm is developed to identify the critical clock buffers for replacement. The area overhead of our proposed flow is negligible, and the power consumption is reduced as well. Simulation results show that the proposed flow can effectively reduce the clock skew by at least 20% by replacing only 1.08% clock buffers on average for 10 years of degradation, even under an extremely constrained condition. The efficiency of our flow will be higher when the clock tree structure has a higher depth, rendering it more favorable for large-scale industry designs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"23 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523636
C. Hsu, K. Tsai, Jing-Fu Jheng, S. Ruan, Chung-An Shen
Network-on-Chip has been proposed for high performance on-chip communication. The major component of a Network-on-Chip architecture is the router, which affects the data transmission latency, chip area and power consumption. Inside the router, buffers occupy a significant a mount of power and a large partition of chip area. Therefore bufferless NoC, which discards the buffers in the routers, has been proposed for solving the power and area problem. In this paper, a low power deflection routing method is proposed for the bufferless on-chip network dealing with the routing problem and achieving the low power goal. The proposed method uses routing matrix for constructing the possible routing path, and then selects the best route for each data packet. Only few calculations are used in this method therefore lowering power consumption the low power goal. The experimental result shows that the proposed approach can greatly reduce power consumption and chip are compared with previous work.
{"title":"A low power detection routing method for bufferless NoC","authors":"C. Hsu, K. Tsai, Jing-Fu Jheng, S. Ruan, Chung-An Shen","doi":"10.1109/ISQED.2013.6523636","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523636","url":null,"abstract":"Network-on-Chip has been proposed for high performance on-chip communication. The major component of a Network-on-Chip architecture is the router, which affects the data transmission latency, chip area and power consumption. Inside the router, buffers occupy a significant a mount of power and a large partition of chip area. Therefore bufferless NoC, which discards the buffers in the routers, has been proposed for solving the power and area problem. In this paper, a low power deflection routing method is proposed for the bufferless on-chip network dealing with the routing problem and achieving the low power goal. The proposed method uses routing matrix for constructing the possible routing path, and then selects the best route for each data packet. Only few calculations are used in this method therefore lowering power consumption the low power goal. The experimental result shows that the proposed approach can greatly reduce power consumption and chip are compared with previous work.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130675751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523605
Nan Wang, Song Chen, T. Yoshimura
In this paper, we address the problem of scheduling operations into control steps with dual threshold voltage (dual-Vth) technique under timing and resource constraints. We present a min-cut based algorithm for leakage power optimization. The proposed algorithm first initializes all the operations to high-Vth, then iteratively shorten the critical path delay by reassigning the set of operations covering all the critical paths to low-Vth until the timing constraints are met. A modified force-directed scheduling is implemented to schedule operations and to adjust threshold voltage assignments with consideration of resource constraints. During this procedure, mobility overlap graph (MOG) is constructed based on the mobilities of high-Vth operations. To guarantee the resource constraints are satisfied, operations' threshold voltages are adjusted by computing the min-cut of MOG. Experimental results show that our method performs better both in running time and leakage power reduction compared with MWIS_heuristic [3].
{"title":"Min-cut based leakage power aware scheduling in high-level synthesis","authors":"Nan Wang, Song Chen, T. Yoshimura","doi":"10.1109/ISQED.2013.6523605","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523605","url":null,"abstract":"In this paper, we address the problem of scheduling operations into control steps with dual threshold voltage (dual-Vth) technique under timing and resource constraints. We present a min-cut based algorithm for leakage power optimization. The proposed algorithm first initializes all the operations to high-Vth, then iteratively shorten the critical path delay by reassigning the set of operations covering all the critical paths to low-Vth until the timing constraints are met. A modified force-directed scheduling is implemented to schedule operations and to adjust threshold voltage assignments with consideration of resource constraints. During this procedure, mobility overlap graph (MOG) is constructed based on the mobilities of high-Vth operations. To guarantee the resource constraints are satisfied, operations' threshold voltages are adjusted by computing the min-cut of MOG. Experimental results show that our method performs better both in running time and leakage power reduction compared with MWIS_heuristic [3].","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125499986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523618
Soumyajit Chatterjee, H. Rahaman, T. Samanta
Design automation for digital microfluidic biochip comprises of many combinatorial optimization problems, which are NP-complete in nature. Efficient optimization algorithms to solve them is in dearth till date. In this paper, we propose a multi-objective optimization algorithm that simultaneously minimizes several resources during bioassay operations in a digital microfluidic biochip. We design the progressive droplet routing as a constrained multi-objective optimization problem considering three objective functions to be optimized, named (i) electrode usages, (ii) routing completion time, or latest arrival time, and (iii) control pin allocation. A composite objective function is constructed by a weighted sum of the first two objective functions. This composite function is minimized pertaining to an upper bound on the third objective function, control pin allocation. A fractional constant weight factor (λ) is chosen to confer upon the necessary weightage on the two factors involved in the composite objective function for accurate optimization procedure. We perform experimentations with several existing benchmarks, and experimental results are quite encouraging.
{"title":"Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip","authors":"Soumyajit Chatterjee, H. Rahaman, T. Samanta","doi":"10.1109/ISQED.2013.6523618","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523618","url":null,"abstract":"Design automation for digital microfluidic biochip comprises of many combinatorial optimization problems, which are NP-complete in nature. Efficient optimization algorithms to solve them is in dearth till date. In this paper, we propose a multi-objective optimization algorithm that simultaneously minimizes several resources during bioassay operations in a digital microfluidic biochip. We design the progressive droplet routing as a constrained multi-objective optimization problem considering three objective functions to be optimized, named (i) electrode usages, (ii) routing completion time, or latest arrival time, and (iii) control pin allocation. A composite objective function is constructed by a weighted sum of the first two objective functions. This composite function is minimized pertaining to an upper bound on the third objective function, control pin allocation. A fractional constant weight factor (λ) is chosen to confer upon the necessary weightage on the two factors involved in the composite objective function for accurate optimization procedure. We perform experimentations with several existing benchmarks, and experimental results are quite encouraging.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124475204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523599
Shan Cao, Zhaolin Li, Z. Chen, Guoyue Jiang, Shaojun Wei
Stream architecture is emerging as an important architecture for performance improvement of media applications. With technology scaled to nanometer-scale, leakage energy consumption is accounting for a greater proportion of the total energy consumption than ever, especially for stream architectures with a large number of functional units. In this paper, a compiler-assisted instruction-level scheduling algorithm is proposed to optimize leakage energy by idle interval distribution for stream architectures. The algorithm explores the scheduling spaces of idle intervals spatially and temporally and gathers the idle intervals for power-gating. The leakage energy is optimized without performance loss by increasing efficient power-gated cycles and decreasing switch times. We implement the proposed scheduling algorithm on Imagine processor and employ a set of benchmarks to evaluate the effectiveness of the algorithm. Experimental results show that the leakage energy consumption is reduced by 52% averagely compared with the list scheduling algorithm.
{"title":"Compiler-assisted leakage energy optimization of media applications on stream architectures","authors":"Shan Cao, Zhaolin Li, Z. Chen, Guoyue Jiang, Shaojun Wei","doi":"10.1109/ISQED.2013.6523599","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523599","url":null,"abstract":"Stream architecture is emerging as an important architecture for performance improvement of media applications. With technology scaled to nanometer-scale, leakage energy consumption is accounting for a greater proportion of the total energy consumption than ever, especially for stream architectures with a large number of functional units. In this paper, a compiler-assisted instruction-level scheduling algorithm is proposed to optimize leakage energy by idle interval distribution for stream architectures. The algorithm explores the scheduling spaces of idle intervals spatially and temporally and gathers the idle intervals for power-gating. The leakage energy is optimized without performance loss by increasing efficient power-gated cycles and decreasing switch times. We implement the proposed scheduling algorithm on Imagine processor and employ a set of benchmarks to evaluate the effectiveness of the algorithm. Experimental results show that the leakage energy consumption is reduced by 52% averagely compared with the list scheduling algorithm.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523660
Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma
The growing design-productivity gap has made designers shift toward using high-level synthesis (HLS) techniques to generate register transfer level design from high-level languages like C/C++. Unfortunately, this translation process is very complex and is prone to introduce bug into the generated design, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an efficient approach to validate the result of HLS against the initial high-level program using translation validation techniques. We redefined the bisimulation relation and proposed a novel algorithm based on it. When compared with the existing method, the proposed method can dramatically reduce the number of automated theorem prover (ATP) querying, which will in turn improve the time cost in equivalence validation. Our method is suitable for structure-preserving transformations such as carried out by Spark synthesizer. We have implemented our validating technique and compared it with a state-of-the-art translation validation method of HLS. The promising results show the effectiveness and efficiency of our method.
{"title":"Efficient translation validation of high-level synthesis","authors":"Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma","doi":"10.1109/ISQED.2013.6523660","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523660","url":null,"abstract":"The growing design-productivity gap has made designers shift toward using high-level synthesis (HLS) techniques to generate register transfer level design from high-level languages like C/C++. Unfortunately, this translation process is very complex and is prone to introduce bug into the generated design, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an efficient approach to validate the result of HLS against the initial high-level program using translation validation techniques. We redefined the bisimulation relation and proposed a novel algorithm based on it. When compared with the existing method, the proposed method can dramatically reduce the number of automated theorem prover (ATP) querying, which will in turn improve the time cost in equivalence validation. Our method is suitable for structure-preserving transformations such as carried out by Spark synthesizer. We have implemented our validating technique and compared it with a state-of-the-art translation validation method of HLS. The promising results show the effectiveness and efficiency of our method.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126368962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523670
Gong Chen, Yu Zhang, Bo Yang, Qing Dong, S. Nakatake
In low power analog circuit designs, the current variation caused by the STI stress must be taken into account. In this paper, we address an energy trade-off related to the STI stress in the design of a comparator composed of the preamplifier and the conventional latch. The power consumption of the pre-amplifier can be formulated as a function of the diffusion length of MOSFETs when considering the STI stress. The longer diffusion length tends to make the power lower. On the other hand, the power to drive the latch is associated with the parasitic capacitance at the output of the pre-amplifier, so shorter diffusion is preferable. To cope with the trade-off, we provide the energy model of the comparator based on the geometric programming. In the post-layout HSPICE simulation with the STI BSIM model, we reveal that the impact of the STI stress on the energy becomes significant especially in low power designs.
在低功耗模拟电路设计中，必须考虑到 STI 应力引起的电流变化。在本文中，我们讨论了由前置放大器和传统锁存器组成的比较器设计中与 STI 应力有关的能量权衡问题。考虑到 STI 应力，前置放大器的功耗可表述为 MOSFET 扩散长度的函数。扩散长度越长，功耗越低。另一方面，驱动锁存器的功率与前置放大器输出端的寄生电容有关，因此扩散长度越短越好。为了权衡利弊，我们提供了基于几何编程的比较器能量模型。在利用 STI BSIM 模型进行的布局后 HSPICE 仿真中，我们发现 STI 应力对能量的影响非常显著，尤其是在低功耗设计中。
{"title":"A comparator energy model considering shallow trench isolation stress by geometric programming","authors":"Gong Chen, Yu Zhang, Bo Yang, Qing Dong, S. Nakatake","doi":"10.1109/ISQED.2013.6523670","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523670","url":null,"abstract":"In low power analog circuit designs, the current variation caused by the STI stress must be taken into account. In this paper, we address an energy trade-off related to the STI stress in the design of a comparator composed of the preamplifier and the conventional latch. The power consumption of the pre-amplifier can be formulated as a function of the diffusion length of MOSFETs when considering the STI stress. The longer diffusion length tends to make the power lower. On the other hand, the power to drive the latch is associated with the parasitic capacitance at the output of the pre-amplifier, so shorter diffusion is preferable. To cope with the trade-off, we provide the energy model of the comparator based on the geometric programming. In the post-layout HSPICE simulation with the STI BSIM model, we reveal that the impact of the STI stress on the energy becomes significant especially in low power designs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125876217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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