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VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands VERVE:一个具有电压岛的基于noc的mpsoc的变化感知节能合成框架
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523673
N. Kapadia, S. Pasricha
With feature sizes far below the wavelength of light, variations in fabrication processes are becoming more common and can lead to unpredictable behavior in modern multiprocessor system-on-chip (MPSoC) designs. The design costs associated with margining required to overcome this unpredictability can be prohibitively high. System-level design approaches that are aware of these variations can be crucial for designing energy-efficient systems. We note that by performing voltage island placement appropriately, the two major unintended consequences of variations on the circuit characteristics (altered delay and power dissipation) can be traded-off, in order to minimize overall system energy. To this end, we propose a novel design-time system-level synthesis framework that is cognizant of process variations while mapping cores operating at specific supply voltages to a die and allocating communication routes on a 2D-mesh network-on-chip (NoC) topology for optimal energy-efficiency. Our experiments with real-world and synthetic application benchmarks show that our framework achieves 3.4% savings in computation energy and 19% savings in communication energy compared to the best known prior work on NoC-based MPSoC synthesis that considers process variations.
随着特征尺寸远低于光的波长,制造工艺的变化变得越来越普遍,并可能导致现代多处理器片上系统(MPSoC)设计中不可预测的行为。与克服这种不可预测性所需的保证金相关的设计成本可能高得令人望而却步。了解这些变化的系统级设计方法对于设计节能系统至关重要。我们注意到,通过适当地执行电压岛放置,可以权衡电路特性变化的两个主要意想不到的后果(改变的延迟和功耗),以最小化整个系统能量。为此,我们提出了一种新的设计时系统级综合框架,该框架能够识别工艺变化,同时将在特定电源电压下工作的内核映射到芯片上,并在2d网格片上网络(NoC)拓扑上分配通信路由,以实现最佳能效。我们对现实世界和合成应用基准的实验表明,与考虑工艺变化的基于noc的MPSoC合成的最著名的先前工作相比,我们的框架在计算能量方面节省了3.4%,在通信能量方面节省了19%。
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引用次数: 11
RF passive device modeling and characterization in 65nm CMOS technology 65纳米CMOS技术下射频无源器件的建模与表征
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523680
E. Lourandakis, S. Stefanou, K. Nikellis, S. Bantas
Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.
本文讨论了基于65nm CMOS工艺制备的M1-M9铜金属层和1铝金属层AP的测试结构的快速无源器件建模,并研究了重叠微带和屏蔽微带结构的电容提取。在微带之间或微带与硅衬底之间,单个电容根据面积和条纹分量进行建模。制备的测试结构与硅数据具有良好的相关性。本文还对电感和交叉电容等复杂无源器件的有效性进行了研究。研究了两种无源器件的器件指标,并将其与测量的硅数据进行了比较。在所有情况下都取得了良好的一致性,证明了所提出的建模方法的准确性。
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引用次数: 6
Wire delay variability in nanoscale technology and its impact on physical design 纳米技术中的导线延迟变异性及其对物理设计的影响
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523671
S. Nassif, Gi-Joon Nam, Shayak Banerjee
Current technology scaling trends are changing the character of wire delay variability. The distribution of wire delay is asymmetric, with a long positive tail which can be as much as 2X longer than the negative tail. This is due to the geometry of these wires, where the aspect ratio is biased towards tall thin wire cross-sections, as well as manufacturing induced variations particularly from lithography. These trends are important for timing closure, whether done via corner-based or statistical analysis. In this paper, we explore these trends, demonstrate their impact in a modern 32nm CMOS design, and suggest ways in which this trend can be managed and reduced. Particularly, through physical synthesis optimization on industrial designs, we show how these trends/observations can be utilized to produce more reliable designs. As the interconnect scaling lags behind the device scaling, the importance of wire variability will grow further in the future technology nodes.
当前的技术缩放趋势正在改变线延迟可变性的特性。线延迟的分布是不对称的,有一条较长的正尾,比负尾长2X。这是由于这些导线的几何形状,其中纵横比偏向于高细导线横截面,以及制造引起的变化,特别是光刻。无论是通过街角分析还是统计分析,这些趋势对于计时关闭都很重要。在本文中,我们探讨了这些趋势,展示了它们在现代32nm CMOS设计中的影响,并提出了管理和减少这种趋势的方法。特别是,通过工业设计的物理合成优化,我们展示了如何利用这些趋势/观察结果来生产更可靠的设计。由于互连扩展滞后于器件扩展,因此在未来的技术节点中,导线可变性的重要性将进一步增长。
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引用次数: 7
Performance entitlement by exploiting transistor's BTI recovery 利用晶体管的BTI恢复的性能权利
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523632
S. Arasu, M. Nourani, V. Reddy, J. Carulli
The inherent problem in signal probability (α) prediction has limited the scope of exploiting the transistor's BTI recovery at circuit level. In this paper, we present a design-for-reliability (DFR) methodology for digital designs, BTI_Refresh, that instead of relying on predicting α, sets it to a known value (~0.5) such that the BTI stress effects are alleviated and a predicted recovery effect could be guaranteed at circuit level. The technique can be applied equally to both NBTI and PBTI. Experimental results using Cadence Relxpert on critical paths extracted from industry designs show that with a negligible power, area overhead, a significant improvement (50%) in the total degradation of critical path performance with respect to end-of-life models is achievable.
信号概率(α)预测的固有问题限制了在电路水平上利用晶体管的BTI恢复的范围。在本文中,我们提出了一种用于数字设计的可靠性设计(DFR)方法,BTI_Refresh,它不是依赖于预测α,而是将其设置为已知值(~0.5),从而减轻了BTI应力效应,并且可以保证在电路级别上预测恢复效果。该技术同样适用于NBTI和PBTI。使用Cadence Relxpert从工业设计中提取的关键路径的实验结果表明,与寿命终止模型相比,在可忽略的功率和面积开销下,关键路径性能的总退化可以实现显著改善(50%)。
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引用次数: 7
Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loop 地统计学启发了纳米级CMOS锁相环的快速布局优化
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523664
Oghenekarho Okobiah, S. Mohanty, E. Kougianos
In this paper, we present a geostatistical method for design and optimization of analog and mixed signal circuits design illustrated with the design of phase locked loop (PLL) systems used in Wide Area Network (WAN) and Private Mobile Radio (PMR) applications. The proposed method incorporates the use of a geostatistic based metamodeling technique (Kriging) and optimization algorithm (gravitational search algorithm) and is compared to similar approaches. The results show that the geostatistical methods provide more accurate metamodels and more efficient optimization design techniques. To the best of the authors' knowledge, this is the first geostatistical method for metamodeling and optimization of PLL designs. The proposed optimization could achieve 79% reduction in PLL power with 4% reduction in locking time without any area penalty.
在本文中,我们提出了一种用于设计和优化模拟和混合信号电路设计的地质统计学方法,并举例说明了用于广域网(WAN)和专用移动无线电(PMR)应用的锁相环(PLL)系统的设计。该方法结合了基于地质统计学的元建模技术(Kriging)和优化算法(引力搜索算法),并与类似方法进行了比较。结果表明,地统计学方法提供了更精确的元模型和更有效的优化设计技术。据作者所知,这是第一个用于锁相环设计元建模和优化的地质统计学方法。所提出的优化可以实现锁相环功率降低79%,锁定时间减少4%,且没有任何面积损失。
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引用次数: 2
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs 基于tsv的三维集成电路温度场分析建模与数值模拟
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523585
Y. Shiyanovskii, C. Papachristou, Cheng-Wen Wu
Three dimensional (3D) integrated circuit (IC) technology is emerging as a potential alternative to address the physical limitations in miniaturization of the current 2D semiconductor devices. The 3D IC integration is based on the concept of through-silicon vias (TSV) and vertical stacking of multiple active layers. TSV-based 3D IC's offer significant advantages in performance due to reduction in interconnect lengths, and design flexibility in vertical floor planning. However, a critical challenge for the 3D IC integration is thermal management. In this paper, we present a new analytical 3D model and numerical simulations of the temperature field for the 3D chip using the formalism of inplane orthogonal functions. The model takes into account heat transfer through external surfaces of the chip, inhomogeneous electric heating within the layer (localized heating), inter layer heat transfer with possible inhomogeneous TSV placement and micro channel cooling. Our simulations implement the proposed model and demonstrate its viability and computational efficiency for temperature field optimization.
三维(3D)集成电路(IC)技术正在成为解决当前二维半导体器件小型化物理限制的潜在替代方案。3D集成电路基于硅通孔(TSV)的概念和多个有源层的垂直堆叠。基于tsv的3D集成电路在性能上具有显著优势,因为它减少了互连长度,并且在垂直地板规划方面具有设计灵活性。然而,3D集成电路的一个关键挑战是热管理。本文提出了一种新的三维解析模型,并利用平面正交函数的形式对三维芯片的温度场进行了数值模拟。该模型考虑了通过芯片外表面的传热、层内不均匀的电加热(局部加热)、可能不均匀的TSV放置的层间传热和微通道冷却。仿真结果验证了该模型在温度场优化中的可行性和计算效率。
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引用次数: 5
LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search LMgr:一个具有动态拓扑更新和弯曲感知最优路径搜索的低内存全局路由器
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523615
Jingwei Lu, Chiu-Wing Sham
Global routing remains a fundamental physical design problem. We observe that large circuits cause high memory cost1, and modern routers could not optimize the routing path of each two-pin subnet. In this paper, (1) we develop a dynamic topology update technique to improve routing quality (2) we improve the memory efficiency with negligible performance overhead (3) we prove the non-optimality of traditional maze routing algorithm (4) we develop a novel routing algorithm and prove that it is optimum (5) we design a new global router, LMgr, which integrates all the above techniques. The experimental results on the ISPD 2008 benchmark suite show that LMgr could outperform NTHU2.0, NTUgr, FastRoute3.0 and FGR1.1 on solution quality in 13 out of 16 benchmarks and peak memory cost in 15 out of 16 benchmarks, the average memory reduction over all the benchmarks is up to 77%.
全局路由仍然是一个基本的物理设计问题。我们观察到,大型电路导致高内存成本1,并且现代路由器无法优化每个两针子网的路由路径。在本文中,(1)我们开发了一种动态拓扑更新技术来提高路由质量(2)我们在忽略性能开销的情况下提高了内存效率(3)我们证明了传统迷宫路由算法的非最优性(4)我们开发了一种新的路由算法并证明了它是最优的(5)我们设计了一种新的全局路由器LMgr,它集成了上述所有技术。在ISPD 2008基准测试套件上的实验结果表明,LMgr在16个基准测试中有13个在解决方案质量上优于NTHU2.0、NTUgr、FastRoute3.0和FGR1.1,在16个基准测试中有15个在峰值内存成本上优于NTHU2.0,在所有基准测试中平均内存减少高达77%。
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引用次数: 17
Flexible data allocation for scratch-pad memories to reduce NBTI effects 灵活的数据分配的刮擦板存储器,以减少NBTI的影响
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523591
Dimitra Papagiannopoulou, Patipan Prasertsom, R. I. Bahar
Negative Bias Temperature Instability (NBTI) is a major reliability issue in nanoscale VLSI systems. Previous work has shown how the exploitation of conventional optimization techniques can reduce the NBTI-induced aging in cache memories. Other works have proposed approaches that incorporate software directed data allocation strategies to partially recover from NBTI-induced aging in Scratchpad Memories (SPM). In this paper, we extend the existing software approach in order to enhance the memory allocation flexibility and make it more appropriate for real embedded applications. Simulation results demonstrate how our proposed data allocation strategies can help mitigate the NBTI-induced aging effects, as well as reduce the leakage energy consumption on scratch-pad memories.
负偏置温度不稳定性(NBTI)是纳米级超大规模集成电路系统的主要可靠性问题。以前的工作已经表明如何利用传统的优化技术可以减少缓存存储器中nbti引起的老化。其他的工作已经提出了结合软件定向数据分配策略的方法,以部分恢复刮擦板存储器(SPM)中nbti引起的老化。在本文中,我们扩展了现有的软件方法,以提高内存分配的灵活性,使其更适合实际的嵌入式应用。仿真结果表明,我们提出的数据分配策略可以有效地缓解nbti引起的老化效应,并降低刮擦板存储器的泄漏能耗。
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引用次数: 7
SRAM bit-line electromigration mechanism and its prevention scheme SRAM位线电迁移机制及其预防方案
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523624
Zhong Guan, M. Marek-Sadowska, S. Nassif
In this paper, we demonstrate that signal lines in SRAM arrays are prone to electromigration (EM). Our analysis shows that the read operation can cause unidirectional current flow in bit-lines. Thus the length of bit-lines should be bounded not only by performance requirements, but also by the Blech length constraint to avoid EM. We propose a method of determining the bit-line width under layout constraints to maximize the number of cells attached to a bit-line, while ensuing the reliability of the bit-line and maintaining SRAM performance. We also study the effects of SRAM parameter variations on the EM-safe bit-line length. Simulation results show that the EM-safe bit-line length decreases as technology scales, temperature or frequency rise, and parameter variations increase.
在本文中,我们证明SRAM阵列中的信号线容易发生电迁移(EM)。我们的分析表明,读操作可以引起位线上的单向电流流动。因此,位线的长度不仅应受到性能要求的限制,还应受到Blech长度约束的限制,以避免EM。我们提出了一种在布局约束下确定位线宽度的方法,以最大限度地增加附着在位线上的单元数,同时保证位线的可靠性并保持SRAM性能。我们还研究了SRAM参数变化对em安全位线长度的影响。仿真结果表明,电磁安全位线长度随着技术规模、温度或频率的升高以及参数变化的增加而减小。
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引用次数: 17
Fast FPGA-based fault injection tool for embedded processors 基于fpga的嵌入式处理器快速故障注入工具
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523654
Mohammad Shokrolah Shirazi, B. Morris, H. Selvaraj
FPGA-based fault injection methods have recently become more popular since they provide high speed in fault injection experiments. During each fault injection experiment, FPGA should send data related with observation points back to host computer for fault tolerant analysis. Since there is high data volume, FPGA should spend most of its time in communication. In this paper, we solve this problem by bringing all parts of fault injection tool inside FPGA. The area overhead problem related with observation data is obviated by using simple observation circuit. As case study, we injected 6400 SEU faults into OpensRISC 1200 processor over the Cyclone II FPGA. Results show that our fault injection experiments are done more than 400 times faster than one of the traditional FPGA based fault injection methods with only 5% area overhead.
基于fpga的故障注入方法由于提供了高速的故障注入实验,近年来越来越受欢迎。在每次故障注入实验中,FPGA将与观测点相关的数据发回上位机进行容错分析。由于数据量大,FPGA应该把大部分时间花在通信上。本文通过将故障注入工具的各个部分集成到FPGA中来解决这一问题。利用简单的观测电路,解决了观测数据的面积开销问题。作为案例研究,我们通过Cyclone II FPGA将6400个SEU故障注入到OpensRISC 1200处理器中。结果表明,我们的故障注入实验比传统的基于FPGA的故障注入方法快400倍以上,而面积开销仅为5%。
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引用次数: 15
期刊
International Symposium on Quality Electronic Design (ISQED)
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