Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523638
Ken Yano, Takanori Hayashida, Toshinori Sato
The demand of power saving and highly dependable LSI has increased by the miniaturization of device process technology and the spread of portable devices such as mobile phones. The design method which takes the worst case scenario makes the design margin too large because of the parameter variations in the deep submicron domain and it has serious impact for performance and power consumption. To deal with excessive design margins, typical-case design method with canary FF has been proposed so far. By using canary FF, variability-aware large guard band can be decreased. In this paper, we describe how canary FF can be integrated in a typical digital circuit design flow in detail and analyze the area and power overheads compared with the worst-case design method. The analysis is done by implementing two conventional 32-bit RISC processor cores; miniMIPS and MeP (Media Embedded Processor). The results show that our proposed method can reduce chip areas effectively and power overhead can be reduced to very small.
{"title":"Improving timing error tolerance without impact on chip area and power consumption","authors":"Ken Yano, Takanori Hayashida, Toshinori Sato","doi":"10.1109/ISQED.2013.6523638","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523638","url":null,"abstract":"The demand of power saving and highly dependable LSI has increased by the miniaturization of device process technology and the spread of portable devices such as mobile phones. The design method which takes the worst case scenario makes the design margin too large because of the parameter variations in the deep submicron domain and it has serious impact for performance and power consumption. To deal with excessive design margins, typical-case design method with canary FF has been proposed so far. By using canary FF, variability-aware large guard band can be decreased. In this paper, we describe how canary FF can be integrated in a typical digital circuit design flow in detail and analyze the area and power overheads compared with the worst-case design method. The analysis is done by implementing two conventional 32-bit RISC processor cores; miniMIPS and MeP (Media Embedded Processor). The results show that our proposed method can reduce chip areas effectively and power overhead can be reduced to very small.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121042521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523649
Jing Xie, Yang Du, Yuan Xie
Optimizing energy consumption for electronic systems has been an important design focus. Multi-power domain design is widely used for low power and high performance applications. Data transfer between power domains needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which leads to large area and performance overhead. In this paper, we propose a CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. Our design separates power rails in each tier, substantially reducing physical design complexity and area penalty. The design is implemented in a 45nm low power technology. It shows 20%-35% smaller clock to Q and 30% energy saving comparing with existing LCFF designs. The proposed design also shows better robustness with ±10% voltage variation.
{"title":"CPDI: Cross-power-domain interface circuit design in monolithic 3D technology","authors":"Jing Xie, Yang Du, Yuan Xie","doi":"10.1109/ISQED.2013.6523649","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523649","url":null,"abstract":"Optimizing energy consumption for electronic systems has been an important design focus. Multi-power domain design is widely used for low power and high performance applications. Data transfer between power domains needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which leads to large area and performance overhead. In this paper, we propose a CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. Our design separates power rails in each tier, substantially reducing physical design complexity and area penalty. The design is implemented in a 45nm low power technology. It shows 20%-35% smaller clock to Q and 30% energy saving comparing with existing LCFF designs. The proposed design also shows better robustness with ±10% voltage variation.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523631
Youhua Shi, Hiroaki Igarashi, N. Togawa, M. Yanagisawa
Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees “always correct” operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with “always correct” outputs.
{"title":"Suspicious timing error prediction with in-cycle clock gating","authors":"Youhua Shi, Hiroaki Igarashi, N. Togawa, M. Yanagisawa","doi":"10.1109/ISQED.2013.6523631","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523631","url":null,"abstract":"Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees “always correct” operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with “always correct” outputs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523590
S. Kiamehr, F. Firouzi, M. Tahoori
Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues of VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips. Accurate aging-aware timing analysis is a key requirement to consider these effects in the design cycle. Our analysis shows that a separate (independent) analysis of different sources of aging leads to significant overestimation of post-aging delay. To overcome the problem of existing methods, we propose a new aging-aware gate delay model that precisely captures the combined effect of different aging sources on delay. Our results obtained from a set of benchmark circuits show that, our proposed gate-delay model estimates the aging-induced Δdelay by 7.8% (translating to 36.0% MTTF) more accurately in comparison to prior techniques. Moreover, we present a flow for integrating the proposed gate delay model with commercial timing analysis tools.
{"title":"Aging-aware timing analysis considering combined effects of NBTI and PBTI","authors":"S. Kiamehr, F. Firouzi, M. Tahoori","doi":"10.1109/ISQED.2013.6523590","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523590","url":null,"abstract":"Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues of VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips. Accurate aging-aware timing analysis is a key requirement to consider these effects in the design cycle. Our analysis shows that a separate (independent) analysis of different sources of aging leads to significant overestimation of post-aging delay. To overcome the problem of existing methods, we propose a new aging-aware gate delay model that precisely captures the combined effect of different aging sources on delay. Our results obtained from a set of benchmark circuits show that, our proposed gate-delay model estimates the aging-induced Δdelay by 7.8% (translating to 36.0% MTTF) more accurately in comparison to prior techniques. Moreover, we present a flow for integrating the proposed gate delay model with commercial timing analysis tools.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123225081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523644
D. Venuto
A low power smart temperature sensor followed by an SC amplifier and a 12bit Successive-Approximation analogue-digital converter (ADC) to compensate temperature deviation in drug electrochemical detection, is here presented. The proposed design is accurate within 0.1°C over the temperature range of -55°C to 125°C. A PTAT voltage is used for temperature monitoring. The succeeding ADC digitizes the output with a bit-clock of 50-kHz. The ADC has a Figure-of-Merit of 66 fJ/conversion-step. The system is implemented in an NXP CMOS 0.14μm technology. The die area is 0.21 mm2 and the whole system consumes less than 16μW for 1.2V of voltage supply.
{"title":"Low power sensor for temperature compensation in molecular biosensing","authors":"D. Venuto","doi":"10.1109/ISQED.2013.6523644","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523644","url":null,"abstract":"A low power smart temperature sensor followed by an SC amplifier and a 12bit Successive-Approximation analogue-digital converter (ADC) to compensate temperature deviation in drug electrochemical detection, is here presented. The proposed design is accurate within 0.1°C over the temperature range of -55°C to 125°C. A PTAT voltage is used for temperature monitoring. The succeeding ADC digitizes the output with a bit-clock of 50-kHz. The ADC has a Figure-of-Merit of 66 fJ/conversion-step. The system is implemented in an NXP CMOS 0.14μm technology. The die area is 0.21 mm2 and the whole system consumes less than 16μW for 1.2V of voltage supply.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121844236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523642
K. Subramaniyan, P. Larsson-Edefors
In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS'89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.
{"title":"Manufacturable nanometer designs using standard cells with regular layout","authors":"K. Subramaniyan, P. Larsson-Edefors","doi":"10.1109/ISQED.2013.6523642","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523642","url":null,"abstract":"In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS'89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129927221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523678
Yong Zou, S. Pasricha
In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs. RESYN employs a nested evolutionary algorithm approach to guide the mapping of cores on a die, and opportunistically determine locations to insert fault tolerance mechanisms in the NoC to minimize energy while satisfying reliability constraints. Our experimental results show that RESYN can reduce energy costs by 14.5% on average compared to a fully protected NoC, while still maintaining more than a 90% fault tolerance. If higher levels of reliability are desired, RESYN can generate a Pareto set of solutions allowing designers to select the most energy-efficient solution for any reliability goal. Given the increasing importance of reliability in the nanometer era for MPSoCs, this work provides important perspectives that can guide the reduction of overheads of reliable NoC design.
{"title":"Reliability-aware and energy-efficient synthesis of NoC based MPSoCs","authors":"Yong Zou, S. Pasricha","doi":"10.1109/ISQED.2013.6523678","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523678","url":null,"abstract":"In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs. RESYN employs a nested evolutionary algorithm approach to guide the mapping of cores on a die, and opportunistically determine locations to insert fault tolerance mechanisms in the NoC to minimize energy while satisfying reliability constraints. Our experimental results show that RESYN can reduce energy costs by 14.5% on average compared to a fully protected NoC, while still maintaining more than a 90% fault tolerance. If higher levels of reliability are desired, RESYN can generate a Pareto set of solutions allowing designers to select the most energy-efficient solution for any reliability goal. Given the increasing importance of reliability in the nanometer era for MPSoCs, this work provides important perspectives that can guide the reduction of overheads of reliable NoC design.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523647
M. Cotter, Huichu Liu, S. Datta, N. Vijaykrishnan
As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs. Due to the nature of TFETs, some of the flip-flop designs that are evaluated require additional modifications beyond simple device replacement-most notably the pseudo-static D flip-flop (DFF). We find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.
{"title":"Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications","authors":"M. Cotter, Huichu Liu, S. Datta, N. Vijaykrishnan","doi":"10.1109/ISQED.2013.6523647","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523647","url":null,"abstract":"As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs. Due to the nature of TFETs, some of the flip-flop designs that are evaluated require additional modifications beyond simple device replacement-most notably the pseudo-static D flip-flop (DFF). We find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130272879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523684
Suming Lai, Peng Li
This paper presents an output-capacitorless low-dropout voltage regulator designed in a commercial 90nm CMOS technology for low-voltage applications. The power efficiency of the regulator is enhanced by significantly reducing its dropout voltage and quiescent current consumption. The resultant degradation of its transient regulation performance is compensated by a novel auxiliary circuit using switched-capacitor technique. The regulator operates under 1V supply voltage with a 0.9V output and delivers a maximum DC current of 100mA. The power efficiency under the full-load condition is about 90% and under the light-load condition (1mA load current) it maintains above 86%. For transient performance, when a 100mA load current step with 5ns rise/fall time is applied, the output voltage droop and overshoot are both within 10% of the steady-state value, while it would exceed 40% without the auxiliary circuit. Monte Carlo and temperature-sweep simulation results show that the LDO is robust to process and temperature variations and device mismatches.
{"title":"A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulation","authors":"Suming Lai, Peng Li","doi":"10.1109/ISQED.2013.6523684","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523684","url":null,"abstract":"This paper presents an output-capacitorless low-dropout voltage regulator designed in a commercial 90nm CMOS technology for low-voltage applications. The power efficiency of the regulator is enhanced by significantly reducing its dropout voltage and quiescent current consumption. The resultant degradation of its transient regulation performance is compensated by a novel auxiliary circuit using switched-capacitor technique. The regulator operates under 1V supply voltage with a 0.9V output and delivers a maximum DC current of 100mA. The power efficiency under the full-load condition is about 90% and under the light-load condition (1mA load current) it maintains above 86%. For transient performance, when a 100mA load current step with 5ns rise/fall time is applied, the output voltage droop and overshoot are both within 10% of the steady-state value, while it would exceed 40% without the auxiliary circuit. Monte Carlo and temperature-sweep simulation results show that the LDO is robust to process and temperature variations and device mismatches.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125744677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523622
Jiyuan Luan, M. Divita
Data retention lifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed- a single transistor EPROM cell as well as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention lifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.
{"title":"Analysis and reliability test to improve the data retention performance of EPROM circuits","authors":"Jiyuan Luan, M. Divita","doi":"10.1109/ISQED.2013.6523622","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523622","url":null,"abstract":"Data retention lifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed- a single transistor EPROM cell as well as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention lifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114535625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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