Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523647
M. Cotter, Huichu Liu, S. Datta, N. Vijaykrishnan
As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs. Due to the nature of TFETs, some of the flip-flop designs that are evaluated require additional modifications beyond simple device replacement-most notably the pseudo-static D flip-flop (DFF). We find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.
{"title":"Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications","authors":"M. Cotter, Huichu Liu, S. Datta, N. Vijaykrishnan","doi":"10.1109/ISQED.2013.6523647","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523647","url":null,"abstract":"As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs. Due to the nature of TFETs, some of the flip-flop designs that are evaluated require additional modifications beyond simple device replacement-most notably the pseudo-static D flip-flop (DFF). We find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130272879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523653
D. Bhatta, I. Mukhopadhyay, S. Natarajan, P. Goteti, Bin Xue
Measurement of the quality of tests run during high volume manufacturing of microprocessors is important to ensure desired outgoing product quality. For digital logic on die, such measurement is performed using techniques such as fast event-driven fault simulation using mature fault models such as stuck-at and transition faults. For analog modules on die, such test quality measurement is not performed in practice due to lack of (a) mature fault models to describe analog failures, and (b) automated, efficient and accurate fault simulation methods. This work is a first step towards our objective of establishing a practical methodology to measure analog test quality. We show promising results of a semi-automated fault simulation approach on analog modules of a high speed serial IO receiver that compares (a) two manufacturing tests in terms of their defect detection capability as measured by their fault coverages for gross and parametric faults, and, (b) the accuracy and performance of using models versus schematics for fault effect propagation.
{"title":"Framework for analog test coverage","authors":"D. Bhatta, I. Mukhopadhyay, S. Natarajan, P. Goteti, Bin Xue","doi":"10.1109/ISQED.2013.6523653","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523653","url":null,"abstract":"Measurement of the quality of tests run during high volume manufacturing of microprocessors is important to ensure desired outgoing product quality. For digital logic on die, such measurement is performed using techniques such as fast event-driven fault simulation using mature fault models such as stuck-at and transition faults. For analog modules on die, such test quality measurement is not performed in practice due to lack of (a) mature fault models to describe analog failures, and (b) automated, efficient and accurate fault simulation methods. This work is a first step towards our objective of establishing a practical methodology to measure analog test quality. We show promising results of a semi-automated fault simulation approach on analog modules of a high speed serial IO receiver that compares (a) two manufacturing tests in terms of their defect detection capability as measured by their fault coverages for gross and parametric faults, and, (b) the accuracy and performance of using models versus schematics for fault effect propagation.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129293267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523678
Yong Zou, S. Pasricha
In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs. RESYN employs a nested evolutionary algorithm approach to guide the mapping of cores on a die, and opportunistically determine locations to insert fault tolerance mechanisms in the NoC to minimize energy while satisfying reliability constraints. Our experimental results show that RESYN can reduce energy costs by 14.5% on average compared to a fully protected NoC, while still maintaining more than a 90% fault tolerance. If higher levels of reliability are desired, RESYN can generate a Pareto set of solutions allowing designers to select the most energy-efficient solution for any reliability goal. Given the increasing importance of reliability in the nanometer era for MPSoCs, this work provides important perspectives that can guide the reduction of overheads of reliable NoC design.
{"title":"Reliability-aware and energy-efficient synthesis of NoC based MPSoCs","authors":"Yong Zou, S. Pasricha","doi":"10.1109/ISQED.2013.6523678","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523678","url":null,"abstract":"In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads that can disrupt stringent chip power budgets and thermal constraints. In this paper, we propose a novel design-time framework (RESYN) to trade-off energy consumption and reliability in the NoC fabric at the system level for MPSoCs. RESYN employs a nested evolutionary algorithm approach to guide the mapping of cores on a die, and opportunistically determine locations to insert fault tolerance mechanisms in the NoC to minimize energy while satisfying reliability constraints. Our experimental results show that RESYN can reduce energy costs by 14.5% on average compared to a fully protected NoC, while still maintaining more than a 90% fault tolerance. If higher levels of reliability are desired, RESYN can generate a Pareto set of solutions allowing designers to select the most energy-efficient solution for any reliability goal. Given the increasing importance of reliability in the nanometer era for MPSoCs, this work provides important perspectives that can guide the reduction of overheads of reliable NoC design.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523642
K. Subramaniyan, P. Larsson-Edefors
In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS'89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.
{"title":"Manufacturable nanometer designs using standard cells with regular layout","authors":"K. Subramaniyan, P. Larsson-Edefors","doi":"10.1109/ISQED.2013.6523642","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523642","url":null,"abstract":"In addition to performance considerations, designing VLSI circuits at nanometer-scale process technology nodes demands considerations related to manufacturability and cost. Regular layout patterns are known to enhance resilience to random as well as certain types of systematic variations. In this contribution we assess the implications of this layout regularity using design automation for Critical Feature Analysis (CFA) and raw metrics, such as via count. Using the ISCAS'89 benchmark suite, for each benchmark circuit we compare place-and-route implementations that are based on semi-regular and ultra-regular cell layouts. While the CFA counter-intuitively suggests that implementations using ultra-regular layouts have lower Design for Manufacturability (DFM) scores than those using semi-regular layouts, we find that ultra-regular layouts yield implementations with an average of 22% fewer vias at the cost of a small wire length increase.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129927221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523644
D. Venuto
A low power smart temperature sensor followed by an SC amplifier and a 12bit Successive-Approximation analogue-digital converter (ADC) to compensate temperature deviation in drug electrochemical detection, is here presented. The proposed design is accurate within 0.1°C over the temperature range of -55°C to 125°C. A PTAT voltage is used for temperature monitoring. The succeeding ADC digitizes the output with a bit-clock of 50-kHz. The ADC has a Figure-of-Merit of 66 fJ/conversion-step. The system is implemented in an NXP CMOS 0.14μm technology. The die area is 0.21 mm2 and the whole system consumes less than 16μW for 1.2V of voltage supply.
{"title":"Low power sensor for temperature compensation in molecular biosensing","authors":"D. Venuto","doi":"10.1109/ISQED.2013.6523644","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523644","url":null,"abstract":"A low power smart temperature sensor followed by an SC amplifier and a 12bit Successive-Approximation analogue-digital converter (ADC) to compensate temperature deviation in drug electrochemical detection, is here presented. The proposed design is accurate within 0.1°C over the temperature range of -55°C to 125°C. A PTAT voltage is used for temperature monitoring. The succeeding ADC digitizes the output with a bit-clock of 50-kHz. The ADC has a Figure-of-Merit of 66 fJ/conversion-step. The system is implemented in an NXP CMOS 0.14μm technology. The die area is 0.21 mm2 and the whole system consumes less than 16μW for 1.2V of voltage supply.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121844236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523649
Jing Xie, Yang Du, Yuan Xie
Optimizing energy consumption for electronic systems has been an important design focus. Multi-power domain design is widely used for low power and high performance applications. Data transfer between power domains needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which leads to large area and performance overhead. In this paper, we propose a CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. Our design separates power rails in each tier, substantially reducing physical design complexity and area penalty. The design is implemented in a 45nm low power technology. It shows 20%-35% smaller clock to Q and 30% energy saving comparing with existing LCFF designs. The proposed design also shows better robustness with ±10% voltage variation.
{"title":"CPDI: Cross-power-domain interface circuit design in monolithic 3D technology","authors":"Jing Xie, Yang Du, Yuan Xie","doi":"10.1109/ISQED.2013.6523649","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523649","url":null,"abstract":"Optimizing energy consumption for electronic systems has been an important design focus. Multi-power domain design is widely used for low power and high performance applications. Data transfer between power domains needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which leads to large area and performance overhead. In this paper, we propose a CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. Our design separates power rails in each tier, substantially reducing physical design complexity and area penalty. The design is implemented in a 45nm low power technology. It shows 20%-35% smaller clock to Q and 30% energy saving comparing with existing LCFF designs. The proposed design also shows better robustness with ±10% voltage variation.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523638
Ken Yano, Takanori Hayashida, Toshinori Sato
The demand of power saving and highly dependable LSI has increased by the miniaturization of device process technology and the spread of portable devices such as mobile phones. The design method which takes the worst case scenario makes the design margin too large because of the parameter variations in the deep submicron domain and it has serious impact for performance and power consumption. To deal with excessive design margins, typical-case design method with canary FF has been proposed so far. By using canary FF, variability-aware large guard band can be decreased. In this paper, we describe how canary FF can be integrated in a typical digital circuit design flow in detail and analyze the area and power overheads compared with the worst-case design method. The analysis is done by implementing two conventional 32-bit RISC processor cores; miniMIPS and MeP (Media Embedded Processor). The results show that our proposed method can reduce chip areas effectively and power overhead can be reduced to very small.
{"title":"Improving timing error tolerance without impact on chip area and power consumption","authors":"Ken Yano, Takanori Hayashida, Toshinori Sato","doi":"10.1109/ISQED.2013.6523638","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523638","url":null,"abstract":"The demand of power saving and highly dependable LSI has increased by the miniaturization of device process technology and the spread of portable devices such as mobile phones. The design method which takes the worst case scenario makes the design margin too large because of the parameter variations in the deep submicron domain and it has serious impact for performance and power consumption. To deal with excessive design margins, typical-case design method with canary FF has been proposed so far. By using canary FF, variability-aware large guard band can be decreased. In this paper, we describe how canary FF can be integrated in a typical digital circuit design flow in detail and analyze the area and power overheads compared with the worst-case design method. The analysis is done by implementing two conventional 32-bit RISC processor cores; miniMIPS and MeP (Media Embedded Processor). The results show that our proposed method can reduce chip areas effectively and power overhead can be reduced to very small.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121042521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523592
Jongpil Jung, K. Kang, G. Micheli, C. Kyung
Three-dimensional (3-D) memory stacking is one of the most promising solutions to tackle memory bandwidth problems in chip multiprocessors. In this work, we propose an efficient runtime 3-D cache management technique which not only takes advantage of the low memory access latency through vertical interconnections, but also exploits runtime memory access demand of applications which varies dynamically with time. Experimental results show that the proposed method offers performance improvement by up to 26.7% and on average 13.1% compared with a configuration of private stacked cache.
{"title":"Runtime 3-D stacked cache management for chip-multiprocessors","authors":"Jongpil Jung, K. Kang, G. Micheli, C. Kyung","doi":"10.1109/ISQED.2013.6523592","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523592","url":null,"abstract":"Three-dimensional (3-D) memory stacking is one of the most promising solutions to tackle memory bandwidth problems in chip multiprocessors. In this work, we propose an efficient runtime 3-D cache management technique which not only takes advantage of the low memory access latency through vertical interconnections, but also exploits runtime memory access demand of applications which varies dynamically with time. Experimental results show that the proposed method offers performance improvement by up to 26.7% and on average 13.1% compared with a configuration of private stacked cache.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133678362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523584
T. Chan, A. Kahng, Jiajia Li
3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and “More than Moore” scaling. However, 3DICs bring simultaneous challenges of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions and optimizations in 3DICs. Initial motivating studies show that in the presence of manufacturing variability, different die stacking orders can lead to as much as 2 years (~44%) difference in MTTF of a 3DIC stack. We study MTTF-driven die-stacking optimization with consideration of variability, and propose a “rule-of-thumb” guideline for stacking optimization to improve peak temperature as well as reliability in 3DICs. We also propose integer-linear programming (ILP) methods for reliability-driven die-stacking optimization. Our methods can achieve ~7% and ~28% improvement in average and minimum MTTF, respectively, of 3DICs; we also achieve ~3% improvement in performance under fixed reliability constraints. Our stacking optimizations can help improve 3DIC product yields under reliability requirements. Our research also yields the notable observation that a limited amount of manufacturing variation can “help” improve 3DIC product reliability when die-stacking optimization is applied.
{"title":"Reliability-constrained die stacking order in 3DICs under manufacturing variability","authors":"T. Chan, A. Kahng, Jiajia Li","doi":"10.1109/ISQED.2013.6523584","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523584","url":null,"abstract":"3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and “More than Moore” scaling. However, 3DICs bring simultaneous challenges of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions and optimizations in 3DICs. Initial motivating studies show that in the presence of manufacturing variability, different die stacking orders can lead to as much as 2 years (~44%) difference in MTTF of a 3DIC stack. We study MTTF-driven die-stacking optimization with consideration of variability, and propose a “rule-of-thumb” guideline for stacking optimization to improve peak temperature as well as reliability in 3DICs. We also propose integer-linear programming (ILP) methods for reliability-driven die-stacking optimization. Our methods can achieve ~7% and ~28% improvement in average and minimum MTTF, respectively, of 3DICs; we also achieve ~3% improvement in performance under fixed reliability constraints. Our stacking optimizations can help improve 3DIC product yields under reliability requirements. Our research also yields the notable observation that a limited amount of manufacturing variation can “help” improve 3DIC product reliability when die-stacking optimization is applied.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122186548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523634
S. Salahuddin, Hailong Jiao, V. Kursun
A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors.
{"title":"A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability","authors":"S. Salahuddin, Hailong Jiao, V. Kursun","doi":"10.1109/ISQED.2013.6523634","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523634","url":null,"abstract":"A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134366306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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