Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523675
Yi Xiang, S. Pasricha
In this paper, we focus on power and thermal management for multicore embedded systems with solar energy harvesting as the power source and a periodic hard real-time task set as the workload. We design a novel semi-dynamic scheme, which reschedules tasks at the beginning of specified time epochs. By rejecting job instances of certain tasks until the next rescheduling point, our scheduler dispatches a subset of tasks that comply with the predicted energy budget and thermal conditions. Our approach reacts to run-time energy harvesting power variation without losing the consistency of the periodic task set, which helps to scale processor speed evenly by utilizing slack time efficiently without the need for complex slack reclamation algorithms, as in prior work. When applied to a multicore platform, our approach offers a chance to shut down cores and reassign tasks for superior energy efficiency. As a result, experimental results show up to 70% miss rate reduction compared to prior work. Unlike any prior work, our approach also integrates thermal management to reduce peak temperature while minimizing miss rate for energy harvesting embedded systems.
{"title":"Thermal-aware semi-dynamic power management for multicore systems with energy harvesting","authors":"Yi Xiang, S. Pasricha","doi":"10.1109/ISQED.2013.6523675","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523675","url":null,"abstract":"In this paper, we focus on power and thermal management for multicore embedded systems with solar energy harvesting as the power source and a periodic hard real-time task set as the workload. We design a novel semi-dynamic scheme, which reschedules tasks at the beginning of specified time epochs. By rejecting job instances of certain tasks until the next rescheduling point, our scheduler dispatches a subset of tasks that comply with the predicted energy budget and thermal conditions. Our approach reacts to run-time energy harvesting power variation without losing the consistency of the periodic task set, which helps to scale processor speed evenly by utilizing slack time efficiently without the need for complex slack reclamation algorithms, as in prior work. When applied to a multicore platform, our approach offers a chance to shut down cores and reassign tasks for superior energy efficiency. As a result, experimental results show up to 70% miss rate reduction compared to prior work. Unlike any prior work, our approach also integrates thermal management to reduce peak temperature while minimizing miss rate for energy harvesting embedded systems.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523611
A. Ceyhan, A. Naeemi
The trade-offs between the technology parameters of various interconnect technologies are investigated on the basis of their impacts on the circuit performances of emerging post-CMOS devices. In this paper, carbon nanotube field-effect transistor (CNFET), nanowire-based gate-all-around (GAA) tunneling field-effect transistor (TFET), FinFET and sub-threshold CMOS circuits are studied. Each of these devices are paired with the conventional Cu/low-k interconnect, single-wall carbon nanotube (SWNT) interconnect manufactured in horizontal bundles or in a single layer, and multi-layer graphene nanoribbon (GNR) interconnect. The relative performances of all these interconnect technologies with each type of device are evaluated. The interconnect technology option that gives the best performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported for each of the device technologies.
{"title":"Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices","authors":"A. Ceyhan, A. Naeemi","doi":"10.1109/ISQED.2013.6523611","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523611","url":null,"abstract":"The trade-offs between the technology parameters of various interconnect technologies are investigated on the basis of their impacts on the circuit performances of emerging post-CMOS devices. In this paper, carbon nanotube field-effect transistor (CNFET), nanowire-based gate-all-around (GAA) tunneling field-effect transistor (TFET), FinFET and sub-threshold CMOS circuits are studied. Each of these devices are paired with the conventional Cu/low-k interconnect, single-wall carbon nanotube (SWNT) interconnect manufactured in horizontal bundles or in a single layer, and multi-layer graphene nanoribbon (GNR) interconnect. The relative performances of all these interconnect technologies with each type of device are evaluated. The interconnect technology option that gives the best performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported for each of the device technologies.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116371474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523610
C. Pan, A. Ceyhan, A. Naeemi
The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.
{"title":"System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs","authors":"C. Pan, A. Ceyhan, A. Naeemi","doi":"10.1109/ISQED.2013.6523610","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523610","url":null,"abstract":"The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132992583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523593
N. Kapadia, S. Pasricha
A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry MPSoCs, the already hard problem of voltage island-aware Network-on-Chip (NoC) design has become even more challenging. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider design of the PDN while synthesizing NoCs. In this work, for the first time, we propose a novel system-level co-synthesis methodology that minimizes 3D NoC energy while meeting performance goals; and simultaneously optimizes the 3D PDN design while satisfying IR-drop constraints. Our experimental results show that the proposed co-synthesis methodology meets IR-drop constraints while minimizing energy consumption for several real-world applications, improving upon results from traditional system-level methodologies that perform PDN design and NoC synthesis separately.
{"title":"A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs","authors":"N. Kapadia, S. Pasricha","doi":"10.1109/ISQED.2013.6523593","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523593","url":null,"abstract":"A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry MPSoCs, the already hard problem of voltage island-aware Network-on-Chip (NoC) design has become even more challenging. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider design of the PDN while synthesizing NoCs. In this work, for the first time, we propose a novel system-level co-synthesis methodology that minimizes 3D NoC energy while meeting performance goals; and simultaneously optimizes the 3D PDN design while satisfying IR-drop constraints. Our experimental results show that the proposed co-synthesis methodology meets IR-drop constraints while minimizing energy consumption for several real-world applications, improving upon results from traditional system-level methodologies that perform PDN design and NoC synthesis separately.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523685
A. Anvesha, M. Baghini
A novel ultra low power, area-efficient, current-mode instrumentation amplifier (CMIA) with embedded bandpass filter, for acquisition of bio-potential signals is presented. A novel bias front-end is also presented, which achieves CMRR of 195dB at 1Hz in the presence of ±5% component mismatch. The CMIA has a tunable bandwidth, from 160Hz to 7.2kHz with input referred rms noise of 2.24 μV in frequency band of 5mHz to 160Hz. The CMIA is designed in 180nm mixed-mode CMOS technology and provides rail to rail output voltage of 1.65V(p-p) while dissipating 39 μW, at 1.8V supply voltage. The output of CMIA doesn't need any further signal conditioning.
{"title":"A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioning","authors":"A. Anvesha, M. Baghini","doi":"10.1109/ISQED.2013.6523685","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523685","url":null,"abstract":"A novel ultra low power, area-efficient, current-mode instrumentation amplifier (CMIA) with embedded bandpass filter, for acquisition of bio-potential signals is presented. A novel bias front-end is also presented, which achieves CMRR of 195dB at 1Hz in the presence of ±5% component mismatch. The CMIA has a tunable bandwidth, from 160Hz to 7.2kHz with input referred rms noise of 2.24 μV in frequency band of 5mHz to 160Hz. The CMIA is designed in 180nm mixed-mode CMOS technology and provides rail to rail output voltage of 1.65V(p-p) while dissipating 39 μW, at 1.8V supply voltage. The output of CMIA doesn't need any further signal conditioning.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133494131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523677
Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram
Distributed computing systems have attracted a lot of attention due to increasing demand for high performance computing and storage. Resource allocation is one of the most important challenges in the distributed systems especially when the clients have some Service Level Agreements (SLAs) and the total profit depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem in a server cluster is considered. The objective is to maximize the total profit, which is the total price gained from serving the clients subtracted by the operation cost of the server cluster. The total price depends on the average request response time for each client as defined in their utility functions, while the operating cost is related to the total energy consumption. A joint optimization framework is proposed, comprised of request dispatching, dynamic voltage and frequency scaling (DVFS) for individual cores, as well as server-level and core-level consolidations. Each core in the cluster is modeled using a continuous-time Markov decision process (CTMDP). A near-optimal hierarchical solution is proposed, consisting of a central manager and distributed local agents. Each local agent employs linear programming-based CTMDP solving method to solve the DVFS problem for the corresponding core. The central manager solves the request dispatching problem and finds the optimal number of turned on cores and servers for request processing, thereby achieving a desirable tradeoff between service request response time and power consumption. Experimental results demonstrate that the proposed near-optimal resource allocation and consolidation algorithm consistently outperforms baseline algorithms.
{"title":"Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model","authors":"Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram","doi":"10.1109/ISQED.2013.6523677","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523677","url":null,"abstract":"Distributed computing systems have attracted a lot of attention due to increasing demand for high performance computing and storage. Resource allocation is one of the most important challenges in the distributed systems especially when the clients have some Service Level Agreements (SLAs) and the total profit depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem in a server cluster is considered. The objective is to maximize the total profit, which is the total price gained from serving the clients subtracted by the operation cost of the server cluster. The total price depends on the average request response time for each client as defined in their utility functions, while the operating cost is related to the total energy consumption. A joint optimization framework is proposed, comprised of request dispatching, dynamic voltage and frequency scaling (DVFS) for individual cores, as well as server-level and core-level consolidations. Each core in the cluster is modeled using a continuous-time Markov decision process (CTMDP). A near-optimal hierarchical solution is proposed, consisting of a central manager and distributed local agents. Each local agent employs linear programming-based CTMDP solving method to solve the DVFS problem for the corresponding core. The central manager solves the request dispatching problem and finds the optimal number of turned on cores and servers for request processing, thereby achieving a desirable tradeoff between service request response time and power consumption. Experimental results demonstrate that the proposed near-optimal resource allocation and consolidation algorithm consistently outperforms baseline algorithms.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523584
T. Chan, A. Kahng, Jiajia Li
3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and “More than Moore” scaling. However, 3DICs bring simultaneous challenges of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions and optimizations in 3DICs. Initial motivating studies show that in the presence of manufacturing variability, different die stacking orders can lead to as much as 2 years (~44%) difference in MTTF of a 3DIC stack. We study MTTF-driven die-stacking optimization with consideration of variability, and propose a “rule-of-thumb” guideline for stacking optimization to improve peak temperature as well as reliability in 3DICs. We also propose integer-linear programming (ILP) methods for reliability-driven die-stacking optimization. Our methods can achieve ~7% and ~28% improvement in average and minimum MTTF, respectively, of 3DICs; we also achieve ~3% improvement in performance under fixed reliability constraints. Our stacking optimizations can help improve 3DIC product yields under reliability requirements. Our research also yields the notable observation that a limited amount of manufacturing variation can “help” improve 3DIC product reliability when die-stacking optimization is applied.
{"title":"Reliability-constrained die stacking order in 3DICs under manufacturing variability","authors":"T. Chan, A. Kahng, Jiajia Li","doi":"10.1109/ISQED.2013.6523584","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523584","url":null,"abstract":"3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and “More than Moore” scaling. However, 3DICs bring simultaneous challenges of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions and optimizations in 3DICs. Initial motivating studies show that in the presence of manufacturing variability, different die stacking orders can lead to as much as 2 years (~44%) difference in MTTF of a 3DIC stack. We study MTTF-driven die-stacking optimization with consideration of variability, and propose a “rule-of-thumb” guideline for stacking optimization to improve peak temperature as well as reliability in 3DICs. We also propose integer-linear programming (ILP) methods for reliability-driven die-stacking optimization. Our methods can achieve ~7% and ~28% improvement in average and minimum MTTF, respectively, of 3DICs; we also achieve ~3% improvement in performance under fixed reliability constraints. Our stacking optimizations can help improve 3DIC product yields under reliability requirements. Our research also yields the notable observation that a limited amount of manufacturing variation can “help” improve 3DIC product reliability when die-stacking optimization is applied.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122186548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523634
S. Salahuddin, Hailong Jiao, V. Kursun
A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors.
{"title":"A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability","authors":"S. Salahuddin, Hailong Jiao, V. Kursun","doi":"10.1109/ISQED.2013.6523634","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523634","url":null,"abstract":"A new FinFET memory circuit technique based on asymmetrically gate underlap engineered bitline access transistors is proposed in this paper. The strengths of the asymmetrical bitline access transistors are weakened during read operations while enhanced during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability and write ability are both enhanced by up to 6.12x and 58%, respectively, without causing any area overhead as compared to the standard symmetrical six-FinFET SRAM cells in a 15nm FinFET technology. The leakage power consumption is also reduced by up to 96.5% with the proposed asymmetrical FinFET SRAM cell as compared to the standard six-FinFET SRAM cells with symmetrical bitline access transistors.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134366306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523661
Young-Ho Gong, H. Jang, S. Chung
Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip caches becomes larger. The increased cache size causes the leakage power and area of the on-chip caches to increase. Recently, to reduce the leakage power and area of the SRAM based cache, the SRAM-eDRAM hybrid cache was proposed. For SRAM-eDRAM hybrid caches, however, there has not been any study to analyze the effects of the reduced area on wire delay, cache access time, and performance. By replacing half (or three fourth) of SRAM cells by small eDRAM cells for the SRAM-eDRAM hybrid caches, wire length is shortened, which eventually results in the reduction of wire delay and cache access time. In this paper, we evaluate the SRAM-eDRAM hybrid caches in terms of the energy, area, wire delay, access time, and performance. We show that the SRAM-eDRAM hybrid cache reduces the energy consumption, area, wire delay, and SRAM array access time by up to 53.9%, 49.9%, 50.4%, and 38.7%, respectively, compared to the SRAM based cache.
{"title":"Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay","authors":"Young-Ho Gong, H. Jang, S. Chung","doi":"10.1109/ISQED.2013.6523661","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523661","url":null,"abstract":"Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip caches becomes larger. The increased cache size causes the leakage power and area of the on-chip caches to increase. Recently, to reduce the leakage power and area of the SRAM based cache, the SRAM-eDRAM hybrid cache was proposed. For SRAM-eDRAM hybrid caches, however, there has not been any study to analyze the effects of the reduced area on wire delay, cache access time, and performance. By replacing half (or three fourth) of SRAM cells by small eDRAM cells for the SRAM-eDRAM hybrid caches, wire length is shortened, which eventually results in the reduction of wire delay and cache access time. In this paper, we evaluate the SRAM-eDRAM hybrid caches in terms of the energy, area, wire delay, access time, and performance. We show that the SRAM-eDRAM hybrid cache reduces the energy consumption, area, wire delay, and SRAM array access time by up to 53.9%, 49.9%, 50.4%, and 38.7%, respectively, compared to the SRAM based cache.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133890918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523592
Jongpil Jung, K. Kang, G. Micheli, C. Kyung
Three-dimensional (3-D) memory stacking is one of the most promising solutions to tackle memory bandwidth problems in chip multiprocessors. In this work, we propose an efficient runtime 3-D cache management technique which not only takes advantage of the low memory access latency through vertical interconnections, but also exploits runtime memory access demand of applications which varies dynamically with time. Experimental results show that the proposed method offers performance improvement by up to 26.7% and on average 13.1% compared with a configuration of private stacked cache.
{"title":"Runtime 3-D stacked cache management for chip-multiprocessors","authors":"Jongpil Jung, K. Kang, G. Micheli, C. Kyung","doi":"10.1109/ISQED.2013.6523592","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523592","url":null,"abstract":"Three-dimensional (3-D) memory stacking is one of the most promising solutions to tackle memory bandwidth problems in chip multiprocessors. In this work, we propose an efficient runtime 3-D cache management technique which not only takes advantage of the low memory access latency through vertical interconnections, but also exploits runtime memory access demand of applications which varies dynamically with time. Experimental results show that the proposed method offers performance improvement by up to 26.7% and on average 13.1% compared with a configuration of private stacked cache.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133678362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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