Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523675
Yi Xiang, S. Pasricha
In this paper, we focus on power and thermal management for multicore embedded systems with solar energy harvesting as the power source and a periodic hard real-time task set as the workload. We design a novel semi-dynamic scheme, which reschedules tasks at the beginning of specified time epochs. By rejecting job instances of certain tasks until the next rescheduling point, our scheduler dispatches a subset of tasks that comply with the predicted energy budget and thermal conditions. Our approach reacts to run-time energy harvesting power variation without losing the consistency of the periodic task set, which helps to scale processor speed evenly by utilizing slack time efficiently without the need for complex slack reclamation algorithms, as in prior work. When applied to a multicore platform, our approach offers a chance to shut down cores and reassign tasks for superior energy efficiency. As a result, experimental results show up to 70% miss rate reduction compared to prior work. Unlike any prior work, our approach also integrates thermal management to reduce peak temperature while minimizing miss rate for energy harvesting embedded systems.
{"title":"Thermal-aware semi-dynamic power management for multicore systems with energy harvesting","authors":"Yi Xiang, S. Pasricha","doi":"10.1109/ISQED.2013.6523675","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523675","url":null,"abstract":"In this paper, we focus on power and thermal management for multicore embedded systems with solar energy harvesting as the power source and a periodic hard real-time task set as the workload. We design a novel semi-dynamic scheme, which reschedules tasks at the beginning of specified time epochs. By rejecting job instances of certain tasks until the next rescheduling point, our scheduler dispatches a subset of tasks that comply with the predicted energy budget and thermal conditions. Our approach reacts to run-time energy harvesting power variation without losing the consistency of the periodic task set, which helps to scale processor speed evenly by utilizing slack time efficiently without the need for complex slack reclamation algorithms, as in prior work. When applied to a multicore platform, our approach offers a chance to shut down cores and reassign tasks for superior energy efficiency. As a result, experimental results show up to 70% miss rate reduction compared to prior work. Unlike any prior work, our approach also integrates thermal management to reduce peak temperature while minimizing miss rate for energy harvesting embedded systems.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523611
A. Ceyhan, A. Naeemi
The trade-offs between the technology parameters of various interconnect technologies are investigated on the basis of their impacts on the circuit performances of emerging post-CMOS devices. In this paper, carbon nanotube field-effect transistor (CNFET), nanowire-based gate-all-around (GAA) tunneling field-effect transistor (TFET), FinFET and sub-threshold CMOS circuits are studied. Each of these devices are paired with the conventional Cu/low-k interconnect, single-wall carbon nanotube (SWNT) interconnect manufactured in horizontal bundles or in a single layer, and multi-layer graphene nanoribbon (GNR) interconnect. The relative performances of all these interconnect technologies with each type of device are evaluated. The interconnect technology option that gives the best performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported for each of the device technologies.
{"title":"Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices","authors":"A. Ceyhan, A. Naeemi","doi":"10.1109/ISQED.2013.6523611","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523611","url":null,"abstract":"The trade-offs between the technology parameters of various interconnect technologies are investigated on the basis of their impacts on the circuit performances of emerging post-CMOS devices. In this paper, carbon nanotube field-effect transistor (CNFET), nanowire-based gate-all-around (GAA) tunneling field-effect transistor (TFET), FinFET and sub-threshold CMOS circuits are studied. Each of these devices are paired with the conventional Cu/low-k interconnect, single-wall carbon nanotube (SWNT) interconnect manufactured in horizontal bundles or in a single layer, and multi-layer graphene nanoribbon (GNR) interconnect. The relative performances of all these interconnect technologies with each type of device are evaluated. The interconnect technology option that gives the best performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported for each of the device technologies.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116371474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523610
C. Pan, A. Ceyhan, A. Naeemi
The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.
{"title":"System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs","authors":"C. Pan, A. Ceyhan, A. Naeemi","doi":"10.1109/ISQED.2013.6523610","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523610","url":null,"abstract":"The ON/OFF current and input capacitance of InAs nanowire based gate-all-around (GAA) tunnel FETs are modeled. Based on the device- and system-level models, optimization has been done and comparison has been made between TFETs and CMOS devices under different constraints for both single- and multi-core processors. Several performance metrics have been analyzed, which shows that optimal numbers of cores, power density and die size area exist for maximizing various design targets.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132992583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523593
N. Kapadia, S. Pasricha
A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry MPSoCs, the already hard problem of voltage island-aware Network-on-Chip (NoC) design has become even more challenging. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider design of the PDN while synthesizing NoCs. In this work, for the first time, we propose a novel system-level co-synthesis methodology that minimizes 3D NoC energy while meeting performance goals; and simultaneously optimizes the 3D PDN design while satisfying IR-drop constraints. Our experimental results show that the proposed co-synthesis methodology meets IR-drop constraints while minimizing energy consumption for several real-world applications, improving upon results from traditional system-level methodologies that perform PDN design and NoC synthesis separately.
{"title":"A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs","authors":"N. Kapadia, S. Pasricha","doi":"10.1109/ISQED.2013.6523593","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523593","url":null,"abstract":"A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry MPSoCs, the already hard problem of voltage island-aware Network-on-Chip (NoC) design has become even more challenging. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider design of the PDN while synthesizing NoCs. In this work, for the first time, we propose a novel system-level co-synthesis methodology that minimizes 3D NoC energy while meeting performance goals; and simultaneously optimizes the 3D PDN design while satisfying IR-drop constraints. Our experimental results show that the proposed co-synthesis methodology meets IR-drop constraints while minimizing energy consumption for several real-world applications, improving upon results from traditional system-level methodologies that perform PDN design and NoC synthesis separately.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523685
A. Anvesha, M. Baghini
A novel ultra low power, area-efficient, current-mode instrumentation amplifier (CMIA) with embedded bandpass filter, for acquisition of bio-potential signals is presented. A novel bias front-end is also presented, which achieves CMRR of 195dB at 1Hz in the presence of ±5% component mismatch. The CMIA has a tunable bandwidth, from 160Hz to 7.2kHz with input referred rms noise of 2.24 μV in frequency band of 5mHz to 160Hz. The CMIA is designed in 180nm mixed-mode CMOS technology and provides rail to rail output voltage of 1.65V(p-p) while dissipating 39 μW, at 1.8V supply voltage. The output of CMIA doesn't need any further signal conditioning.
{"title":"A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioning","authors":"A. Anvesha, M. Baghini","doi":"10.1109/ISQED.2013.6523685","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523685","url":null,"abstract":"A novel ultra low power, area-efficient, current-mode instrumentation amplifier (CMIA) with embedded bandpass filter, for acquisition of bio-potential signals is presented. A novel bias front-end is also presented, which achieves CMRR of 195dB at 1Hz in the presence of ±5% component mismatch. The CMIA has a tunable bandwidth, from 160Hz to 7.2kHz with input referred rms noise of 2.24 μV in frequency band of 5mHz to 160Hz. The CMIA is designed in 180nm mixed-mode CMOS technology and provides rail to rail output voltage of 1.65V(p-p) while dissipating 39 μW, at 1.8V supply voltage. The output of CMIA doesn't need any further signal conditioning.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133494131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523677
Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram
Distributed computing systems have attracted a lot of attention due to increasing demand for high performance computing and storage. Resource allocation is one of the most important challenges in the distributed systems especially when the clients have some Service Level Agreements (SLAs) and the total profit depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem in a server cluster is considered. The objective is to maximize the total profit, which is the total price gained from serving the clients subtracted by the operation cost of the server cluster. The total price depends on the average request response time for each client as defined in their utility functions, while the operating cost is related to the total energy consumption. A joint optimization framework is proposed, comprised of request dispatching, dynamic voltage and frequency scaling (DVFS) for individual cores, as well as server-level and core-level consolidations. Each core in the cluster is modeled using a continuous-time Markov decision process (CTMDP). A near-optimal hierarchical solution is proposed, consisting of a central manager and distributed local agents. Each local agent employs linear programming-based CTMDP solving method to solve the DVFS problem for the corresponding core. The central manager solves the request dispatching problem and finds the optimal number of turned on cores and servers for request processing, thereby achieving a desirable tradeoff between service request response time and power consumption. Experimental results demonstrate that the proposed near-optimal resource allocation and consolidation algorithm consistently outperforms baseline algorithms.
{"title":"Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model","authors":"Yanzhi Wang, Shuang Chen, H. Goudarzi, Massoud Pedram","doi":"10.1109/ISQED.2013.6523677","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523677","url":null,"abstract":"Distributed computing systems have attracted a lot of attention due to increasing demand for high performance computing and storage. Resource allocation is one of the most important challenges in the distributed systems especially when the clients have some Service Level Agreements (SLAs) and the total profit depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation problem in a server cluster is considered. The objective is to maximize the total profit, which is the total price gained from serving the clients subtracted by the operation cost of the server cluster. The total price depends on the average request response time for each client as defined in their utility functions, while the operating cost is related to the total energy consumption. A joint optimization framework is proposed, comprised of request dispatching, dynamic voltage and frequency scaling (DVFS) for individual cores, as well as server-level and core-level consolidations. Each core in the cluster is modeled using a continuous-time Markov decision process (CTMDP). A near-optimal hierarchical solution is proposed, consisting of a central manager and distributed local agents. Each local agent employs linear programming-based CTMDP solving method to solve the DVFS problem for the corresponding core. The central manager solves the request dispatching problem and finds the optimal number of turned on cores and servers for request processing, thereby achieving a desirable tradeoff between service request response time and power consumption. Experimental results demonstrate that the proposed near-optimal resource allocation and consolidation algorithm consistently outperforms baseline algorithms.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523631
Youhua Shi, Hiroaki Igarashi, N. Togawa, M. Yanagisawa
Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees “always correct” operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with “always correct” outputs.
{"title":"Suspicious timing error prediction with in-cycle clock gating","authors":"Youhua Shi, Hiroaki Igarashi, N. Togawa, M. Yanagisawa","doi":"10.1109/ISQED.2013.6523631","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523631","url":null,"abstract":"Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees “always correct” operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with “always correct” outputs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523622
Jiyuan Luan, M. Divita
Data retention lifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed- a single transistor EPROM cell as well as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention lifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.
{"title":"Analysis and reliability test to improve the data retention performance of EPROM circuits","authors":"Jiyuan Luan, M. Divita","doi":"10.1109/ISQED.2013.6523622","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523622","url":null,"abstract":"Data retention lifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed- a single transistor EPROM cell as well as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention lifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114535625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523590
S. Kiamehr, F. Firouzi, M. Tahoori
Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues of VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips. Accurate aging-aware timing analysis is a key requirement to consider these effects in the design cycle. Our analysis shows that a separate (independent) analysis of different sources of aging leads to significant overestimation of post-aging delay. To overcome the problem of existing methods, we propose a new aging-aware gate delay model that precisely captures the combined effect of different aging sources on delay. Our results obtained from a set of benchmark circuits show that, our proposed gate-delay model estimates the aging-induced Δdelay by 7.8% (translating to 36.0% MTTF) more accurately in comparison to prior techniques. Moreover, we present a flow for integrating the proposed gate delay model with commercial timing analysis tools.
{"title":"Aging-aware timing analysis considering combined effects of NBTI and PBTI","authors":"S. Kiamehr, F. Firouzi, M. Tahoori","doi":"10.1109/ISQED.2013.6523590","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523590","url":null,"abstract":"Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues of VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips. Accurate aging-aware timing analysis is a key requirement to consider these effects in the design cycle. Our analysis shows that a separate (independent) analysis of different sources of aging leads to significant overestimation of post-aging delay. To overcome the problem of existing methods, we propose a new aging-aware gate delay model that precisely captures the combined effect of different aging sources on delay. Our results obtained from a set of benchmark circuits show that, our proposed gate-delay model estimates the aging-induced Δdelay by 7.8% (translating to 36.0% MTTF) more accurately in comparison to prior techniques. Moreover, we present a flow for integrating the proposed gate delay model with commercial timing analysis tools.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123225081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523684
Suming Lai, Peng Li
This paper presents an output-capacitorless low-dropout voltage regulator designed in a commercial 90nm CMOS technology for low-voltage applications. The power efficiency of the regulator is enhanced by significantly reducing its dropout voltage and quiescent current consumption. The resultant degradation of its transient regulation performance is compensated by a novel auxiliary circuit using switched-capacitor technique. The regulator operates under 1V supply voltage with a 0.9V output and delivers a maximum DC current of 100mA. The power efficiency under the full-load condition is about 90% and under the light-load condition (1mA load current) it maintains above 86%. For transient performance, when a 100mA load current step with 5ns rise/fall time is applied, the output voltage droop and overshoot are both within 10% of the steady-state value, while it would exceed 40% without the auxiliary circuit. Monte Carlo and temperature-sweep simulation results show that the LDO is robust to process and temperature variations and device mismatches.
{"title":"A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulation","authors":"Suming Lai, Peng Li","doi":"10.1109/ISQED.2013.6523684","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523684","url":null,"abstract":"This paper presents an output-capacitorless low-dropout voltage regulator designed in a commercial 90nm CMOS technology for low-voltage applications. The power efficiency of the regulator is enhanced by significantly reducing its dropout voltage and quiescent current consumption. The resultant degradation of its transient regulation performance is compensated by a novel auxiliary circuit using switched-capacitor technique. The regulator operates under 1V supply voltage with a 0.9V output and delivers a maximum DC current of 100mA. The power efficiency under the full-load condition is about 90% and under the light-load condition (1mA load current) it maintains above 86%. For transient performance, when a 100mA load current step with 5ns rise/fall time is applied, the output voltage droop and overshoot are both within 10% of the steady-state value, while it would exceed 40% without the auxiliary circuit. Monte Carlo and temperature-sweep simulation results show that the LDO is robust to process and temperature variations and device mismatches.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125744677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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