Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670879
Rongchang Yan, Bruce C. Kim
Multi-chip Module (MCM) technology has become an important means to package high performance systems. However, wide usage of MCM technology has been restricted by the cost of design, fabrication and testing. Since electrical testing can cost as high as 50% of the MCM cost in the near future, an efficient MCM substrate test scheme is needed to ensure system reliability and reduce test cost. Numerous techniques are being pursued in the industry for testing unpopulated MCM substrates. Recently, a novel technique for testing MCM substrate using single-ended probe has been developed. In this paper, we present a heuristic algorithm to reduce the single-ended probe travel time in MCM substrate testing. Using our new novel heuristic algorithm, the test cost is dramatically reduced.
{"title":"A novel routing algorithm for MCM substrate verification using single-ended probe","authors":"Rongchang Yan, Bruce C. Kim","doi":"10.1109/VTEST.1998.670879","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670879","url":null,"abstract":"Multi-chip Module (MCM) technology has become an important means to package high performance systems. However, wide usage of MCM technology has been restricted by the cost of design, fabrication and testing. Since electrical testing can cost as high as 50% of the MCM cost in the near future, an efficient MCM substrate test scheme is needed to ensure system reliability and reduce test cost. Numerous techniques are being pursued in the industry for testing unpopulated MCM substrates. Recently, a novel technique for testing MCM substrate using single-ended probe has been developed. In this paper, we present a heuristic algorithm to reduce the single-ended probe travel time in MCM substrate testing. Using our new novel heuristic algorithm, the test cost is dramatically reduced.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114790263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670884
C. Stroud, J. Tannehill
Testing requirements for the application of built-in self-test to fault tolerant circuits include: (1) detection of all single and multiple faults and (2) verification of correct circuit operation in the presence of faults. Modifications to built-in logic block observer (BILBO) and circular BIST are proposed which make these techniques satisfy both testing requirements. Evaluation of the two modified BIST approaches via single and multiple stuck-at fault simulation in conjunction with a random fault injection procedure indicate that the modified BILBO approach provides better testing results.
{"title":"Applying built-in self-test to majority voting fault tolerant circuits","authors":"C. Stroud, J. Tannehill","doi":"10.1109/VTEST.1998.670884","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670884","url":null,"abstract":"Testing requirements for the application of built-in self-test to fault tolerant circuits include: (1) detection of all single and multiple faults and (2) verification of correct circuit operation in the presence of faults. Modifications to built-in logic block observer (BILBO) and circular BIST are proposed which make these techniques satisfy both testing requirements. Evaluation of the two modified BIST approaches via single and multiple stuck-at fault simulation in conjunction with a random fault injection procedure indicate that the modified BILBO approach provides better testing results.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128210081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670888
Hsing-Chung Liang, Chung-Len Lee, Jwu-E Chen
This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits.
{"title":"Partial reset and scan for flip-flops based on states requirement for test generation","authors":"Hsing-Chung Liang, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/VTEST.1998.670888","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670888","url":null,"abstract":"This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133698875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670870
G. Parthasarathy, M. Bushnell
We propose a novel hardware model to reconfigure a sequential ULSI circuit for partial-scanned delay-fault built-in self-test (BIST). We modify the standard stuck-fault BIST model to ensure highly robust delay tests by inserting hardware to avoid circuit hazards that invalidate delay tests. The model treats un-scanned flip-flops and latches as inverters or buffers. We propose a novel minimum feedback vertex set (FVS) algorithm based on quadratic 0-1 programming (which has O(n/sup 2/) complexity) for partial-scan flip-flop selection. We obtain a pipelined sequential circuit and insert parity-flippers to remove hazards during testing. We avoid placing hardware on time-critical paths. We find the FVS and insert deglitching hardware for all of the 1989 ISCAS circuits.
{"title":"Towards simultaneous delay-fault built-in self-test and partial-scan insertion","authors":"G. Parthasarathy, M. Bushnell","doi":"10.1109/VTEST.1998.670870","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670870","url":null,"abstract":"We propose a novel hardware model to reconfigure a sequential ULSI circuit for partial-scanned delay-fault built-in self-test (BIST). We modify the standard stuck-fault BIST model to ensure highly robust delay tests by inserting hardware to avoid circuit hazards that invalidate delay tests. The model treats un-scanned flip-flops and latches as inverters or buffers. We propose a novel minimum feedback vertex set (FVS) algorithm based on quadratic 0-1 programming (which has O(n/sup 2/) complexity) for partial-scan flip-flop selection. We obtain a pipelined sequential circuit and insert parity-flippers to remove hazards during testing. We avoid placing hardware on time-critical paths. We find the FVS and insert deglitching hardware for all of the 1989 ISCAS circuits.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114836221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670889
X. Kavousianos, D. Nikolos
This paper presents a novel method for designing type-I and type-II single and double output TSC Berger code checkers taking into account a realistic fault model including stuck-at, transistor stuck-open, transistor stuck-on, resistive bridging faults and breaks. A benefit of the proposed type-I single and double output checkers is that all faults are testable by a very small set of code words the number of which does not increase with the information length, that is, the checkers are C-testable. The proposed double output checkers are two-times faster than the corresponding single output checkers, but require for their implementation twice as many transistors as the single output checkers. The proposed single output checkers are the first known TSC Berger code checkers in the open literature, while the type-I single output checkers are near optimal with respect to the number of the transistors required for their implementation. The checkers of this paper with either, single or double output are significantly more efficient, with respect to the implementation area and speed than the already known from the open literature Berger code checkers.
{"title":"Novel single and double output TSC Berger code checkers","authors":"X. Kavousianos, D. Nikolos","doi":"10.1109/VTEST.1998.670889","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670889","url":null,"abstract":"This paper presents a novel method for designing type-I and type-II single and double output TSC Berger code checkers taking into account a realistic fault model including stuck-at, transistor stuck-open, transistor stuck-on, resistive bridging faults and breaks. A benefit of the proposed type-I single and double output checkers is that all faults are testable by a very small set of code words the number of which does not increase with the information length, that is, the checkers are C-testable. The proposed double output checkers are two-times faster than the corresponding single output checkers, but require for their implementation twice as many transistors as the single output checkers. The proposed single output checkers are the first known TSC Berger code checkers in the open literature, while the type-I single output checkers are near optimal with respect to the number of the transistors required for their implementation. The checkers of this paper with either, single or double output are significantly more efficient, with respect to the implementation area and speed than the already known from the open literature Berger code checkers.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114775697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670913
J. Kasten
Wireless technologies like cellular phones, pagers, cordless phones, RF identification devices (RFID) and Global Positioning Systems (GPS) of today are required to be convenient and affordable. For this reason radio frequency (RF) integrated circuits (ICs) are developed and tested which meet the cost and function demands of the consumer. In this tutorial RF measurements are introduced in three parts: RF devices, measurement types and measurement systems. Since some of the developments of mixed signal analogue testing may be of great importance in this area of testing, they are also taken into account.
{"title":"An introduction to RF testing: device, method and system","authors":"J. Kasten","doi":"10.1109/VTEST.1998.670913","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670913","url":null,"abstract":"Wireless technologies like cellular phones, pagers, cordless phones, RF identification devices (RFID) and Global Positioning Systems (GPS) of today are required to be convenient and affordable. For this reason radio frequency (RF) integrated circuits (ICs) are developed and tested which meet the cost and function demands of the consumer. In this tutorial RF measurements are introduced in three parts: RF devices, measurement types and measurement systems. Since some of the developments of mixed signal analogue testing may be of great importance in this area of testing, they are also taken into account.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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