Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670858
J. Chang, Chao-Wen Tseng, Yi-Chin Chu, S. Wattal, M. Purtell, E. McCluskey
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed the Stage 1 tests were packaged for further investigation. This paper describes the experimental setup and the preliminary results for the final package test. We focus on the correlation among various defect classes, including IDDQ failures, Very-Low-Voltage (VLV) failures, timing-independent combinational (TIC) defects, and non-TIC defects. We used 2 supply voltages for VLV tests. Two test speeds were used at each supply voltage. 9 dies failed only the VLV Boolean tests, and 7 of these were confirmed to have had high IDDQ measurement results. We also investigated the defect classes of the test escapes for 100% single stuck fault (SSF), transition fault, and IDDQ test sets.
{"title":"Experimental results for IDDQ and VLV testing","authors":"J. Chang, Chao-Wen Tseng, Yi-Chin Chu, S. Wattal, M. Purtell, E. McCluskey","doi":"10.1109/VTEST.1998.670858","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670858","url":null,"abstract":"An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed the Stage 1 tests were packaged for further investigation. This paper describes the experimental setup and the preliminary results for the final package test. We focus on the correlation among various defect classes, including IDDQ failures, Very-Low-Voltage (VLV) failures, timing-independent combinational (TIC) defects, and non-TIC defects. We used 2 supply voltages for VLV tests. Two test speeds were used at each supply voltage. 9 dies failed only the VLV Boolean tests, and 7 of these were confirmed to have had high IDDQ measurement results. We also investigated the defect classes of the test escapes for 100% single stuck fault (SSF), transition fault, and IDDQ test sets.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122854561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670878
Li-C. Wang, M. Abadir, Jing Zeng
Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for army design validation have been proposed and had great success, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, the authors propose a way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way for the evaluation of the quality of various validation approaches at both logic and transistor levels. Experimental results using different validation approaches on PowerPC microprocessor arrays will be reported.
{"title":"On logic and transistor level design error detection of various validation approaches for PowerPC(TM) microprocessor arrays","authors":"Li-C. Wang, M. Abadir, Jing Zeng","doi":"10.1109/VTEST.1998.670878","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670878","url":null,"abstract":"Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. At Somerset, validation of array designs relies on both formal verification and vector simulation. Although several methods for army design validation have been proposed and had great success, little evidence has been reported for the effectiveness of these methods with respect to the detection of design errors. In this paper, the authors propose a way of measuring the effectiveness of different validation approaches based on automatic design error injection and simulation. The technique provides a systematic way for the evaluation of the quality of various validation approaches at both logic and transistor levels. Experimental results using different validation approaches on PowerPC microprocessor arrays will be reported.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124464390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670872
J. Savir
A new weighted random pattern (WRP) design for testability (DFT) is described where the shift register latches (SRLs) distributed throughout the chip are modified so that they can generate biased pseudo-random patterns upon demand. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to "go after" the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.
{"title":"Distributed generation of weighted random patterns","authors":"J. Savir","doi":"10.1109/VTEST.1998.670872","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670872","url":null,"abstract":"A new weighted random pattern (WRP) design for testability (DFT) is described where the shift register latches (SRLs) distributed throughout the chip are modified so that they can generate biased pseudo-random patterns upon demand. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to \"go after\" the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128568784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670851
B. Pouya, N. Touba
A new method is presented for designing space compactors for either deterministic testing or pseudo-random testing. A tree of elementary gates (AND, OR, NAND, NOR) is used to combine the outputs of the circuit-under-test (CUT) in a way that zero-aliasing is guaranteed with no modification of the CUT. The elementary-tree is synthesized by adding one gate at a time without introducing redundancy. The end result is a cascaded network CUT followed by space compactor, that is irredundant and has fewer outputs than the CUT alone. All faults in the CUT and space compactor can be tested. Only the outputs of the space compactor need to be observed during testing. Experimental results are surprising; they show that very high compaction ratios can be achieved with zero-aliasing elementary-tree space compactors. Compared with parity trees and other space compactor designs that have been proposed, the method presented here requires less overhead and yet guarantees zero-aliasing.
{"title":"Synthesis of zero-aliasing elementary-tree space compactors","authors":"B. Pouya, N. Touba","doi":"10.1109/VTEST.1998.670851","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670851","url":null,"abstract":"A new method is presented for designing space compactors for either deterministic testing or pseudo-random testing. A tree of elementary gates (AND, OR, NAND, NOR) is used to combine the outputs of the circuit-under-test (CUT) in a way that zero-aliasing is guaranteed with no modification of the CUT. The elementary-tree is synthesized by adding one gate at a time without introducing redundancy. The end result is a cascaded network CUT followed by space compactor, that is irredundant and has fewer outputs than the CUT alone. All faults in the CUT and space compactor can be tested. Only the outputs of the space compactor need to be observed during testing. Experimental results are surprising; they show that very high compaction ratios can be achieved with zero-aliasing elementary-tree space compactors. Compared with parity trees and other space compactor designs that have been proposed, the method presented here requires less overhead and yet guarantees zero-aliasing.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126783790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670887
M. Flottes, R. Pires, B. Rouzeyre, L. Volpe
In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.
{"title":"Low cost partial scan design: a high level synthesis approach","authors":"M. Flottes, R. Pires, B. Rouzeyre, L. Volpe","doi":"10.1109/VTEST.1998.670887","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670887","url":null,"abstract":"In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670865
X. Lin, I. Pomeranz, S. Reddy
We describe a time-efficient procedure for removing sequentially redundant faults from synchronous sequential circuits with synchronizing sequences. We use the properties of redundant faults and propose several methods to identify subsets of redundant faults that can be removed simultaneously from the circuit. By removing several redundant faults simultaneously, the number of repetitions of the test generation procedure invoked to identify redundant faults is reduced. Experimental results presented in this work demonstrate the effectiveness of the proposed removal procedure.
{"title":"On removing redundant faults in synchronous sequential circuits","authors":"X. Lin, I. Pomeranz, S. Reddy","doi":"10.1109/VTEST.1998.670865","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670865","url":null,"abstract":"We describe a time-efficient procedure for removing sequentially redundant faults from synchronous sequential circuits with synchronizing sequences. We use the properties of redundant faults and propose several methods to identify subsets of redundant faults that can be removed simultaneously from the circuit. By removing several redundant faults simultaneously, the number of repetitions of the test generation procedure invoked to identify redundant faults is reduced. Experimental results presented in this work demonstrate the effectiveness of the proposed removal procedure.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125710659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670869
U. Sparmann, Lars Köller
It has been shown previously, that paths which are internally fanout free and not nonrobustly testable with respect to at least one transition, can be removed from a circuit without changing its functional behavior. This transformation has been successfully applied in order to remove long false paths from a given circuit. In this work, we show how to apply the above transformation in order to improve delay testability. Experimental results demonstrate that large improvements in testability can be obtained at low hardware costs. In addition, the delay of the circuits is even reduced in most cases.
{"title":"Improving path delay fault testability by path removal","authors":"U. Sparmann, Lars Köller","doi":"10.1109/VTEST.1998.670869","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670869","url":null,"abstract":"It has been shown previously, that paths which are internally fanout free and not nonrobustly testable with respect to at least one transition, can be removed from a circuit without changing its functional behavior. This transformation has been successfully applied in order to remove long false paths from a given circuit. In this work, we show how to apply the above transformation in order to improve delay testability. Experimental results demonstrate that large improvements in testability can be obtained at low hardware costs. In addition, the delay of the circuits is even reduced in most cases.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129699787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670844
Ovidio V. Maiuri, W. Moore
Recent developments and future trends in VLSI/ULSI process and design technologies are introducing new levels of complexity in testing. This paper explains why modern submicron CMOS technologies are stretching test capabilities, making it easier for failures in digital integrated circuits (ICs) to elude test. Submicron transistor technologies are being forced to shift to lower power-supply voltages to maintain the internal electric field in the MOS transistors, and also to reduce power consumption. The consequent reduction of threshold voltage and the increase of leakage current are decreasing the effectiveness of quiescent control monitoring (I/sub DDQ/) testing because the reduced ratio between the MOSFET's on and of currents is making this testing technique impracticable. A possible solution to fault test escape is presented in terms of a new testing methodology: the Multidimensional Testing Paradigm (MTP). This methodology is based on the use of voltage, temperature, and frequency parameterized testing. The impact of device dimension scaling on submicron CMOS digital circuits is illustrated. Bridging faults (BFs), faults causing two physically adjacent node, in the layout of a circuit to be electrically connected to each other, are used as a representative class of fault model, and their effect on the electrical behavior of a simple digital system are described. The traditional analysis of a static gate properties as a function of the short's resistances, based on the use of the gate logic threshold as a pivot, is demonstrated to be inadequate for modern microelectronic technologies. A new, more meaningful classification of BF resistance values is introduced.
{"title":"Implications of voltage and dimension scaling on CMOS testing: the multidimensional testing paradigm","authors":"Ovidio V. Maiuri, W. Moore","doi":"10.1109/VTEST.1998.670844","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670844","url":null,"abstract":"Recent developments and future trends in VLSI/ULSI process and design technologies are introducing new levels of complexity in testing. This paper explains why modern submicron CMOS technologies are stretching test capabilities, making it easier for failures in digital integrated circuits (ICs) to elude test. Submicron transistor technologies are being forced to shift to lower power-supply voltages to maintain the internal electric field in the MOS transistors, and also to reduce power consumption. The consequent reduction of threshold voltage and the increase of leakage current are decreasing the effectiveness of quiescent control monitoring (I/sub DDQ/) testing because the reduced ratio between the MOSFET's on and of currents is making this testing technique impracticable. A possible solution to fault test escape is presented in terms of a new testing methodology: the Multidimensional Testing Paradigm (MTP). This methodology is based on the use of voltage, temperature, and frequency parameterized testing. The impact of device dimension scaling on submicron CMOS digital circuits is illustrated. Bridging faults (BFs), faults causing two physically adjacent node, in the layout of a circuit to be electrically connected to each other, are used as a representative class of fault model, and their effect on the electrical behavior of a simple digital system are described. The traditional analysis of a static gate properties as a function of the short's resistances, based on the use of the gate logic threshold as a pivot, is demonstrated to be inadequate for modern microelectronic technologies. A new, more meaningful classification of BF resistance values is introduced.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114868989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670847
Jun Zhao, F. Meyer, F. Lombardi
This paper presents two new approaches for testing interconnects of random access memories (RAM). Tire first algorithm is referred to as the Adaptive Diagnosis Algorithm (ADA), while the second algorithm is referred to as the Consecutive Diagnosis Algorithm (CDA). Initially, it is shown that the diagnosis of the address lines is the most difficult step in interconnect testing of memories as the diagnosis of faults in data lines can be resolved easily. The execution of ADA is such that the diagnosis of the address lines is performed sequentially (i.e. on a line by line basis), while enforcing the conditions by which it is possible to differentiate for each line a stuck-at fault from a short. This is determined by the operations as for diagnosis a short requires an additional READ compared with a suck-at fault. A different condition in the generation of the overall sequence is utilized in CDA; by using different test patterns for the address lines, a relation can be assessed between consecutive READ operations.
{"title":"Fault detection and diagnosis of interconnects of random access memories","authors":"Jun Zhao, F. Meyer, F. Lombardi","doi":"10.1109/VTEST.1998.670847","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670847","url":null,"abstract":"This paper presents two new approaches for testing interconnects of random access memories (RAM). Tire first algorithm is referred to as the Adaptive Diagnosis Algorithm (ADA), while the second algorithm is referred to as the Consecutive Diagnosis Algorithm (CDA). Initially, it is shown that the diagnosis of the address lines is the most difficult step in interconnect testing of memories as the diagnosis of faults in data lines can be resolved easily. The execution of ADA is such that the diagnosis of the address lines is performed sequentially (i.e. on a line by line basis), while enforcing the conditions by which it is possible to differentiate for each line a stuck-at fault from a short. This is determined by the operations as for diagnosis a short requires an additional READ compared with a suck-at fault. A different condition in the generation of the overall sequence is utilized in CDA; by using different test patterns for the address lines, a relation can be assessed between consecutive READ operations.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114892337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670899
P. R. Sidorowicz, J. Brzozowski
An approach to modeling and testing memories is presented and illustrated using an n-word by l-bit (n/spl times/l) static content-addressable memory (GAM) array for cell input stuck-at faults. An input stuck at fault model for a CAM is defined, and a test of length 7n+2l+5 with 100% fault coverage with respect to this fault model is constructed. This test also detects all the usual cell stuck-at and transition faults. Finally, some design-for-testability (DFT) modifications facilitating a further reduction of this test's length are proposed.
{"title":"An approach to modeling and testing memories and its application to CAMs","authors":"P. R. Sidorowicz, J. Brzozowski","doi":"10.1109/VTEST.1998.670899","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670899","url":null,"abstract":"An approach to modeling and testing memories is presented and illustrated using an n-word by l-bit (n/spl times/l) static content-addressable memory (GAM) array for cell input stuck-at faults. An input stuck at fault model for a CAM is defined, and a test of length 7n+2l+5 with 100% fault coverage with respect to this fault model is constructed. This test also detects all the usual cell stuck-at and transition faults. Finally, some design-for-testability (DFT) modifications facilitating a further reduction of this test's length are proposed.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114652339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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