Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670841
S. Kosonocky, A. Bright, K. W. Warren, R. Haring, S. Klepner, S. Asaad, S. Basavaiah, Bob Havreluk, D. Heidel, M. Immediato, K. Jenkins, R. Joshi, B. Parker, T. Rajeevakumar, K. Stawiasz
A "system on a chip" is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.
{"title":"Designing a testable system on a chip","authors":"S. Kosonocky, A. Bright, K. W. Warren, R. Haring, S. Klepner, S. Asaad, S. Basavaiah, Bob Havreluk, D. Heidel, M. Immediato, K. Jenkins, R. Joshi, B. Parker, T. Rajeevakumar, K. Stawiasz","doi":"10.1109/VTEST.1998.670841","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670841","url":null,"abstract":"A \"system on a chip\" is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127565806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670863
M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian
Traditional combinational fault models are not sufficient to detect to most common failure mechanisms in CMOS Iterative Logic Arrays (ILAs). The Realistic Sequential Cell Fault Model (RS-CFM) provides a comprehensive, robust test methodology for ILAs. It also satisfies the requirements for low test complexity and cell implementation independence. Adopting RS-CFM, we first provide sufficient conditions for two-dimensional (2D) ILAs to be robustly testable for first time in the literature. Then, we propose sufficient modifications to the carry-save and carry-propagate array multipliers so that they can be treated robustly with respect to RS-CPM with a test set of linear size.
{"title":"Robustly testable array multipliers under realistic sequential cell fault model","authors":"M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian","doi":"10.1109/VTEST.1998.670863","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670863","url":null,"abstract":"Traditional combinational fault models are not sufficient to detect to most common failure mechanisms in CMOS Iterative Logic Arrays (ILAs). The Realistic Sequential Cell Fault Model (RS-CFM) provides a comprehensive, robust test methodology for ILAs. It also satisfies the requirements for low test complexity and cell implementation independence. Adopting RS-CFM, we first provide sufficient conditions for two-dimensional (2D) ILAs to be robustly testable for first time in the literature. Then, we propose sufficient modifications to the carry-save and carry-propagate array multipliers so that they can be treated robustly with respect to RS-CPM with a test set of linear size.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133139490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670849
P. Bose
We describe a systematic methodology for generating performance test cases for current generation microprocessors. Such rest cases are used for: (a) validating the expected pipeline flow behavior and timing; and, (b) detecting and diagnosing performance bugs in the design. We cite examples of application to a real, superscalar processor in pre- and post-silicon stages of development.
{"title":"Performance test case generation for microprocessors","authors":"P. Bose","doi":"10.1109/VTEST.1998.670849","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670849","url":null,"abstract":"We describe a systematic methodology for generating performance test cases for current generation microprocessors. Such rest cases are used for: (a) validating the expected pipeline flow behavior and timing; and, (b) detecting and diagnosing performance bugs in the design. We cite examples of application to a real, superscalar processor in pre- and post-silicon stages of development.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115581177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670908
D. Karayiannis, S. Tragoudas
This paper presents a test pattern generator for path delay faults which generates a polynomial number of test patterns that target a large number of functionally sensitizable faults. The number of these faults may be exponential to the input site. Experimental results are presented on the ISCAS'85 benchmarks.
{"title":"A nonenumerative ATPG for functionally sensitizable path delay faults","authors":"D. Karayiannis, S. Tragoudas","doi":"10.1109/VTEST.1998.670908","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670908","url":null,"abstract":"This paper presents a test pattern generator for path delay faults which generates a polynomial number of test patterns that target a large number of functionally sensitizable faults. The number of these faults may be exponential to the input site. Experimental results are presented on the ISCAS'85 benchmarks.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129815950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670860
P. Variyam, A. Chatterjee
The use of alternate tests in addition to specification-based measurements is achieving more recognition in industry due to the higher coverage that they provide. The fault and yield coverages of these tests depend on how the pass/fail test decision is made. In this paper we address the critical issue of accurate test threshold determination for these alternate tests. We propose to post-process the given set of sensitive and linearly independent measurements to synthesize a new set of measurements based on which the pass/fail decision is made. A novel methodology for post processing the measurement results called measurement synthesis is presented. Simulation results show that test effectiveness can be greatly enhanced by measurement synthesis.
{"title":"Enhancing test effectiveness for analog circuits using synthesized measurements","authors":"P. Variyam, A. Chatterjee","doi":"10.1109/VTEST.1998.670860","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670860","url":null,"abstract":"The use of alternate tests in addition to specification-based measurements is achieving more recognition in industry due to the higher coverage that they provide. The fault and yield coverages of these tests depend on how the pass/fail test decision is made. In this paper we address the critical issue of accurate test threshold determination for these alternate tests. We propose to post-process the given set of sensitive and linearly independent measurements to synthesize a new set of measurements based on which the pass/fail decision is made. A novel methodology for post processing the measurement results called measurement synthesis is presented. Simulation results show that test effectiveness can be greatly enhanced by measurement synthesis.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124996710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670871
J. Rajski, J. Tyszer
The paper presents novel systematic design techniques for the automated synthesis of phase shifter circuits used to remove effects of structural dependencies featured by test generators driving parallel scan chains. As shown in the paper, it is possible to synthesize very large and fast phase shifters for BIST applications with guaranteed phaseshifts between scan chains and very small number of gates per channel.
{"title":"Design of phase shifters for BIST applications","authors":"J. Rajski, J. Tyszer","doi":"10.1109/VTEST.1998.670871","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670871","url":null,"abstract":"The paper presents novel systematic design techniques for the automated synthesis of phase shifter circuits used to remove effects of structural dependencies featured by test generators driving parallel scan chains. As shown in the paper, it is possible to synthesize very large and fast phase shifters for BIST applications with guaranteed phaseshifts between scan chains and very small number of gates per channel.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122521857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670873
D. Heidel, S. Dhong, H. P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz
As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.
{"title":"High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor","authors":"D. Heidel, S. Dhong, H. P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz","doi":"10.1109/VTEST.1998.670873","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670873","url":null,"abstract":"As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114935824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670848
Kazuki Shigeta, T. Ishiyama
The authors propose a new diagnosis technique based on path tracing, which diagnoses fault locations in a sequential circuit by extracting combinational circuit blocks dynamically and tracing error propagation paths from failed primary outputs to fault origins. The dynamic circuit extraction reduces analysis area, which is suitable for a large circuit. By applying this technique to several ISCAS'89 benchmark circuits, the authors demonstrated that this technique could localize faults into 20 candidates within four hours.
{"title":"A new path tracing algorithm with dynamic circuit extraction for sequential circuit fault diagnosis","authors":"Kazuki Shigeta, T. Ishiyama","doi":"10.1109/VTEST.1998.670848","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670848","url":null,"abstract":"The authors propose a new diagnosis technique based on path tracing, which diagnoses fault locations in a sequential circuit by extracting combinational circuit blocks dynamically and tracing error propagation paths from failed primary outputs to fault origins. The dynamic circuit extraction reduces analysis area, which is suitable for a large circuit. By applying this technique to several ISCAS'89 benchmark circuits, the authors demonstrated that this technique could localize faults into 20 candidates within four hours.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131146512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670892
F. Azaïs, M. Renovell, Y. Bertrand, J.-C. Bodin
In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode.
{"title":"Design-for-testability for switched-current circuits","authors":"F. Azaïs, M. Renovell, Y. Bertrand, J.-C. Bodin","doi":"10.1109/VTEST.1998.670892","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670892","url":null,"abstract":"In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134090171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670859
M. Tian, C. Shi
Efficient methods have been developed for fault simulation of linear analog circuits. However, DC fault simulation of nonlinear analog circuits-a more practically-relevant problem-remains largely unexplored. In this paper, we propose an one-step relaxation approach to nonlinear DC fault simulation. In this approach, only one Newton-Raphson iteration is performed for the faulty circuit with the DC solution of the good circuit as the initial point, and the results are used to approximate the actual results of exact fault simulation. With one-step relaxation implemented using Householder's formula, the proposed approach is numerically stable, and computationally efficient. It has a very simple circuit interpretation: the nonlinear circuit under test is modeled by a linearized circuit at its operating point, and faults are modeled as faults in the linearized circuit. Experiment results have demonstrated that the proposed approach achieves almost the same fault coverage as exact fault simulation for 29 MCNC Circuit Simulation Workshop benchmark circuits.
{"title":"Nonlinear analog DC fault simulation by one-step relaxation","authors":"M. Tian, C. Shi","doi":"10.1109/VTEST.1998.670859","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670859","url":null,"abstract":"Efficient methods have been developed for fault simulation of linear analog circuits. However, DC fault simulation of nonlinear analog circuits-a more practically-relevant problem-remains largely unexplored. In this paper, we propose an one-step relaxation approach to nonlinear DC fault simulation. In this approach, only one Newton-Raphson iteration is performed for the faulty circuit with the DC solution of the good circuit as the initial point, and the results are used to approximate the actual results of exact fault simulation. With one-step relaxation implemented using Householder's formula, the proposed approach is numerically stable, and computationally efficient. It has a very simple circuit interpretation: the nonlinear circuit under test is modeled by a linearized circuit at its operating point, and faults are modeled as faults in the linearized circuit. Experiment results have demonstrated that the proposed approach achieves almost the same fault coverage as exact fault simulation for 29 MCNC Circuit Simulation Workshop benchmark circuits.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122535568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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