Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670846
K. Lee, C. Nordquist, J. Abraham
As clock speeds of current deep submicron design technologies increase over 1 GHz and metal line spacings narrow, unexpected crosstalk effects start to degrade the circuit performance significantly. It is important for the designer to test the effects before taping out the designs. Unfortunately, conventional tests for stuck-at or delay faults are not guaranteed to expose potential crosstalk effects. This paper presents an efficient methodology for generating test vectors to detect crosstalk glitch effects in digital circuits. The ATEG (Automatic Test Extractor for Glitch) algorithm uses the multiple backrace technique, and uses a "forward-evaluation" technique in its backtacking phase which searches for the "right" entry to select by propagating "suggested values" to minimize the number of backtracks. In the glitch propagation phase, we employ a criterion function which gives a metric for determining the propagation of a transitional signal at a given gate. Our experiments show that ATEG efficiently generates test vectors to create glitches at candidate nodes.
{"title":"Automatic test pattern generation for crosstalk glitches in digital circuits","authors":"K. Lee, C. Nordquist, J. Abraham","doi":"10.1109/VTEST.1998.670846","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670846","url":null,"abstract":"As clock speeds of current deep submicron design technologies increase over 1 GHz and metal line spacings narrow, unexpected crosstalk effects start to degrade the circuit performance significantly. It is important for the designer to test the effects before taping out the designs. Unfortunately, conventional tests for stuck-at or delay faults are not guaranteed to expose potential crosstalk effects. This paper presents an efficient methodology for generating test vectors to detect crosstalk glitch effects in digital circuits. The ATEG (Automatic Test Extractor for Glitch) algorithm uses the multiple backrace technique, and uses a \"forward-evaluation\" technique in its backtacking phase which searches for the \"right\" entry to select by propagating \"suggested values\" to minimize the number of backtracks. In the glitch propagation phase, we employ a criterion function which gives a metric for determining the propagation of a transitional signal at a given gate. Our experiments show that ATEG efficiently generates test vectors to create glitches at candidate nodes.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131797834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670853
Amitava Majumdar, M. Komoda, Tim Ayres
The problem of generating DC parametric test patterns while reducing ground bounce is considered. A clear tradeoff is identified between test time and the amount of ground bounce. An algorithm generating input DC tests with minimum ground bounce is proposed. Furthermore, we propose algorithms for reducing ground bounce for output DC tests under test time constraints based on the amount of information available. Experimental results prove that these algorithms not only reduce ground bounce but also keep test time within reasonable limits.
{"title":"Ground bounce considerations in DC parametric test generation using boundary scan","authors":"Amitava Majumdar, M. Komoda, Tim Ayres","doi":"10.1109/VTEST.1998.670853","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670853","url":null,"abstract":"The problem of generating DC parametric test patterns while reducing ground bounce is considered. A clear tradeoff is identified between test time and the amount of ground bounce. An algorithm generating input DC tests with minimum ground bounce is proposed. Furthermore, we propose algorithms for reducing ground bounce for output DC tests under test time constraints based on the amount of information available. Experimental results prove that these algorithms not only reduce ground bounce but also keep test time within reasonable limits.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670902
Fulvio Corno, N. Gaudenzi, P. Prinetto, M. Reorda
This paper presents a BIST architecture for finite state machines that exploits cellular automata (CA) as pattern generators and signature analyzers. The main advantage of the proposed approach, called C/sup 2/BIST (circular cellular BIST) is that the same CA is used for generation and compaction, thus lowering substantially the area requirements. The configuration of the CA rules is performed through a generic algorithm that is shown to provide good results both in terms of fault coverage and number of reconfigurations. In many cases, no reconfiguration is necessary and the corresponding area occupation is competitive with current BIST approaches.
{"title":"On the identification of optimal cellular automata for built-in self-test of sequential circuits","authors":"Fulvio Corno, N. Gaudenzi, P. Prinetto, M. Reorda","doi":"10.1109/VTEST.1998.670902","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670902","url":null,"abstract":"This paper presents a BIST architecture for finite state machines that exploits cellular automata (CA) as pattern generators and signature analyzers. The main advantage of the proposed approach, called C/sup 2/BIST (circular cellular BIST) is that the same CA is used for generation and compaction, thus lowering substantially the area requirements. The configuration of the CA rules is performed through a generic algorithm that is shown to provide good results both in terms of fault coverage and number of reconfigurations. In many cases, no reconfiguration is necessary and the corresponding area occupation is competitive with current BIST approaches.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125546836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670843
M. Nourani, C. Papachristou
We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.
{"title":"Parallelism in structural fault testing of embedded cores","authors":"M. Nourani, C. Papachristou","doi":"10.1109/VTEST.1998.670843","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670843","url":null,"abstract":"We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a \"bypass\" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129972710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670898
A. V. Goor, S. Hamdioui
In this paper the effects of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n/sup 2/), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account.
{"title":"Fault models and tests for two-port memories","authors":"A. V. Goor, S. Hamdioui","doi":"10.1109/VTEST.1998.670898","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670898","url":null,"abstract":"In this paper the effects of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n/sup 2/), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126298101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670868
S. Majumder, V. Agrawal, M. Bushnell
We explore non-robust untestability of paths based on redundant stuck-at faults. Such untestability classification is necessary for a path to be ignored in timing verification and delay testing. A recent result states that redundant stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) faults of a line imply untestability of rising and falling delay faults, respectively, for all paths through that line. We find that this result only establishes robust untestability of paths. Starting with known examples, where a non-robust test can exist for some paths that pass through the site of a redundant stuck-at fault, we examine various classes of stuck-at fault redundancies. We prove that: (1) an unexcitable or undrivable redundant s-a-0 (s-a-1) fault will make all paths through the fault site non-robustly delay-untestable for rising (falling) transition, and (2) an unobservable fault site (causing both s-a-0 and s-a-1 faults to be redundant) can only classify the passing paths as robustly delay-untestable, Finally, we show that two singly-untestable paths, passing through the sites of separate redundant single stuck-at faults, may form a multiply-testable pair of paths provided the two redundant single stuck-at faults have a multi-fault test.
{"title":"On delay-untestable paths and stuck-fault redundancy","authors":"S. Majumder, V. Agrawal, M. Bushnell","doi":"10.1109/VTEST.1998.670868","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670868","url":null,"abstract":"We explore non-robust untestability of paths based on redundant stuck-at faults. Such untestability classification is necessary for a path to be ignored in timing verification and delay testing. A recent result states that redundant stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) faults of a line imply untestability of rising and falling delay faults, respectively, for all paths through that line. We find that this result only establishes robust untestability of paths. Starting with known examples, where a non-robust test can exist for some paths that pass through the site of a redundant stuck-at fault, we examine various classes of stuck-at fault redundancies. We prove that: (1) an unexcitable or undrivable redundant s-a-0 (s-a-1) fault will make all paths through the fault site non-robustly delay-untestable for rising (falling) transition, and (2) an unobservable fault site (causing both s-a-0 and s-a-1 faults to be redundant) can only classify the passing paths as robustly delay-untestable, Finally, we show that two singly-untestable paths, passing through the sites of separate redundant single stuck-at faults, may form a multiply-testable pair of paths provided the two redundant single stuck-at faults have a multi-fault test.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122617778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670893
A. Lechner, A. Richardson, B. Hermes, M. Ohletz
A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented.
{"title":"A design for testability study on a high performance automatic gain control circuit","authors":"A. Lechner, A. Richardson, B. Hermes, M. Ohletz","doi":"10.1109/VTEST.1998.670893","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670893","url":null,"abstract":"A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132523149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670890
M. Seuring, M. Gössel, E. Sogomonyan
In this paper a new structural method for linear output space compaction is presented. The method is applicable to concurrent checking and built-in self test (BIST). Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs output partitions are determined without fault simulation. For all ISCAS 85 benchmark circuits three groups of compacted outputs are sufficient to achieve 100% fault coverage in test mode and for 3 to 5 groups an error detection probability of 98% is obtained in on-line mode. The method can be applied to very large circuits.
{"title":"A structural approach for space compaction for concurrent checking and BIST","authors":"M. Seuring, M. Gössel, E. Sogomonyan","doi":"10.1109/VTEST.1998.670890","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670890","url":null,"abstract":"In this paper a new structural method for linear output space compaction is presented. The method is applicable to concurrent checking and built-in self test (BIST). Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs output partitions are determined without fault simulation. For all ISCAS 85 benchmark circuits three groups of compacted outputs are sufficient to achieve 100% fault coverage in test mode and for 3 to 5 groups an error detection probability of 98% is obtained in on-line mode. The method can be applied to very large circuits.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131708815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670912
Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the test pattern generation phase and selects a subset of sequences able to reduce the consumed power without reducing the fault coverage. The method is composed of three independent steps: redundant test pattern generation, power consumption measurement, optimal test sequence selection. The experimental results gathered on the ISCAS benchmark circuits show that our approach decreases the power consumption by 70% on average with respect to the original test pattern, generated ignoring the heat dissipation problem.
{"title":"A test pattern generation methodology for low power consumption","authors":"Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda","doi":"10.1109/VTEST.1998.670912","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670912","url":null,"abstract":"This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the test pattern generation phase and selects a subset of sequences able to reduce the consumed power without reducing the fault coverage. The method is composed of three independent steps: redundant test pattern generation, power consumption measurement, optimal test sequence selection. The experimental results gathered on the ISCAS benchmark circuits show that our approach decreases the power consumption by 70% on average with respect to the original test pattern, generated ignoring the heat dissipation problem.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115282113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-04-26DOI: 10.1109/VTEST.1998.670900
V. Iyengar, K. Chakrabarty, B. Murray
We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of flip-flops but few primary inputs. Such circuits are often encountered as embedded cores and filters for digital signal processing, and are inherently difficult to test. We show that statistical encoding of test sets can be combined with low-cost pattern decoding for deterministic BIST. This approach exploits recent advances in sequential circuit ATPG and unlike other BIST schemes, does not require access to gate-level models of the circuit under test. Experimental results show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time.
{"title":"Built-in self testing of sequential circuits using precomputed test sets","authors":"V. Iyengar, K. Chakrabarty, B. Murray","doi":"10.1109/VTEST.1998.670900","DOIUrl":"https://doi.org/10.1109/VTEST.1998.670900","url":null,"abstract":"We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of flip-flops but few primary inputs. Such circuits are often encountered as embedded cores and filters for digital signal processing, and are inherently difficult to test. We show that statistical encoding of test sets can be combined with low-cost pattern decoding for deterministic BIST. This approach exploits recent advances in sequential circuit ATPG and unlike other BIST schemes, does not require access to gate-level models of the circuit under test. Experimental results show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129407589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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