Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240465
D. Disanto, T. Shirley, R. Shimon
5G and aerospace/defense (A/D) trends are influencing the requirements for mm-wave test and measurement (T&M) equipment and the underlying technologies. Additional requirements such as small formfactors, lower-cost mm-wave test, and connector-less test are emerging. To meet these challenging attributes, both silicon and III-Vs have important roles to play. Si provides attractive solutions for small form-factor & high-volume applications with its excellent integration and economies of scale. However, operating voltages limit performance while high NRE costs create challenges for high-mix low-volume businesses. While III-Vs are well suited to mm-wave performance, they have significantly higher manufacturing costs and require continued advances in packaging to meet form-factor needs. Simultaneously addressing performance and cost needs at mm-wave requires careful consideration of these tradeoffs to drive selection of, and improvements in, semiconductor devices and packaging solutions.
{"title":"Technology options for mm-wave test and measurement equipment","authors":"D. Disanto, T. Shirley, R. Shimon","doi":"10.1109/CSICS.2017.8240465","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240465","url":null,"abstract":"5G and aerospace/defense (A/D) trends are influencing the requirements for mm-wave test and measurement (T&M) equipment and the underlying technologies. Additional requirements such as small formfactors, lower-cost mm-wave test, and connector-less test are emerging. To meet these challenging attributes, both silicon and III-Vs have important roles to play. Si provides attractive solutions for small form-factor & high-volume applications with its excellent integration and economies of scale. However, operating voltages limit performance while high NRE costs create challenges for high-mix low-volume businesses. While III-Vs are well suited to mm-wave performance, they have significantly higher manufacturing costs and require continued advances in packaging to meet form-factor needs. Simultaneously addressing performance and cost needs at mm-wave requires careful consideration of these tradeoffs to drive selection of, and improvements in, semiconductor devices and packaging solutions.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126798899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240466
N. Chowdhury, T. Palacios
This paper describes how the use of nanostructures can significantly increase the performance of GaN transistors. 100–400 nm fins have been defined underneath the gate electrode of AlGaN/GaN transistors to increase the gate modulation efficiency of these devices and to allow for the tuning of the threshold voltage. The proper design of these fins allows not only an improvement in the DC performance of the device, but also a significant enhancement of the rf linearity of the transistors. The excellent electron transport in these nanostructures, combined with the wide bandgap of GaN, its large effective mass and its moderate electric permittivity, also allows the potential scaling of GaN transistors below 5 nm channel length. The theoretical performance of these ultra-scaled devices is benchmarked with respect to other competing technologies.
{"title":"Nanostructured GaN transistors","authors":"N. Chowdhury, T. Palacios","doi":"10.1109/CSICS.2017.8240466","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240466","url":null,"abstract":"This paper describes how the use of nanostructures can significantly increase the performance of GaN transistors. 100–400 nm fins have been defined underneath the gate electrode of AlGaN/GaN transistors to increase the gate modulation efficiency of these devices and to allow for the tuning of the threshold voltage. The proper design of these fins allows not only an improvement in the DC performance of the device, but also a significant enhancement of the rf linearity of the transistors. The excellent electron transport in these nanostructures, combined with the wide bandgap of GaN, its large effective mass and its moderate electric permittivity, also allows the potential scaling of GaN transistors below 5 nm channel length. The theoretical performance of these ultra-scaled devices is benchmarked with respect to other competing technologies.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126771297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240458
Thé Linh Nguyen, Lionel Li, G. Salamanca, O. Mizuhara
Power consumption is the most challenging requirement as bit rate increases for a given form factor. This paper reports a 90mW 11.3Gb/s 4.4Vp-p Mach-Zehnder Modulator (MZM) driver that enables a 750mW tunable transmitter suitable for SFP+ form factor for 80km transmission system.
{"title":"90mW, 4.4Vp-p, 11.35Gb/s MZM driver enabling low-power tunable transmitter for SFP+ module application","authors":"Thé Linh Nguyen, Lionel Li, G. Salamanca, O. Mizuhara","doi":"10.1109/CSICS.2017.8240458","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240458","url":null,"abstract":"Power consumption is the most challenging requirement as bit rate increases for a given form factor. This paper reports a 90mW 11.3Gb/s 4.4Vp-p Mach-Zehnder Modulator (MZM) driver that enables a 750mW tunable transmitter suitable for SFP+ form factor for 80km transmission system.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123795622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240434
Brandon Mathieu, J. Mccue, B. Dupaix, V. Patel, S. Dooley, James Wilson, H. M. Lavasani, W. Khalil
A power- and area-efficient Low Voltage Differential Signaling (LVDS) AC coupled receiver for short links is presented. The receiver accommodates the wide LVDS common-mode range without requiring large, board-mounted AC coupling capacitors or a slow, rail-to-rail input stage. Instead, a small, on-chip coupling capacitance generates a pseudo return-to-zero (RZ) pulse that is latched into the receiver via output feedback to bias switches. This reduces the effects of baseline wander caused by DC imbalanced data streams without the need for encoding or scrambling, while outputting a full-scale CMOS digital signal. The receiver is implemented in a 130 nm SiGe BiCMOS (fT = 200 GHz) technology and is tested with a 100 mV p-p differential PRBS15, demonstrating a BER of < 10−12. The design includes low and high power modes characterized at 8 Gb/s consuming 3.7 mW and at 10 Gb/s consuming 5.1 mW, respectively. A peak efficiency of 0.46 mW/Gb/s is recorded in the low power mode. The design occupies 0.0115 mm2, including the on-chip coupling capacitance.
{"title":"An AC coupled 10 Gb/s LVDS-compatible receiver with latched data biasing in 130 nm SiGe BiCMOS","authors":"Brandon Mathieu, J. Mccue, B. Dupaix, V. Patel, S. Dooley, James Wilson, H. M. Lavasani, W. Khalil","doi":"10.1109/CSICS.2017.8240434","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240434","url":null,"abstract":"A power- and area-efficient Low Voltage Differential Signaling (LVDS) AC coupled receiver for short links is presented. The receiver accommodates the wide LVDS common-mode range without requiring large, board-mounted AC coupling capacitors or a slow, rail-to-rail input stage. Instead, a small, on-chip coupling capacitance generates a pseudo return-to-zero (RZ) pulse that is latched into the receiver via output feedback to bias switches. This reduces the effects of baseline wander caused by DC imbalanced data streams without the need for encoding or scrambling, while outputting a full-scale CMOS digital signal. The receiver is implemented in a 130 nm SiGe BiCMOS (fT = 200 GHz) technology and is tested with a 100 mV p-p differential PRBS15, demonstrating a BER of < 10−12. The design includes low and high power modes characterized at 8 Gb/s consuming 3.7 mW and at 10 Gb/s consuming 5.1 mW, respectively. A peak efficiency of 0.46 mW/Gb/s is recorded in the low power mode. The design occupies 0.0115 mm2, including the on-chip coupling capacitance.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114182843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240433
C. Campbell
In this paper the non-uniform distributed power amplifier (NDPA) architecture is reviewed. Analysis of the structure highlights some of issues and limitations one encounters when utilizing this topology for the monolithic implementation of wideband power amplifiers. Existing techniques for mitigating these issues are then discussed along with published benchmarks for NDPA MMICs that demonstrate the approach.
{"title":"GaN non-uniform distributed power amplifier MMICs — The highs and lows (Invited)","authors":"C. Campbell","doi":"10.1109/CSICS.2017.8240433","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240433","url":null,"abstract":"In this paper the non-uniform distributed power amplifier (NDPA) architecture is reviewed. Analysis of the structure highlights some of issues and limitations one encounters when utilizing this topology for the monolithic implementation of wideband power amplifiers. Existing techniques for mitigating these issues are then discussed along with published benchmarks for NDPA MMICs that demonstrate the approach.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124239069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240459
F. Kharabi
This paper describes new features and versatility of a Verilog-A FET model for High-Efficiency and wideband applications, with examples in GaN technologies. It describes the flexibility of having the Internal output nodes available for design in exact wave-shaping for high-efficiency class amplifications and a more realistic CDS formulation that meets the needs of newer HEMT technologies with multiple field-plates both in RF and power electronics applications. Examples are given to demonstrate the utility of the 8-terminal model.
{"title":"HEMT model with internal nodes access and custom CDS function for amplifier design","authors":"F. Kharabi","doi":"10.1109/CSICS.2017.8240459","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240459","url":null,"abstract":"This paper describes new features and versatility of a Verilog-A FET model for High-Efficiency and wideband applications, with examples in GaN technologies. It describes the flexibility of having the Internal output nodes available for design in exact wave-shaping for high-efficiency class amplifications and a more realistic CDS formulation that meets the needs of newer HEMT technologies with multiple field-plates both in RF and power electronics applications. Examples are given to demonstrate the utility of the 8-terminal model.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240467
Lina Cao, C. Lo, H. Marchand, W. Johnson, P. Fay
A comparison of coplanar waveguides (CPWs) for MMIC applications fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported. In addition to the two substrate types, two fabrication process flows-one suitable for mesa-isolated MMICs and the other appropriate for MMIC flows incorporating implant isolation-were evaluated. The propagation and loss performance of the CPWs on the different substrate types was assessed from 100 MHz to 20 GHz. While the ohmic loss associated with the metal lines was comparable between the two substrate types, some differences in the dielectric loss were observed. For the GaN-on-Si substrates, the dielectric loss contributes ∼0.1 dB/mm to the line loss, while the GaN-on-SiC substrates show less than 0.01 dB/mm. To gauge the impact for circuits, X-band λ/8 open-circuited stubs (for matching) and quarter-wave short-circuited stubs (e.g. for bias) were designed and compared. The obtained reflection coefficients suggest that while GaN-on-Si CPWs have more loss, matching network performance can be expected to be within ∼0.3 dB of those for GaN-on-SiC. From this study, it appears that GaN-on-Si substrates have interconnect performance for MMICs that is nearly as good as those on GaN-on-SiC substrates, demonstrating excellent potential for high-performance GaN MMICs.
{"title":"Coplanar waveguide performance comparison of GaN-on-Si and GaN-on-SiC substrates","authors":"Lina Cao, C. Lo, H. Marchand, W. Johnson, P. Fay","doi":"10.1109/CSICS.2017.8240467","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240467","url":null,"abstract":"A comparison of coplanar waveguides (CPWs) for MMIC applications fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported. In addition to the two substrate types, two fabrication process flows-one suitable for mesa-isolated MMICs and the other appropriate for MMIC flows incorporating implant isolation-were evaluated. The propagation and loss performance of the CPWs on the different substrate types was assessed from 100 MHz to 20 GHz. While the ohmic loss associated with the metal lines was comparable between the two substrate types, some differences in the dielectric loss were observed. For the GaN-on-Si substrates, the dielectric loss contributes ∼0.1 dB/mm to the line loss, while the GaN-on-SiC substrates show less than 0.01 dB/mm. To gauge the impact for circuits, X-band λ/8 open-circuited stubs (for matching) and quarter-wave short-circuited stubs (e.g. for bias) were designed and compared. The obtained reflection coefficients suggest that while GaN-on-Si CPWs have more loss, matching network performance can be expected to be within ∼0.3 dB of those for GaN-on-SiC. From this study, it appears that GaN-on-Si substrates have interconnect performance for MMICs that is nearly as good as those on GaN-on-SiC substrates, demonstrating excellent potential for high-performance GaN MMICs.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132257677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240425
D. Gustafsson, A. Leidenhed, K. Andersson
This paper reports on a packaged GaN MMIC Doherty Power Amplifier operating in the 7 GHz band. The power amplifier exhibits a small-signal gain of 18 dB from 7.0 GHz to 8.0 GHz and the saturated output power is more than 42 dBm across the same frequency band. Measured power added efficiency is better than 24% in 10 dB back-off from saturation. The linearity of the amplifier is excellent — achieving a NMSE of −38 dB without DpD and −52 dB with DPD. The power amplifier was implemented in a 0.25 um gate-length GaN-HEMT technology and packaged in a QFN 6 mm × 6 mm package using plastic overmold. The dimensions of the MMIC were 4.38 mm × 4.38 mm. These results represent current state-of-the-art in high efficiency power amplifiers for wireless backhaul applications.
{"title":"Packaged 7 GHz GaN MMIC doherty power amplifier","authors":"D. Gustafsson, A. Leidenhed, K. Andersson","doi":"10.1109/CSICS.2017.8240425","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240425","url":null,"abstract":"This paper reports on a packaged GaN MMIC Doherty Power Amplifier operating in the 7 GHz band. The power amplifier exhibits a small-signal gain of 18 dB from 7.0 GHz to 8.0 GHz and the saturated output power is more than 42 dBm across the same frequency band. Measured power added efficiency is better than 24% in 10 dB back-off from saturation. The linearity of the amplifier is excellent — achieving a NMSE of −38 dB without DpD and −52 dB with DPD. The power amplifier was implemented in a 0.25 um gate-length GaN-HEMT technology and packaged in a QFN 6 mm × 6 mm package using plastic overmold. The dimensions of the MMIC were 4.38 mm × 4.38 mm. These results represent current state-of-the-art in high efficiency power amplifiers for wireless backhaul applications.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128833240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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