Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240432
S. Takagi, M. Takenaka
CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V/Ge channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to form these new materials on Si is a common key issue. The wafer bonding technologies are utilized for this purpose. We demonstrate the operation and the electrical characteristics of a variety of III-V/Ge MOSFETs and TFETs including the hetero-structures.
{"title":"Ultra-low power MOSFET and tunneling FET technologies using III-V and Ge","authors":"S. Takagi, M. Takenaka","doi":"10.1109/CSICS.2017.8240432","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240432","url":null,"abstract":"CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V/Ge channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to form these new materials on Si is a common key issue. The wafer bonding technologies are utilized for this purpose. We demonstrate the operation and the electrical characteristics of a variety of III-V/Ge MOSFETs and TFETs including the hetero-structures.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129338513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240421
J. Pomeroy, Roland B. Simon, C. Middleton, Martin Kuball
Screening for optimal thermal performance of semiconductor wafers was developed based on a noninvasive thermo-reflectance technique. Temperature changes of the wafer surface, induced by a nanosecond pulsed laser absorbed into the near surface region, allows to extract critical thermal parameters such as thermal boundary resistances between epilayers or epilayers and substrate. These affect channel temperature in devices (RF, power, optoelectronics) once the wafer is fully processed. This is illustrated on GaN-on-diamond wafers which are presently being developed for ultra-high power RF applications.
{"title":"Transient thermoreflectance wafer mapping for process control and development: GaN-on-Diamond","authors":"J. Pomeroy, Roland B. Simon, C. Middleton, Martin Kuball","doi":"10.1109/CSICS.2017.8240421","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240421","url":null,"abstract":"Screening for optimal thermal performance of semiconductor wafers was developed based on a noninvasive thermo-reflectance technique. Temperature changes of the wafer surface, induced by a nanosecond pulsed laser absorbed into the near surface region, allows to extract critical thermal parameters such as thermal boundary resistances between epilayers or epilayers and substrate. These affect channel temperature in devices (RF, power, optoelectronics) once the wafer is fully processed. This is illustrated on GaN-on-diamond wafers which are presently being developed for ultra-high power RF applications.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"3 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121297163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240469
Z. Hu, G. Sarris, C. De Martino, M. Spirito, E. McCune
A two-stage D-band differential cascode power amplifier is presented, integrated using the IHP 0.13 pm SiGe BiCMOS technology. A compact layout of the cascode stage is proposed to minimize the parasitics contributing to potential instability, achieving 13 dB of gain/stage while operating at 46% of fT, using stage peaking. The PA is analyzed using Booth chart techniques showing that the amplifier can operate with greatly reduced supply and bias while maintaining linearity dynamic range. The fabricated prototype achieves P1dB, Psat, and IIP2 of 0.2 dBm, 6.2 dBm, and 25.5 dBm respectively with 26 dB overall gain. The AM-PM conversion of the PA is experimentally characterized showing phase fluctuations lower than ±1.5° in a 10 GHz bandwidth. Furthermore, it exhibits 1 dB deviation of power gain over 40 dB input power range with 0.4 V supply variation.
{"title":"Design and linearity analysis of a D-band power amplifier in 0.13 μm SiGe BiCMOS technology","authors":"Z. Hu, G. Sarris, C. De Martino, M. Spirito, E. McCune","doi":"10.1109/CSICS.2017.8240469","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240469","url":null,"abstract":"A two-stage D-band differential cascode power amplifier is presented, integrated using the IHP 0.13 pm SiGe BiCMOS technology. A compact layout of the cascode stage is proposed to minimize the parasitics contributing to potential instability, achieving 13 dB of gain/stage while operating at 46% of fT, using stage peaking. The PA is analyzed using Booth chart techniques showing that the amplifier can operate with greatly reduced supply and bias while maintaining linearity dynamic range. The fabricated prototype achieves P1dB, Psat, and IIP2 of 0.2 dBm, 6.2 dBm, and 25.5 dBm respectively with 26 dB overall gain. The AM-PM conversion of the PA is experimentally characterized showing phase fluctuations lower than ±1.5° in a 10 GHz bandwidth. Furthermore, it exhibits 1 dB deviation of power gain over 40 dB input power range with 0.4 V supply variation.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134594306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240448
Lung-I Chou, Li-Yi Peng, Hsiang-Chun Wang, H. Chiu, How-Ting Wang, Dong-Long Chiang, J. Chyi
In this letter, a microwave annealing (MWA) method for Ohmic contact applied to InAlN/GaN high electron mobility transistor (HEMT) is the first time. The feature of MWA method is low operating temperature (450°C∼550°C). By using this technique, MWA-HEMT can achieve a low Ohmic contact resistance and smoother Ohmic contact surface than traditional rapid thermal annealing (RTA). The situation of Indium diffusion and device gate leakage current has been improved by this technique. Moreover, the reliability and RF performance of MWA-HEMT has a better result than RTA-HEMT.
{"title":"InAlN/GaN HEMT using microwave annealing for low temperature ohmic contact formation","authors":"Lung-I Chou, Li-Yi Peng, Hsiang-Chun Wang, H. Chiu, How-Ting Wang, Dong-Long Chiang, J. Chyi","doi":"10.1109/CSICS.2017.8240448","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240448","url":null,"abstract":"In this letter, a microwave annealing (MWA) method for Ohmic contact applied to InAlN/GaN high electron mobility transistor (HEMT) is the first time. The feature of MWA method is low operating temperature (450°C∼550°C). By using this technique, MWA-HEMT can achieve a low Ohmic contact resistance and smoother Ohmic contact surface than traditional rapid thermal annealing (RTA). The situation of Indium diffusion and device gate leakage current has been improved by this technique. Moreover, the reliability and RF performance of MWA-HEMT has a better result than RTA-HEMT.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122126102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240426
K. Kikuchi, K. Tsuzuki, S. Kamei, S. Yamanaka, S. Asakawa, T. Itoh, Y. Nasu, K. Takeda, K. Honda, Y. Kawamura, M. Jizodo, Masayuki Takahashi, M. Usui, H. Mawatari, T. Saida
We actualized a silicon photonics (SiPh)-based coherent optical subassembly (COSA) with a compact and low-height package for the next-generation transceiver form factors. We integrated optical functions required for transmitting and receiving digital coherent optical signals into a single SiPh chip. The COSA is applicable to 100-Gbps dual-polarization quadrature phase shift keying and 200Gbps dual polarization 16-quadrature amplitude modulation transmissions.
{"title":"Silicon-photonics-based coherent optical subassembly (COSA) for ultra-compact coherent transceiver","authors":"K. Kikuchi, K. Tsuzuki, S. Kamei, S. Yamanaka, S. Asakawa, T. Itoh, Y. Nasu, K. Takeda, K. Honda, Y. Kawamura, M. Jizodo, Masayuki Takahashi, M. Usui, H. Mawatari, T. Saida","doi":"10.1109/CSICS.2017.8240426","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240426","url":null,"abstract":"We actualized a silicon photonics (SiPh)-based coherent optical subassembly (COSA) with a compact and low-height package for the next-generation transceiver form factors. We integrated optical functions required for transmitting and receiving digital coherent optical signals into a single SiPh chip. The COSA is applicable to 100-Gbps dual-polarization quadrature phase shift keying and 200Gbps dual polarization 16-quadrature amplitude modulation transmissions.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129952753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240435
W. Steyaert, P. Reynaert
Scaling in CMOS has increased the attainable operational frequencies, while greatly increasing the transistor's parasitic modeling complexity. Additionally, the performance of the ever-smaller on-chip passives for mm-wave and THz circuits is being degraded by numerous process requirements and limitations, such as high densities of dummy metals. This work discusses the main transistor layout trade-offs for high-frequency performance in both 40nm and 28nm bulk CMOS. The impact of dummy metals on a single-turn on-chip inductor for mm-wave/THz frequencies is presented, which shows that low dummy metal densities around critical high-frequency passives are essential to minimize degradation in performance.
{"title":"Layout optimizations for THz integrated circuit design in bulk nanometer CMOS","authors":"W. Steyaert, P. Reynaert","doi":"10.1109/CSICS.2017.8240435","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240435","url":null,"abstract":"Scaling in CMOS has increased the attainable operational frequencies, while greatly increasing the transistor's parasitic modeling complexity. Additionally, the performance of the ever-smaller on-chip passives for mm-wave and THz circuits is being degraded by numerous process requirements and limitations, such as high densities of dummy metals. This work discusses the main transistor layout trade-offs for high-frequency performance in both 40nm and 28nm bulk CMOS. The impact of dummy metals on a single-turn on-chip inductor for mm-wave/THz frequencies is presented, which shows that low dummy metal densities around critical high-frequency passives are essential to minimize degradation in performance.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240424
Kevin W. Kobayashi, Charles Campbell, Cathy Lee, Justin Gallagher, John Shust, Andrew Botelho
This paper reports on a frequency agile GaN LNA MMIC that can be reconfigured for both S- and X-band extending operation over multiple octaves of frequency. The LNA is based on a 0.15um GaN HEMT technology and utilizes GaN FET switches to tune the LNA for 3–3.5 GHz Sband and 9–11 GHz X-band operation. Switch tuned for Sband, the amplifier achieves 15 dB of gain, NF ranging from 0.9–1.3 dB, an input return-loss better than 10 dB, and an IP3 of 29.2–32.8 dBm. Switch tuned for X-band, the amplifier achieves a gain of 13.5–14.5 dB, a NF ranging from 1.4–2.2 dB, an input return-loss from 11–12 dB, and an IP3 of 29.534.5 dBm. To the authors' knowledge, this work is the first band reconfigurable GaN LNA reported up to X-band frequencies. The LNA demonstrates comparable or better combined NF & input return-loss performance than previous single-band optimized GaN LNAs reported at X-band.
{"title":"A reconfigurable S-/X-band GaN cascode LNA MMIC","authors":"Kevin W. Kobayashi, Charles Campbell, Cathy Lee, Justin Gallagher, John Shust, Andrew Botelho","doi":"10.1109/CSICS.2017.8240424","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240424","url":null,"abstract":"This paper reports on a frequency agile GaN LNA MMIC that can be reconfigured for both S- and X-band extending operation over multiple octaves of frequency. The LNA is based on a 0.15um GaN HEMT technology and utilizes GaN FET switches to tune the LNA for 3–3.5 GHz Sband and 9–11 GHz X-band operation. Switch tuned for Sband, the amplifier achieves 15 dB of gain, NF ranging from 0.9–1.3 dB, an input return-loss better than 10 dB, and an IP3 of 29.2–32.8 dBm. Switch tuned for X-band, the amplifier achieves a gain of 13.5–14.5 dB, a NF ranging from 1.4–2.2 dB, an input return-loss from 11–12 dB, and an IP3 of 29.534.5 dBm. To the authors' knowledge, this work is the first band reconfigurable GaN LNA reported up to X-band frequencies. The LNA demonstrates comparable or better combined NF & input return-loss performance than previous single-band optimized GaN LNAs reported at X-band.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117319734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240460
W. Deal, K. Leong, A. Zamora, B. Gorospe, K. Nguyen, X. Mei
This paper reports on a 660 GHz transmitter using InP HEMT technology. The transmitter features a x18 multiplier chain, sub-harmonic mixer, and a power amplifier at the output. Tradeoffs in the upconverter topology are discussed, including transmit noise power, RF filtering, and phase noise. With SSPA at the output, this up-converter achieves the highest reported power to date at this frequency. This significantly advances the technology required for submillimeter wave communication.
{"title":"A 660 GHz up-converter for THz communications","authors":"W. Deal, K. Leong, A. Zamora, B. Gorospe, K. Nguyen, X. Mei","doi":"10.1109/CSICS.2017.8240460","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240460","url":null,"abstract":"This paper reports on a 660 GHz transmitter using InP HEMT technology. The transmitter features a x18 multiplier chain, sub-harmonic mixer, and a power amplifier at the output. Tradeoffs in the upconverter topology are discussed, including transmit noise power, RF filtering, and phase noise. With SSPA at the output, this up-converter achieves the highest reported power to date at this frequency. This significantly advances the technology required for submillimeter wave communication.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121271936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240427
Chung-hsu Chen, R. Sadler, David Wang, Daniel Hou, Yuefei Yang, W. Yau, Shiguang Wang, Mo Wu, Tingyi Wu, Rex Chen, Benjamin Ou
To model drain IV characteristics, the temperature dependence is important for GaN HEMT. We show that the time dependence should also be included in the modeling approach. In this paper, we use the trap information obtained from current transient spectroscopy (CTS) to create a 3D plot of Ids-Vds-time(I-V-t). This gives a more realistic description for time-domain pulsed IV behavior. The controversial question of whether the pulsed IV/RF is a trapping effect or a thermal effect is analyzed. The Poole-Frenkel emission-based time-dependent trapping model is proposed to describe the GaN HEMT memory effects (kink effect and knee walkout). To our knowledge, this is the first model offered to describe the “soft” (or degraded) knee region of the GaN HEMT IV curves.
{"title":"The interplay of thermal, time and Poole-Frenkel emission on the trap-based physical modeling of GaN HEMT drain characteristics","authors":"Chung-hsu Chen, R. Sadler, David Wang, Daniel Hou, Yuefei Yang, W. Yau, Shiguang Wang, Mo Wu, Tingyi Wu, Rex Chen, Benjamin Ou","doi":"10.1109/CSICS.2017.8240427","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240427","url":null,"abstract":"To model drain IV characteristics, the temperature dependence is important for GaN HEMT. We show that the time dependence should also be included in the modeling approach. In this paper, we use the trap information obtained from current transient spectroscopy (CTS) to create a 3D plot of Ids-Vds-time(I-V-t). This gives a more realistic description for time-domain pulsed IV behavior. The controversial question of whether the pulsed IV/RF is a trapping effect or a thermal effect is analyzed. The Poole-Frenkel emission-based time-dependent trapping model is proposed to describe the GaN HEMT memory effects (kink effect and knee walkout). To our knowledge, this is the first model offered to describe the “soft” (or degraded) knee region of the GaN HEMT IV curves.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117293223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240457
E. Preisler, K. Moen, J. Zheng, P. Hurwitz, S. Chaudhry, M. Racanelli
Over the past decade, SiGe BiCMOS processes have become a mainstay in the Front-End-Module (FEM) of commercial radio products. SiGe BiCMOS processes offer an excellent compromise between the low cost of commodity CMOS and the high performance of III-V based technologies. This allows them to address many of the difficult specification challenges of FEM components in cellular phones and other complex radio systems at a cost level that is acceptable for very high volume products. In this paper several examples of applications of SiGe BiCMOS processes in FEMs are given, including power amplifiers, low-noise amplifiers, RF switches and combinations thereof. Further, the utility of SiGe BiCMOS to address emerging commercial applications at higher frequencies is discussed.
{"title":"SiGe BiCMOS processes for commercial RF front-end-module applications","authors":"E. Preisler, K. Moen, J. Zheng, P. Hurwitz, S. Chaudhry, M. Racanelli","doi":"10.1109/CSICS.2017.8240457","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240457","url":null,"abstract":"Over the past decade, SiGe BiCMOS processes have become a mainstay in the Front-End-Module (FEM) of commercial radio products. SiGe BiCMOS processes offer an excellent compromise between the low cost of commodity CMOS and the high performance of III-V based technologies. This allows them to address many of the difficult specification challenges of FEM components in cellular phones and other complex radio systems at a cost level that is acceptable for very high volume products. In this paper several examples of applications of SiGe BiCMOS processes in FEMs are given, including power amplifiers, low-noise amplifiers, RF switches and combinations thereof. Further, the utility of SiGe BiCMOS to address emerging commercial applications at higher frequencies is discussed.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127061554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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