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2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)最新文献

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Design of monolithic silicon photonics at 25 Gb/s 25gb /s单片硅光子学设计
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240453
J. Orcutt
Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here, I examine 25 Gb/s applications in commercially available process technology with a focus on receiver sub-system optimization.
单片CMOS光子学通过简化封装、设计和测试来最小化收发器的总成本。在这里,我研究了商用过程技术中的25gb /s应用程序,重点是接收器子系统优化。
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引用次数: 4
A 28 GHz 480 elements digital AAS using GaN HEMT amplifiers with 68 dBm EIRP for 5G long-range base station applications 采用GaN HEMT放大器和68 dBm EIRP的28ghz 480元数字AAS,用于5G远程基站应用
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240471
T. Kuwabara, N. Tawa, Yuichi Tone, T. Kaneko
This paper reports the design, development and performance of a 28 GHz 480 elements digital Active Antenna System (AAS) prototype for 5G long-range applications. AAS accommodates 32 channels of 0.15 um GaN HEMT power amplifier chains. The antenna array prototype consists of full digitally controlled 32 streams of 15 elements sub-arrays. They can deliver a total conductive power of 41 dBm and Average Effective Isotropically Radiated Power (EIRP) of 68 dBm for the macro-cell coverage at 28 GHz. The prototype also features newly proposed high density heat spreading structure dissipating around 450 W in an 11 liter compact enclosure. The paper proposes and demonstrates one of direction of the high power GaN HEMT application to the millimeter-wave 5G long-range base stations.
本文报道了用于5G远程应用的28 GHz 480元数字有源天线系统(AAS)原型的设计、开发和性能。AAS可容纳32个通道的0.15 um GaN HEMT功率放大器链。天线阵原型由全数字控制的32流15元子阵组成。它们可以提供41 dBm的总导电功率和68 dBm的平均有效各向同性辐射功率(EIRP),用于28 GHz的宏蜂窝覆盖。原型车还采用了新提出的高密度散热结构,在一个11升的紧凑外壳中耗散约450瓦。提出并论证了高功率GaN HEMT在毫米波5G远程基站中的应用方向之一。
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引用次数: 20
A fully decoupled LC tank VCO based 16 to 19 GHz PLL in 130nm SiGe BiCMOS achieving −131dBc/Hz phase noise at 10MHz offset 基于16至19 GHz锁相环的完全解耦LC槽压控振荡器,采用130nm SiGe BiCMOS,在10MHz偏移时实现- 131dBc/Hz相位噪声
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240451
B. Sadhu, S. Reynolds
This paper describes a technique for reducing oscillator phase noise through a circuit topology that decouples the LC tank from the active devices, achieving a higher amplitude of oscillation not limited by the active device breakdown voltage. This fully decoupled LC tank topology also reduces noise injection into the tank, which, coupled with the higher tank swing, results in low phase noise operation. As proof of concept, a VCO operating at 16 to 19 GHz is implemented in the IBM 130nm SiGe BiCMOS technology fT/fmax of 200/280 GHz). The VCO achieves a phase noise of −131dBc/Hz at a 10MHz offset from the carrier.
本文描述了一种通过电路拓扑降低振荡器相位噪声的技术,该电路拓扑将LC槽与有源器件解耦,从而实现不受有源器件击穿电压限制的更高幅度的振荡。这种完全解耦的LC储罐拓扑结构还减少了注入储罐的噪声,再加上储罐的摆动幅度较大,从而实现了低相位噪声的运行。作为概念验证,在IBM 130纳米SiGe BiCMOS技术(fT/fmax为200/280 GHz)中实现了工作在16至19 GHz的VCO。在距离载波10MHz的偏移处,VCO实现了−131dBc/Hz的相位噪声。
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引用次数: 3
IC calibration kits and de-embedding techniques for sub-mm-wave device characterization 亚毫米波器件特性的集成电路校准套件和去嵌入技术
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240449
M. Spirito, L. Galatro
In this paper, we describe a design and characterization flow to accurately extract the performance of high-speed devices, integrated in Silicon-based technologies. An EM-based technique to accurately derive the characteristic impedance of transmission lines embedded in lossy and multilayered substrates, is described. Further, this technique is employed to characterize lower metal levels transmission lines (i.e., M1) enabling to employ a direct calibration/de-embedding approach to properly define the measurement reference plane at the intrinsic device terminals, though a TRL based technique. Finally, the proposed calibration/de-embedding approach is employed to benchmark the performance of a SiGe HBT versus the HiCUM L2 predictions.
在本文中,我们描述了一个设计和表征流程,以准确地提取高速器件的性能,集成在硅基技术中。描述了一种基于电磁的技术,可以精确地推导出嵌入有损耗和多层衬底中的传输线的特性阻抗。此外,该技术还用于表征较低金属水平的传输线(即M1),从而能够采用直接校准/去嵌入方法,通过基于TRL的技术来正确定义固有设备终端的测量参考平面。最后,采用所提出的校准/去嵌入方法对SiGe HBT与HiCUM L2预测的性能进行基准测试。
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引用次数: 0
39GHz GaN front end MMIC for 5G applications 用于5G应用的39GHz GaN前端MMIC
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240473
Bumjin Kim, Vivian Zhi-Qi Li
This paper presents the design and the measured results of a GaN-based T/R MMIC suitable for millimeter-wave 5G applications. The design successfully integrated a PA, an LNA, and a T/R switch in one IC. At 39GHz, the transmit path achieved an average output power of 26dBm with 9% PAE and −30dBc ACPR under a 64QAM OFDM signal. The receive path achieved 16dB gain with 4dB NF. The fabricated MMIC is packaged in a low cost surface mount package in both single and dual channel versions to support multi-element phased array applications.
本文介绍了一种适用于毫米波5G应用的基于gan的T/R MMIC的设计和测量结果。该设计成功地将PA、LNA和收发开关集成在一个IC中。在39GHz的发射路径下,在64QAM OFDM信号下,平均输出功率为26dBm, PAE为9%,ACPR为- 30dBc。接收路径增益为16dB, NF为4dB。制造的MMIC封装在低成本的表面贴装封装中,有单通道和双通道版本,以支持多元素相控阵应用。
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引用次数: 14
GaN device-circuit interaction on RF linear power amplifier designed using the MVSG compact model 采用MVSG紧凑模型设计射频线性功率放大器的GaN器件-电路相互作用
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240430
Pilsoon Choi, U. Radhakrishna, D. Antoniadis, E. Fitzgerald
This work presents a GaN RF power amplifier with a common-source-common-gate (CS-CG) linearization technique, demonstrating device-circuit interactions using the physics-based MIT Virtual Source GaNFET (MVSG) model. A few device parameters are carefully chosen to investigate their effects on the circuit performance, as well as to suggest how to fabricate or choose a better GaN device for RF power amplifier design. The designed amplifier achieves 11dB gain at 6GHz, 51% drain efficiency at 35.3dBm Psat, and 39dBm output IP3 with 10V supply voltage. In this work, it is shown that the physical device parameters related to DC, RF, and thermal conditions affect the above circuit performance, especially linearity, and could be used to link the circuit performance to specific device level physics.
本研究提出了一种具有共源-共门(CS-CG)线性化技术的GaN射频功率放大器,使用基于物理的MIT虚拟源GaNFET (MVSG)模型演示了器件-电路相互作用。仔细选择了一些器件参数来研究它们对电路性能的影响,以及建议如何制造或选择更好的GaN器件用于射频功率放大器设计。该放大器在6GHz时实现11dB增益,在35.3dBm Psat时实现51%漏极效率,在10V电源电压下实现39dBm输出IP3。在这项工作中,研究表明,与直流、射频和热条件相关的物理器件参数会影响上述电路性能,特别是线性,并可用于将电路性能与特定器件级物理联系起来。
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引用次数: 2
ADC-based receiver designs: Challenges and opportunities 基于adc的接收机设计:挑战与机遇
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240461
A. Sheikholeslami
This paper reviews a set of architecture and circuit techniques that have enabled data rates beyond 10Gb/s, and explores a range of design challenges and considerations as we move to higher data rates. In particular, we review ADC-based designs and their challenges and tradeoffs, including ADC resolution, oversampling ratio, and power consumption.
本文回顾了一组使数据速率超过10Gb/s的架构和电路技术,并探讨了我们向更高数据速率移动时的一系列设计挑战和考虑因素。我们特别回顾了基于ADC的设计及其挑战和权衡,包括ADC分辨率、过采样率和功耗。
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引用次数: 1
MMICs for next generation radar 用于下一代雷达的mmic
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240442
A. Darwish, Ken Mcknight, J. Penn, E. Viveiros, A. Hedden, H. A. Hung
The rapid progress towards 5G wireless systems is accelerating the development of mm-wave semiconductor processes, broadband circuits, and system technologies. Similarly, next-generation radar is being expanded and redefined. Legacy radar systems are nearing the end of their life cycle and systems developers are aiming to upgrade their capability while reducing cost, size, and weight. Radar systems have requirements that result in technical circuit design challenges including high power, broadband, and low distortion. This paper focuses on MMIC design challenges specific to the design of next-generation radars that will operate in a crowded wireless environment, allow spectrum sharing, and dynamic frequency selection. Simulated and measured data are presented.
5G无线系统的快速发展正在加速毫米波半导体工艺、宽带电路和系统技术的发展。同样,下一代雷达正在被扩展和重新定义。传统雷达系统正接近其生命周期的终点,系统开发商的目标是在降低成本、尺寸和重量的同时升级其能力。雷达系统的要求导致了技术电路设计的挑战,包括高功率、宽带和低失真。本文重点介绍了下一代雷达设计中的MMIC设计挑战,这些雷达将在拥挤的无线环境中运行,允许频谱共享和动态频率选择。给出了仿真和实测数据。
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引用次数: 0
Fully differential high input power handling ultra-wideband low noise amplifier for MIMO radar application 用于MIMO雷达应用的全差分高输入功率处理超宽带低噪声放大器
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240428
M. Sakalas, P. Sakalas, N. Joram, F. Ellinger
A fully differential, high input power handling, ultra-wideband, variable gain low noise amplifier MMIC for a monostatic MIMO radar was designed in a 130 nm SiGe BiCMOS Technology. The amplifier features an extensively high RF input power survivability, high power handling, ultra-wideband operation of 0.1–50 GHz and a linearly variable gain with 12 dB tuning range. The measured differential mode noise figure is below 5.5 dB within the bandwidth, whereas the 1-dB compression point is reached at −7.8 to −2.6 dBm input power levels at nominal gain operation. The maximum DC power consumption is 70 mW and the total chip area is 0.76 mm2.
采用130 nm SiGe BiCMOS技术,设计了一种用于单站MIMO雷达的全差分、高输入功率处理、超宽带、可变增益低噪声放大器MMIC。该放大器具有极高的射频输入功率生存能力、高功率处理能力、0.1-50 GHz的超宽带工作以及12 dB调谐范围的线性可变增益。在带宽范围内,测量的差模噪声系数低于5.5 dB,而在标称增益操作下,在- 7.8至- 2.6 dBm输入功率水平下达到1 dB压缩点。最大直流功耗为70mw,总芯片面积为0.76 mm2。
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引用次数: 8
DC-62 GHz 4-phase 25% duty cycle quadrature clock generator DC-62 GHz 4相25%占空比正交时钟发生器
Pub Date : 2017-10-01 DOI: 10.1109/CSICS.2017.8240468
Naftali Weiss, S. Shopov, P. Schvan, P. Chevalier, A. Cathelin, S. Voinigescu
A process-, temperature-and supply-insensitive DC-to-62GHz 4-phase quadrature generator for clock signals with 25% duty cycle was manufactured in a production 55-nm SiGe BiCMOS technology. The purely digital circuit is based on a 2.5 V bipolar-CML static divider, AND gates and inverter stages, and operates with input signals from DC to 124 GHz while consuming 178 mW. Measurements were conducted with 63-GHz and 100-GHz bandwidth real-time oscilloscopes. The measured self-oscillation frequency of the static divider in the generator was 98.8 GHz, compared to 93 GHz in simulation. The measured output signals remained in quadrature up to 62 GHz. The measured duty cycle is 25–26% up to 30 GHz and increases up to 33% at 50 GHz, beyond which measurements are impacted by the limited bandwidth of the oscilloscope. The simulated duty cycle was lower than 28% up to 62 GHz.
采用55纳米SiGe BiCMOS技术生产了一款对工艺、温度和电源不敏感的dc - 62ghz 4相正交发生器,用于25%占空比的时钟信号。纯数字电路基于2.5 V双极- cml静态分频器、与门和逆变级,输入信号从DC到124 GHz,功耗为178 mW。测量用63 ghz和100 ghz带宽的实时示波器进行。静态分频器的自振荡频率为98.8 GHz,仿真结果为93 GHz。测量到的输出信号保持正交到62 GHz。测量的占空比在30 GHz时为25-26%,在50 GHz时增加到33%,超过这一范围的测量会受到示波器有限带宽的影响。模拟的占空比在62 GHz范围内低于28%。
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引用次数: 9
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2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)
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