Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240477
M. LaRue, B. Dupaix, S. Rashid, T. Barton, T. James, W. Gouty, P. Watson, T. Quach, W. Khalil
A fully-integrated transmitter is presented in DARPA's DAHI process technology, featuring heterogeneous integration of 45nm SOI CMOS and 0.2pm GaN technologies. This transmitter is capable of transmitting SOQPSK-TG telemetry waveforms across 2–5 GHz with a peak transmitter power efficiency of 41.32% and peak output power of 32.93 dBm. A reconfigurable CMOS phase modulator is implemented to provide 6-bit phase resolution across the entire output frequency range, and a wide-swing CMOS buffer was designed to drive the GaN power amplifier. The GaN PA features a three-stage design, featuring a differential CML buffer, push-pull inverting buffer, and a class-E switch-mode power amplifier to efficiently amplify the signal. To the authors' knowledge, this is the first fully-integrated transmitter combining CMOS and GaN technology demonstrated in literature.
{"title":"A fully-integrated S/C band transmitter in 45nm CMOS/ 0.2gm GaN heterogeneous technology","authors":"M. LaRue, B. Dupaix, S. Rashid, T. Barton, T. James, W. Gouty, P. Watson, T. Quach, W. Khalil","doi":"10.1109/CSICS.2017.8240477","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240477","url":null,"abstract":"A fully-integrated transmitter is presented in DARPA's DAHI process technology, featuring heterogeneous integration of 45nm SOI CMOS and 0.2pm GaN technologies. This transmitter is capable of transmitting SOQPSK-TG telemetry waveforms across 2–5 GHz with a peak transmitter power efficiency of 41.32% and peak output power of 32.93 dBm. A reconfigurable CMOS phase modulator is implemented to provide 6-bit phase resolution across the entire output frequency range, and a wide-swing CMOS buffer was designed to drive the GaN power amplifier. The GaN PA features a three-stage design, featuring a differential CML buffer, push-pull inverting buffer, and a class-E switch-mode power amplifier to efficiently amplify the signal. To the authors' knowledge, this is the first fully-integrated transmitter combining CMOS and GaN technology demonstrated in literature.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133388421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240422
Y. Yamaguchi, J. Kamioka, M. Hangai, S. Shinjo, K. Yamanaka
This paper reports a 20 W Ka-band GaN high power MMIC (Monolithic Microwave Integrated Circuit) amplifier under continuous wave (CW) operation. The one-finger large signal models were made to take account of both the phase difference of RF gate voltage at a gate feeder and thermal effect. By using this model, the gate pitch length of unit cell transistor was optimally designed to obtain maximum output power as MMIC amplifier under CW operation. As a result, 21.7W output power under CW operation was successfully achieved with power added efficiency (PAE) of 19.8% at Ka-band by a single-ended MMIC. To the best of authors' knowledge, this output power is state-of-the-art for GaN MMIC amplifiers under CW operation at Ka-band.
本文报道了一种连续波工作下的20 W ka波段GaN大功率单片微波集成电路放大器。建立了考虑栅极馈线处射频栅极电压相位差和热效应的单指大信号模型。利用该模型，优化设计了单元晶体管的栅极间距长度，使其在连续波工作下作为MMIC放大器获得最大输出功率。结果表明，在连续波工作下，单端MMIC的输出功率为21.7W, ka波段的功率附加效率(PAE)为19.8%。据作者所知，这种输出功率对于ka波段连续波工作的GaN MMIC放大器来说是最先进的。
{"title":"A CW 20W Ka-band GaN high power MMIC amplifier with a gate pitch designed by using one-finger large signal models","authors":"Y. Yamaguchi, J. Kamioka, M. Hangai, S. Shinjo, K. Yamanaka","doi":"10.1109/CSICS.2017.8240422","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240422","url":null,"abstract":"This paper reports a 20 W Ka-band GaN high power MMIC (Monolithic Microwave Integrated Circuit) amplifier under continuous wave (CW) operation. The one-finger large signal models were made to take account of both the phase difference of RF gate voltage at a gate feeder and thermal effect. By using this model, the gate pitch length of unit cell transistor was optimally designed to obtain maximum output power as MMIC amplifier under CW operation. As a result, 21.7W output power under CW operation was successfully achieved with power added efficiency (PAE) of 19.8% at Ka-band by a single-ended MMIC. To the best of authors' knowledge, this output power is state-of-the-art for GaN MMIC amplifiers under CW operation at Ka-band.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130880124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240470
K. Patel, H. Golestaneh, S. Boumaiza
This paper proposes a design methodology based off the novel concept of current contours to insure proper current profiles for the main and peaking transistors needed to satisfy the load modulation conditions in a Doherty power amplifier over a wide frequency range. Utilizing this technique allows the construction of input matching networks that maximize the efficiency enhancement and linearity of the DPA. As a proof-of-concept, a 12 W DPA was designed. From 2.7 GHz to 4.7 GHz, continuous wave measurements have shown efficiency levels of greater than 37 % at 6 dB output power back-off and peak power. A gain of at least 8 db was shown with output power ranging from 40.7 dBm ±1 dB. Under an 80 MHz carrier aggregated signal, modulated signal results showed good linearizability with an ACLR of −48 dBc/Hz after digital pre-distortion.
{"title":"Current contours based IMN design methodology for broadband GaN Doherty power amplifiers","authors":"K. Patel, H. Golestaneh, S. Boumaiza","doi":"10.1109/CSICS.2017.8240470","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240470","url":null,"abstract":"This paper proposes a design methodology based off the novel concept of current contours to insure proper current profiles for the main and peaking transistors needed to satisfy the load modulation conditions in a Doherty power amplifier over a wide frequency range. Utilizing this technique allows the construction of input matching networks that maximize the efficiency enhancement and linearity of the DPA. As a proof-of-concept, a 12 W DPA was designed. From 2.7 GHz to 4.7 GHz, continuous wave measurements have shown efficiency levels of greater than 37 % at 6 dB output power back-off and peak power. A gain of at least 8 db was shown with output power ranging from 40.7 dBm ±1 dB. Under an 80 MHz carrier aggregated signal, modulated signal results showed good linearizability with an ACLR of −48 dBc/Hz after digital pre-distortion.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240445
S. Bhagavatheeswaran, T. Cummings, Eric Tangen, M. Heins, R. Chan, C. Steinbeiser
This paper describes the implementation of a state-of-the art 56Gb/s single-channel linear transimpedance amplifier (TIA) integrated circuit for PAM-4/NRZ/DMT modulation formats used in data center interconnects (DCI) and base station front haul applications. Fabricated in 130nm SiGe BiCMOS process, the TIA has a single-ended input, differential output configuration, with nominal maximum DC transimpedance gain of ∼5.8 kQ (75 dB), gain dynamic range of 28 dB, average input referred noise (IRN) of 14.9 pA/VHz, typical bandwidth of 38 GHz across the entire gain dynamic range, Total Harmonic Distortion (THD) of 2% for output of 500mVppd, adjustable output voltage swing up to 1Vppd, all operated with typical supply of 3.3 V. At 2.8 V supply, bandwidth of 34 GHz has been achieved. Performance has been measured from −5C to 95C. The TIA has Receive Signal Strength Indicator (RSSI) for measuring the input signal strength, peak detect (PKD) function for measuring the output amplitude and in-built photo-diode (PD) cathode bias network. The chip can be operated in manual gain control (MGC) or automatic gain control (AGC) mode. The die area is 1.6 mmA2. A state-of-the art 4-level Pulse Amplitude Modulation (PAM-4) eye diagram at 56Gb/s has been demonstrated with this linear TIA. The Die has been integrated into an optical product from Discovery Semiconductors and several optical interconnect products.
{"title":"A 56 Gb/s PAM-4 linear transimpedance amplifier in 0.13-μm SiGe BiCMOS technology for optical receivers","authors":"S. Bhagavatheeswaran, T. Cummings, Eric Tangen, M. Heins, R. Chan, C. Steinbeiser","doi":"10.1109/CSICS.2017.8240445","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240445","url":null,"abstract":"This paper describes the implementation of a state-of-the art 56Gb/s single-channel linear transimpedance amplifier (TIA) integrated circuit for PAM-4/NRZ/DMT modulation formats used in data center interconnects (DCI) and base station front haul applications. Fabricated in 130nm SiGe BiCMOS process, the TIA has a single-ended input, differential output configuration, with nominal maximum DC transimpedance gain of ∼5.8 kQ (75 dB), gain dynamic range of 28 dB, average input referred noise (IRN) of 14.9 pA/VHz, typical bandwidth of 38 GHz across the entire gain dynamic range, Total Harmonic Distortion (THD) of 2% for output of 500mVppd, adjustable output voltage swing up to 1Vppd, all operated with typical supply of 3.3 V. At 2.8 V supply, bandwidth of 34 GHz has been achieved. Performance has been measured from −5C to 95C. The TIA has Receive Signal Strength Indicator (RSSI) for measuring the input signal strength, peak detect (PKD) function for measuring the output amplitude and in-built photo-diode (PD) cathode bias network. The chip can be operated in manual gain control (MGC) or automatic gain control (AGC) mode. The die area is 1.6 mmA2. A state-of-the art 4-level Pulse Amplitude Modulation (PAM-4) eye diagram at 56Gb/s has been demonstrated with this linear TIA. The Die has been integrated into an optical product from Discovery Semiconductors and several optical interconnect products.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"62 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120924418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240436
S. Zihir, Gabriel M. Rebeiz
In this paper, a 5–15 GHz I/Q modulator implemented in 45 nm SOI CMOS is presented, which shares DC current through biasing branch, I/Q mixers and stacked-FET power amplifier (PA) to provide high output power and linearity. Stacked SOI transistors are used to isolate the modulator from high voltage swing at the load and mitigate device break-down. The proposed architecture results in an OP1db and OIP3 of 15.6–19.5 dBm and 26–30 dBm at 5–15 GHz, respectively. The circuit occupies only 0.46 rnrn2 including pads. Application areas are in the 5G high-linearity IF circuity for high data-rate modulations.
本文提出了一种采用45 nm SOI CMOS实现的5-15 GHz I/Q调制器，该调制器通过偏置支路、I/Q混频器和堆叠fet功率放大器(PA)共享直流电流，提供高输出功率和线性度。堆叠SOI晶体管用于隔离调制器在负载处的高电压振荡，并减轻器件击穿。该架构在5-15 GHz下的OP1db和OIP3分别为15.6-19.5 dBm和26-30 dBm。包括焊盘在内，该电路仅占用0.46 rnrn2。应用领域是用于高数据速率调制的5G高线性中频电路。
{"title":"A 5–15 GHz stacked I/Q modulator with 15–19 dBm OP1dB and 26–30 dBm OIP3 in 45 nm SOI CMOS","authors":"S. Zihir, Gabriel M. Rebeiz","doi":"10.1109/CSICS.2017.8240436","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240436","url":null,"abstract":"In this paper, a 5–15 GHz I/Q modulator implemented in 45 nm SOI CMOS is presented, which shares DC current through biasing branch, I/Q mixers and stacked-FET power amplifier (PA) to provide high output power and linearity. Stacked SOI transistors are used to isolate the modulator from high voltage swing at the load and mitigate device break-down. The proposed architecture results in an OP1db and OIP3 of 15.6–19.5 dBm and 26–30 dBm at 5–15 GHz, respectively. The circuit occupies only 0.46 rnrn2 including pads. Application areas are in the 5G high-linearity IF circuity for high data-rate modulations.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123912841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240437
Sona Carpenter, Z. He, H. Zirath
A wideband balanced active frequency doubler at Dband (110–170 GHz) and a frequency tripler at G-band (140–220 GHz) is presented. The circuits are implemented in a 250nm InP DHBT technology with ft/fmax 350/600 GHz respectively. The experimental results of the frequency doubler exhibit an output power of 4.2 dBm with 3-dB output bandwidth from 120 to 158 GHz corresponding to 27.3 % relative bandwidth. The power efficiency is 11.9 % at 124 GHz output and 5 dBm input power. The doubler chip consumes a dc-power of 19 mW and the chip dimension is 0.45 × 0.4 mm2. The tripler chip can provide output power of 3.8 dBm and has 3-dB output bandwidth of 27 GHz from 162–189 GHz. The balanced topology and band pass filter were utilized in tripler circuit for harmonic suppression. The fundamental- and second-harmonic suppressions are better than 20 dBc and 28 dBc, respectively. The dc power consumption is 26 mW. The chip surface is 0.9 × 0.4 mm2.
{"title":"Balanced active frequency multipliers in D and G bands using 250nm InP DHBT technology","authors":"Sona Carpenter, Z. He, H. Zirath","doi":"10.1109/CSICS.2017.8240437","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240437","url":null,"abstract":"A wideband balanced active frequency doubler at Dband (110–170 GHz) and a frequency tripler at G-band (140–220 GHz) is presented. The circuits are implemented in a 250nm InP DHBT technology with ft/fmax 350/600 GHz respectively. The experimental results of the frequency doubler exhibit an output power of 4.2 dBm with 3-dB output bandwidth from 120 to 158 GHz corresponding to 27.3 % relative bandwidth. The power efficiency is 11.9 % at 124 GHz output and 5 dBm input power. The doubler chip consumes a dc-power of 19 mW and the chip dimension is 0.45 × 0.4 mm2. The tripler chip can provide output power of 3.8 dBm and has 3-dB output bandwidth of 27 GHz from 162–189 GHz. The balanced topology and band pass filter were utilized in tripler circuit for harmonic suppression. The fundamental- and second-harmonic suppressions are better than 20 dBc and 28 dBc, respectively. The dc power consumption is 26 mW. The chip surface is 0.9 × 0.4 mm2.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132777996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240444
A. P. Catalano, A. Magnani, V. d’Alessandro, L. Codecasa, N. Rinaldi, B. Moser, P. Zampardi
This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs in a laminate (package) environment. The combination between the Design of Experiments technique and a fast and accurate simulation capability is adopted to quantify the impact of all the key technology parameters and explore a wide range of operating conditions.
{"title":"Numerical analysis of the thermal behavior sensitivity to technology parameters and operating conditions in InGaP/GaAs HBTs","authors":"A. P. Catalano, A. Magnani, V. d’Alessandro, L. Codecasa, N. Rinaldi, B. Moser, P. Zampardi","doi":"10.1109/CSICS.2017.8240444","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240444","url":null,"abstract":"This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs in a laminate (package) environment. The combination between the Design of Experiments technique and a fast and accurate simulation capability is adopted to quantify the impact of all the key technology parameters and explore a wide range of operating conditions.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129727892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240438
G. Brocero, D. Kendig, A. Shakouri, Y. Guhel, P. Eudeline, J. Sipma, B. Boudart
Significant advances in AlGaN/GaN heterostructure based technologies in the last decade, with AlGaN/GaN high electron mobility transistors (HEMTs) has led to high power performance at Gigahertz frequencies for communication, space, radar, and defense applications. The conjunction of the remarkable properties of the AlGaN/GaN heterojunction and the high thermal conductivity of the silicon carbide substrate enables GaN on SiC-based high electron-mobility transistors (HEMTs) to be very efficient for RF and microwave applications. However, this very high power density leads to self-heating under operating conditions and has important consequences for both performance and reliability. Since these devices, over time, are going to be increasingly smaller and more powerful a method for measuring the self-heating is of great interest for thermal management, temperature control, and optimizing simulation software. This paper presents early results of a new high spatial resolution thermal characterization technique using a thermoreflectance imaging system on a commercial sample. This technique, hyperspectral thermoreflectance imaging, enables us to obtain a clean thermal image in CW mode with 45 nm spatial resolution. We will show the thermal imaging results for a AlGaN/GaN HEMT on a SiC substrate. Although the zone of interest has narrow geometry and some grainy surfaces, the results show a very good linearity of reflection response with changing temperature with a significantly smaller error.
{"title":"Innovative submicron thermal characterization method for AlGaN/GaN power HEMTs with hyperspectral thermoreflectance imaging","authors":"G. Brocero, D. Kendig, A. Shakouri, Y. Guhel, P. Eudeline, J. Sipma, B. Boudart","doi":"10.1109/CSICS.2017.8240438","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240438","url":null,"abstract":"Significant advances in AlGaN/GaN heterostructure based technologies in the last decade, with AlGaN/GaN high electron mobility transistors (HEMTs) has led to high power performance at Gigahertz frequencies for communication, space, radar, and defense applications. The conjunction of the remarkable properties of the AlGaN/GaN heterojunction and the high thermal conductivity of the silicon carbide substrate enables GaN on SiC-based high electron-mobility transistors (HEMTs) to be very efficient for RF and microwave applications. However, this very high power density leads to self-heating under operating conditions and has important consequences for both performance and reliability. Since these devices, over time, are going to be increasingly smaller and more powerful a method for measuring the self-heating is of great interest for thermal management, temperature control, and optimizing simulation software. This paper presents early results of a new high spatial resolution thermal characterization technique using a thermoreflectance imaging system on a commercial sample. This technique, hyperspectral thermoreflectance imaging, enables us to obtain a clean thermal image in CW mode with 45 nm spatial resolution. We will show the thermal imaging results for a AlGaN/GaN HEMT on a SiC substrate. Although the zone of interest has narrow geometry and some grainy surfaces, the results show a very good linearity of reflection response with changing temperature with a significantly smaller error.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128623555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240429
P. Sakalas, M. Schroter, T. Nardmann, H. Zirath
High frequency (h.f.) harmonic distortion (HD) of advanced InP heterojunction bipolar transistors (HBTs) with various emitter widths was investigated. Geometry scalable parameters for the compact model (CM) HICUM/L2 v. 2.34, featuring a two-region base-collector capacitance formulation, were extracted from temperature dependent DC and AC measurements of HBTs and from the special test structures. Single tone harmonic distortion and active two tone load pull measurements were carried out for different emitter area devices. The compact model was used for data analysis.
研究了不同发射极宽度的先进InP异质结双极晶体管(hbt)的高频谐波畸变。紧凑模型(CM) HICUM/L2 v. 2.34的几何可扩展参数采用双区基极集电极电容公式，从hbt的温度相关直流和交流测量以及特殊测试结构中提取。对不同发射极面积的器件进行了单音谐波失真和有源双音负载拉力测量。采用紧凑模型进行数据分析。
{"title":"Harmonic distortion analysis of InP HBTs with 650 GHz fmax for high data rate communication systems","authors":"P. Sakalas, M. Schroter, T. Nardmann, H. Zirath","doi":"10.1109/CSICS.2017.8240429","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240429","url":null,"abstract":"High frequency (h.f.) harmonic distortion (HD) of advanced InP heterojunction bipolar transistors (HBTs) with various emitter widths was investigated. Geometry scalable parameters for the compact model (CM) HICUM/L2 v. 2.34, featuring a two-region base-collector capacitance formulation, were extracted from temperature dependent DC and AC measurements of HBTs and from the special test structures. Single tone harmonic distortion and active two tone load pull measurements were carried out for different emitter area devices. The compact model was used for data analysis.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128668087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240474
T. Merkle, A. Tessmann, M. Kuri, S. Wagner, A. Leuther, S. Rey, M. Zink, H. Stulz, M. Riessle, I. Kallfass, T. Kürner
The first modular 4-channel frontend for exploring phased array communications at a carrier frequency of 300 GHz was developed. A metamorphic HEMT process with a gate length of 35 nm was the key enabling technology for the integration of each transmit and receive channel. All channels implemented the quadrature direct conversion architecture. The measured RF bandwidth exceeded 55 GHz for the receive array respectively 45 GHz for the transmit array using a continuous wave baseband test signal. Phase shifting in the local oscillator path was the focus of this work. The concept was realized by using four synchronized direct digital synthesis channels followed by a high power frequency multiplier-by-12 MMIC. Investigating and assessing the array coherency at 300 GHz by the use of higher order modulation schemes was also proposed, highlighted on the example of a 16-QAM signal at 4 Gbaud in comparison to phase noise measurements of each channel.
{"title":"Testbed for phased array communications from 275 to 325 GHz","authors":"T. Merkle, A. Tessmann, M. Kuri, S. Wagner, A. Leuther, S. Rey, M. Zink, H. Stulz, M. Riessle, I. Kallfass, T. Kürner","doi":"10.1109/CSICS.2017.8240474","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240474","url":null,"abstract":"The first modular 4-channel frontend for exploring phased array communications at a carrier frequency of 300 GHz was developed. A metamorphic HEMT process with a gate length of 35 nm was the key enabling technology for the integration of each transmit and receive channel. All channels implemented the quadrature direct conversion architecture. The measured RF bandwidth exceeded 55 GHz for the receive array respectively 45 GHz for the transmit array using a continuous wave baseband test signal. Phase shifting in the local oscillator path was the focus of this work. The concept was realized by using four synchronized direct digital synthesis channels followed by a high power frequency multiplier-by-12 MMIC. Investigating and assessing the array coherency at 300 GHz by the use of higher order modulation schemes was also proposed, highlighted on the example of a 16-QAM signal at 4 Gbaud in comparison to phase noise measurements of each channel.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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