Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240477
M. LaRue, B. Dupaix, S. Rashid, T. Barton, T. James, W. Gouty, P. Watson, T. Quach, W. Khalil
A fully-integrated transmitter is presented in DARPA's DAHI process technology, featuring heterogeneous integration of 45nm SOI CMOS and 0.2pm GaN technologies. This transmitter is capable of transmitting SOQPSK-TG telemetry waveforms across 2–5 GHz with a peak transmitter power efficiency of 41.32% and peak output power of 32.93 dBm. A reconfigurable CMOS phase modulator is implemented to provide 6-bit phase resolution across the entire output frequency range, and a wide-swing CMOS buffer was designed to drive the GaN power amplifier. The GaN PA features a three-stage design, featuring a differential CML buffer, push-pull inverting buffer, and a class-E switch-mode power amplifier to efficiently amplify the signal. To the authors' knowledge, this is the first fully-integrated transmitter combining CMOS and GaN technology demonstrated in literature.
{"title":"A fully-integrated S/C band transmitter in 45nm CMOS/ 0.2gm GaN heterogeneous technology","authors":"M. LaRue, B. Dupaix, S. Rashid, T. Barton, T. James, W. Gouty, P. Watson, T. Quach, W. Khalil","doi":"10.1109/CSICS.2017.8240477","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240477","url":null,"abstract":"A fully-integrated transmitter is presented in DARPA's DAHI process technology, featuring heterogeneous integration of 45nm SOI CMOS and 0.2pm GaN technologies. This transmitter is capable of transmitting SOQPSK-TG telemetry waveforms across 2–5 GHz with a peak transmitter power efficiency of 41.32% and peak output power of 32.93 dBm. A reconfigurable CMOS phase modulator is implemented to provide 6-bit phase resolution across the entire output frequency range, and a wide-swing CMOS buffer was designed to drive the GaN power amplifier. The GaN PA features a three-stage design, featuring a differential CML buffer, push-pull inverting buffer, and a class-E switch-mode power amplifier to efficiently amplify the signal. To the authors' knowledge, this is the first fully-integrated transmitter combining CMOS and GaN technology demonstrated in literature.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133388421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240431
A. Gasmi, M. El Kaamouchi, J. Poulain, B. Wroblewski, F. Lecourt, Gulnar Dagher, P. Frijlink, R. Leblanc
This paper presents two Monolithic Microwave Integrated Circuits (MMIC) designed and fabricated with the same 100 nm Gallium Nitride on Silicon (GaN/Si) millimeter wave process, demonstrating the excellent multipurpose capability of this technology. The first circuit is a 29–33 GHz power amplifier, presenting 10 W of output power in pulsed operation and 8 W is CW operation. The second MMIC is a 26–34 GHz Transmit/Receive chip (T/R chip), including on the same chip a Low Noise Amplifier (LNA), a Power Amplifier (PA) and a SPDT switch. In the 28–34 GHz frequency bandwidth, this T/R chip, including the switch losses, presents an output power of 35–36 dBm and a Noise Figure of 2.7 dB with an associated gain of 18 dB for the receive and transmit paths.
{"title":"10W power amplifier and 3W transmit/receive module with 3 dB NF in Ka band using a 100nm GaN/Si process","authors":"A. Gasmi, M. El Kaamouchi, J. Poulain, B. Wroblewski, F. Lecourt, Gulnar Dagher, P. Frijlink, R. Leblanc","doi":"10.1109/CSICS.2017.8240431","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240431","url":null,"abstract":"This paper presents two Monolithic Microwave Integrated Circuits (MMIC) designed and fabricated with the same 100 nm Gallium Nitride on Silicon (GaN/Si) millimeter wave process, demonstrating the excellent multipurpose capability of this technology. The first circuit is a 29–33 GHz power amplifier, presenting 10 W of output power in pulsed operation and 8 W is CW operation. The second MMIC is a 26–34 GHz Transmit/Receive chip (T/R chip), including on the same chip a Low Noise Amplifier (LNA), a Power Amplifier (PA) and a SPDT switch. In the 28–34 GHz frequency bandwidth, this T/R chip, including the switch losses, presents an output power of 35–36 dBm and a Noise Figure of 2.7 dB with an associated gain of 18 dB for the receive and transmit paths.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240470
K. Patel, H. Golestaneh, S. Boumaiza
This paper proposes a design methodology based off the novel concept of current contours to insure proper current profiles for the main and peaking transistors needed to satisfy the load modulation conditions in a Doherty power amplifier over a wide frequency range. Utilizing this technique allows the construction of input matching networks that maximize the efficiency enhancement and linearity of the DPA. As a proof-of-concept, a 12 W DPA was designed. From 2.7 GHz to 4.7 GHz, continuous wave measurements have shown efficiency levels of greater than 37 % at 6 dB output power back-off and peak power. A gain of at least 8 db was shown with output power ranging from 40.7 dBm ±1 dB. Under an 80 MHz carrier aggregated signal, modulated signal results showed good linearizability with an ACLR of −48 dBc/Hz after digital pre-distortion.
{"title":"Current contours based IMN design methodology for broadband GaN Doherty power amplifiers","authors":"K. Patel, H. Golestaneh, S. Boumaiza","doi":"10.1109/CSICS.2017.8240470","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240470","url":null,"abstract":"This paper proposes a design methodology based off the novel concept of current contours to insure proper current profiles for the main and peaking transistors needed to satisfy the load modulation conditions in a Doherty power amplifier over a wide frequency range. Utilizing this technique allows the construction of input matching networks that maximize the efficiency enhancement and linearity of the DPA. As a proof-of-concept, a 12 W DPA was designed. From 2.7 GHz to 4.7 GHz, continuous wave measurements have shown efficiency levels of greater than 37 % at 6 dB output power back-off and peak power. A gain of at least 8 db was shown with output power ranging from 40.7 dBm ±1 dB. Under an 80 MHz carrier aggregated signal, modulated signal results showed good linearizability with an ACLR of −48 dBc/Hz after digital pre-distortion.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240436
S. Zihir, Gabriel M. Rebeiz
In this paper, a 5–15 GHz I/Q modulator implemented in 45 nm SOI CMOS is presented, which shares DC current through biasing branch, I/Q mixers and stacked-FET power amplifier (PA) to provide high output power and linearity. Stacked SOI transistors are used to isolate the modulator from high voltage swing at the load and mitigate device break-down. The proposed architecture results in an OP1db and OIP3 of 15.6–19.5 dBm and 26–30 dBm at 5–15 GHz, respectively. The circuit occupies only 0.46 rnrn2 including pads. Application areas are in the 5G high-linearity IF circuity for high data-rate modulations.
本文提出了一种采用45 nm SOI CMOS实现的5-15 GHz I/Q调制器，该调制器通过偏置支路、I/Q混频器和堆叠fet功率放大器(PA)共享直流电流，提供高输出功率和线性度。堆叠SOI晶体管用于隔离调制器在负载处的高电压振荡，并减轻器件击穿。该架构在5-15 GHz下的OP1db和OIP3分别为15.6-19.5 dBm和26-30 dBm。包括焊盘在内，该电路仅占用0.46 rnrn2。应用领域是用于高数据速率调制的5G高线性中频电路。
{"title":"A 5–15 GHz stacked I/Q modulator with 15–19 dBm OP1dB and 26–30 dBm OIP3 in 45 nm SOI CMOS","authors":"S. Zihir, Gabriel M. Rebeiz","doi":"10.1109/CSICS.2017.8240436","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240436","url":null,"abstract":"In this paper, a 5–15 GHz I/Q modulator implemented in 45 nm SOI CMOS is presented, which shares DC current through biasing branch, I/Q mixers and stacked-FET power amplifier (PA) to provide high output power and linearity. Stacked SOI transistors are used to isolate the modulator from high voltage swing at the load and mitigate device break-down. The proposed architecture results in an OP1db and OIP3 of 15.6–19.5 dBm and 26–30 dBm at 5–15 GHz, respectively. The circuit occupies only 0.46 rnrn2 including pads. Application areas are in the 5G high-linearity IF circuity for high data-rate modulations.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123912841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240445
S. Bhagavatheeswaran, T. Cummings, Eric Tangen, M. Heins, R. Chan, C. Steinbeiser
This paper describes the implementation of a state-of-the art 56Gb/s single-channel linear transimpedance amplifier (TIA) integrated circuit for PAM-4/NRZ/DMT modulation formats used in data center interconnects (DCI) and base station front haul applications. Fabricated in 130nm SiGe BiCMOS process, the TIA has a single-ended input, differential output configuration, with nominal maximum DC transimpedance gain of ∼5.8 kQ (75 dB), gain dynamic range of 28 dB, average input referred noise (IRN) of 14.9 pA/VHz, typical bandwidth of 38 GHz across the entire gain dynamic range, Total Harmonic Distortion (THD) of 2% for output of 500mVppd, adjustable output voltage swing up to 1Vppd, all operated with typical supply of 3.3 V. At 2.8 V supply, bandwidth of 34 GHz has been achieved. Performance has been measured from −5C to 95C. The TIA has Receive Signal Strength Indicator (RSSI) for measuring the input signal strength, peak detect (PKD) function for measuring the output amplitude and in-built photo-diode (PD) cathode bias network. The chip can be operated in manual gain control (MGC) or automatic gain control (AGC) mode. The die area is 1.6 mmA2. A state-of-the art 4-level Pulse Amplitude Modulation (PAM-4) eye diagram at 56Gb/s has been demonstrated with this linear TIA. The Die has been integrated into an optical product from Discovery Semiconductors and several optical interconnect products.
{"title":"A 56 Gb/s PAM-4 linear transimpedance amplifier in 0.13-μm SiGe BiCMOS technology for optical receivers","authors":"S. Bhagavatheeswaran, T. Cummings, Eric Tangen, M. Heins, R. Chan, C. Steinbeiser","doi":"10.1109/CSICS.2017.8240445","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240445","url":null,"abstract":"This paper describes the implementation of a state-of-the art 56Gb/s single-channel linear transimpedance amplifier (TIA) integrated circuit for PAM-4/NRZ/DMT modulation formats used in data center interconnects (DCI) and base station front haul applications. Fabricated in 130nm SiGe BiCMOS process, the TIA has a single-ended input, differential output configuration, with nominal maximum DC transimpedance gain of ∼5.8 kQ (75 dB), gain dynamic range of 28 dB, average input referred noise (IRN) of 14.9 pA/VHz, typical bandwidth of 38 GHz across the entire gain dynamic range, Total Harmonic Distortion (THD) of 2% for output of 500mVppd, adjustable output voltage swing up to 1Vppd, all operated with typical supply of 3.3 V. At 2.8 V supply, bandwidth of 34 GHz has been achieved. Performance has been measured from −5C to 95C. The TIA has Receive Signal Strength Indicator (RSSI) for measuring the input signal strength, peak detect (PKD) function for measuring the output amplitude and in-built photo-diode (PD) cathode bias network. The chip can be operated in manual gain control (MGC) or automatic gain control (AGC) mode. The die area is 1.6 mmA2. A state-of-the art 4-level Pulse Amplitude Modulation (PAM-4) eye diagram at 56Gb/s has been demonstrated with this linear TIA. The Die has been integrated into an optical product from Discovery Semiconductors and several optical interconnect products.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"62 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120924418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240437
Sona Carpenter, Z. He, H. Zirath
A wideband balanced active frequency doubler at Dband (110–170 GHz) and a frequency tripler at G-band (140–220 GHz) is presented. The circuits are implemented in a 250nm InP DHBT technology with ft/fmax 350/600 GHz respectively. The experimental results of the frequency doubler exhibit an output power of 4.2 dBm with 3-dB output bandwidth from 120 to 158 GHz corresponding to 27.3 % relative bandwidth. The power efficiency is 11.9 % at 124 GHz output and 5 dBm input power. The doubler chip consumes a dc-power of 19 mW and the chip dimension is 0.45 × 0.4 mm2. The tripler chip can provide output power of 3.8 dBm and has 3-dB output bandwidth of 27 GHz from 162–189 GHz. The balanced topology and band pass filter were utilized in tripler circuit for harmonic suppression. The fundamental- and second-harmonic suppressions are better than 20 dBc and 28 dBc, respectively. The dc power consumption is 26 mW. The chip surface is 0.9 × 0.4 mm2.
{"title":"Balanced active frequency multipliers in D and G bands using 250nm InP DHBT technology","authors":"Sona Carpenter, Z. He, H. Zirath","doi":"10.1109/CSICS.2017.8240437","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240437","url":null,"abstract":"A wideband balanced active frequency doubler at Dband (110–170 GHz) and a frequency tripler at G-band (140–220 GHz) is presented. The circuits are implemented in a 250nm InP DHBT technology with ft/fmax 350/600 GHz respectively. The experimental results of the frequency doubler exhibit an output power of 4.2 dBm with 3-dB output bandwidth from 120 to 158 GHz corresponding to 27.3 % relative bandwidth. The power efficiency is 11.9 % at 124 GHz output and 5 dBm input power. The doubler chip consumes a dc-power of 19 mW and the chip dimension is 0.45 × 0.4 mm2. The tripler chip can provide output power of 3.8 dBm and has 3-dB output bandwidth of 27 GHz from 162–189 GHz. The balanced topology and band pass filter were utilized in tripler circuit for harmonic suppression. The fundamental- and second-harmonic suppressions are better than 20 dBc and 28 dBc, respectively. The dc power consumption is 26 mW. The chip surface is 0.9 × 0.4 mm2.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132777996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240474
T. Merkle, A. Tessmann, M. Kuri, S. Wagner, A. Leuther, S. Rey, M. Zink, H. Stulz, M. Riessle, I. Kallfass, T. Kürner
The first modular 4-channel frontend for exploring phased array communications at a carrier frequency of 300 GHz was developed. A metamorphic HEMT process with a gate length of 35 nm was the key enabling technology for the integration of each transmit and receive channel. All channels implemented the quadrature direct conversion architecture. The measured RF bandwidth exceeded 55 GHz for the receive array respectively 45 GHz for the transmit array using a continuous wave baseband test signal. Phase shifting in the local oscillator path was the focus of this work. The concept was realized by using four synchronized direct digital synthesis channels followed by a high power frequency multiplier-by-12 MMIC. Investigating and assessing the array coherency at 300 GHz by the use of higher order modulation schemes was also proposed, highlighted on the example of a 16-QAM signal at 4 Gbaud in comparison to phase noise measurements of each channel.
{"title":"Testbed for phased array communications from 275 to 325 GHz","authors":"T. Merkle, A. Tessmann, M. Kuri, S. Wagner, A. Leuther, S. Rey, M. Zink, H. Stulz, M. Riessle, I. Kallfass, T. Kürner","doi":"10.1109/CSICS.2017.8240474","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240474","url":null,"abstract":"The first modular 4-channel frontend for exploring phased array communications at a carrier frequency of 300 GHz was developed. A metamorphic HEMT process with a gate length of 35 nm was the key enabling technology for the integration of each transmit and receive channel. All channels implemented the quadrature direct conversion architecture. The measured RF bandwidth exceeded 55 GHz for the receive array respectively 45 GHz for the transmit array using a continuous wave baseband test signal. Phase shifting in the local oscillator path was the focus of this work. The concept was realized by using four synchronized direct digital synthesis channels followed by a high power frequency multiplier-by-12 MMIC. Investigating and assessing the array coherency at 300 GHz by the use of higher order modulation schemes was also proposed, highlighted on the example of a 16-QAM signal at 4 Gbaud in comparison to phase noise measurements of each channel.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240444
A. P. Catalano, A. Magnani, V. d’Alessandro, L. Codecasa, N. Rinaldi, B. Moser, P. Zampardi
This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs in a laminate (package) environment. The combination between the Design of Experiments technique and a fast and accurate simulation capability is adopted to quantify the impact of all the key technology parameters and explore a wide range of operating conditions.
{"title":"Numerical analysis of the thermal behavior sensitivity to technology parameters and operating conditions in InGaP/GaAs HBTs","authors":"A. P. Catalano, A. Magnani, V. d’Alessandro, L. Codecasa, N. Rinaldi, B. Moser, P. Zampardi","doi":"10.1109/CSICS.2017.8240444","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240444","url":null,"abstract":"This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs in a laminate (package) environment. The combination between the Design of Experiments technique and a fast and accurate simulation capability is adopted to quantify the impact of all the key technology parameters and explore a wide range of operating conditions.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129727892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240466
N. Chowdhury, T. Palacios
This paper describes how the use of nanostructures can significantly increase the performance of GaN transistors. 100–400 nm fins have been defined underneath the gate electrode of AlGaN/GaN transistors to increase the gate modulation efficiency of these devices and to allow for the tuning of the threshold voltage. The proper design of these fins allows not only an improvement in the DC performance of the device, but also a significant enhancement of the rf linearity of the transistors. The excellent electron transport in these nanostructures, combined with the wide bandgap of GaN, its large effective mass and its moderate electric permittivity, also allows the potential scaling of GaN transistors below 5 nm channel length. The theoretical performance of these ultra-scaled devices is benchmarked with respect to other competing technologies.
{"title":"Nanostructured GaN transistors","authors":"N. Chowdhury, T. Palacios","doi":"10.1109/CSICS.2017.8240466","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240466","url":null,"abstract":"This paper describes how the use of nanostructures can significantly increase the performance of GaN transistors. 100–400 nm fins have been defined underneath the gate electrode of AlGaN/GaN transistors to increase the gate modulation efficiency of these devices and to allow for the tuning of the threshold voltage. The proper design of these fins allows not only an improvement in the DC performance of the device, but also a significant enhancement of the rf linearity of the transistors. The excellent electron transport in these nanostructures, combined with the wide bandgap of GaN, its large effective mass and its moderate electric permittivity, also allows the potential scaling of GaN transistors below 5 nm channel length. The theoretical performance of these ultra-scaled devices is benchmarked with respect to other competing technologies.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126771297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/CSICS.2017.8240465
D. Disanto, T. Shirley, R. Shimon
5G and aerospace/defense (A/D) trends are influencing the requirements for mm-wave test and measurement (T&M) equipment and the underlying technologies. Additional requirements such as small formfactors, lower-cost mm-wave test, and connector-less test are emerging. To meet these challenging attributes, both silicon and III-Vs have important roles to play. Si provides attractive solutions for small form-factor & high-volume applications with its excellent integration and economies of scale. However, operating voltages limit performance while high NRE costs create challenges for high-mix low-volume businesses. While III-Vs are well suited to mm-wave performance, they have significantly higher manufacturing costs and require continued advances in packaging to meet form-factor needs. Simultaneously addressing performance and cost needs at mm-wave requires careful consideration of these tradeoffs to drive selection of, and improvements in, semiconductor devices and packaging solutions.
{"title":"Technology options for mm-wave test and measurement equipment","authors":"D. Disanto, T. Shirley, R. Shimon","doi":"10.1109/CSICS.2017.8240465","DOIUrl":"https://doi.org/10.1109/CSICS.2017.8240465","url":null,"abstract":"5G and aerospace/defense (A/D) trends are influencing the requirements for mm-wave test and measurement (T&M) equipment and the underlying technologies. Additional requirements such as small formfactors, lower-cost mm-wave test, and connector-less test are emerging. To meet these challenging attributes, both silicon and III-Vs have important roles to play. Si provides attractive solutions for small form-factor & high-volume applications with its excellent integration and economies of scale. However, operating voltages limit performance while high NRE costs create challenges for high-mix low-volume businesses. While III-Vs are well suited to mm-wave performance, they have significantly higher manufacturing costs and require continued advances in packaging to meet form-factor needs. Simultaneously addressing performance and cost needs at mm-wave requires careful consideration of these tradeoffs to drive selection of, and improvements in, semiconductor devices and packaging solutions.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126798899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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