Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451002
A. Veiga, E. Spinelli
We present an FPGA-synthesizable version of a pseudo-random pulse generator that can be used to emulate radioactive source activity. It is intended for debugging real-time digital pulse processing applications, beyond the capabilities of periodic generators. The proposed module delivers a discrete random sequence that follows the Poisson inter-arrival distribution. Operation is based on a barrel-shifted maximal-length linear feedback shift register, operating as uniform random number generator, followed by an implementation of the Bernoulli trial to emulate exponential inter-arrival times. Due to its simple design, it can operate at high clock frequencies, providing a minimum time between events of two FPGA clock cycles operating at full-speed. A small footprint Verilog module is proposed for embedding in digital processors. Attainable performance and required resources are calculated. Additionally, it is shown how digital output pulses can be width-modulated to generate, with minimum conditioning, the analog signals present in a spectroscopy detection chain.
{"title":"A pulse generator with poisson-exponential distribution for emulation of radioactive decay events","authors":"A. Veiga, E. Spinelli","doi":"10.1109/LASCAS.2016.7451002","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451002","url":null,"abstract":"We present an FPGA-synthesizable version of a pseudo-random pulse generator that can be used to emulate radioactive source activity. It is intended for debugging real-time digital pulse processing applications, beyond the capabilities of periodic generators. The proposed module delivers a discrete random sequence that follows the Poisson inter-arrival distribution. Operation is based on a barrel-shifted maximal-length linear feedback shift register, operating as uniform random number generator, followed by an implementation of the Bernoulli trial to emulate exponential inter-arrival times. Due to its simple design, it can operate at high clock frequencies, providing a minimum time between events of two FPGA clock cycles operating at full-speed. A small footprint Verilog module is proposed for embedding in digital processors. Attainable performance and required resources are calculated. Additionally, it is shown how digital output pulses can be width-modulated to generate, with minimum conditioning, the analog signals present in a spectroscopy detection chain.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131168674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451073
Ckristian Duran, D. L. Rueda, Giovanny Castillo, A. Agudelo, Camilo Rojas, L. Chaparro, H. Hurtado, Juan Romero, Wilmer Ramirez, H. Gómez, Javier Ardila, G. LuisE.Rueda, H. Hernández, Jose Amaya, E. Roa
In this paper a complete implementation and design of a fully-synthesized 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification, and an SPI APB slave interface for checking the correct behavioral of the APB bridge. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves. A total power density is reported as 167μW/MHz and the area for this RISC-V microcontroller has a reduced footprint of 798μm×484μm.
{"title":"A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC","authors":"Ckristian Duran, D. L. Rueda, Giovanny Castillo, A. Agudelo, Camilo Rojas, L. Chaparro, H. Hurtado, Juan Romero, Wilmer Ramirez, H. Gómez, Javier Ardila, G. LuisE.Rueda, H. Hernández, Jose Amaya, E. Roa","doi":"10.1109/LASCAS.2016.7451073","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451073","url":null,"abstract":"In this paper a complete implementation and design of a fully-synthesized 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification, and an SPI APB slave interface for checking the correct behavioral of the APB bridge. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves. A total power density is reported as 167μW/MHz and the area for this RISC-V microcontroller has a reduced footprint of 798μm×484μm.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123682098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451013
Ahmad Hassan, Aref Trigui, M. Sawan
Bıocompatıbılıty remains a critical issue due to the foreign body response following device implantation. “Collagen” is the main bio-material composed around the implanted devices. This paper reports the possibility to measure the thickness of the “Collagen layers” using impedance measurement. An implanted passive circuit sensitive to the collagen thickness is wirelessly connected to the external reading circuit through inductive coupling. The resonance frequency of the system is directly proportional to the Collagen layer thickness variation. A modeling and simulation study of the Collagen material is presented by “COMSOL” to verify the functionality and obtain the optimal design parameters. Reported results demonstrate the increment of collagen capacitance from 30fF to 120fF when the collagen thickness rises from 1mm to 6mm. The experimental validation is reported using Impedance Analyzer. The measured resonance frequency drops from 55.78MHz to 54.98MHz when the collagen thickness increases from 0 to 10mm.
{"title":"Wireless monitoring of collagen progression around implantable prostheses","authors":"Ahmad Hassan, Aref Trigui, M. Sawan","doi":"10.1109/LASCAS.2016.7451013","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451013","url":null,"abstract":"Bıocompatıbılıty remains a critical issue due to the foreign body response following device implantation. “Collagen” is the main bio-material composed around the implanted devices. This paper reports the possibility to measure the thickness of the “Collagen layers” using impedance measurement. An implanted passive circuit sensitive to the collagen thickness is wirelessly connected to the external reading circuit through inductive coupling. The resonance frequency of the system is directly proportional to the Collagen layer thickness variation. A modeling and simulation study of the Collagen material is presented by “COMSOL” to verify the functionality and obtain the optimal design parameters. Reported results demonstrate the increment of collagen capacitance from 30fF to 120fF when the collagen thickness rises from 1mm to 6mm. The experimental validation is reported using Impedance Analyzer. The measured resonance frequency drops from 55.78MHz to 54.98MHz when the collagen thickness increases from 0 to 10mm.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131097784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451028
Luian H. Zanoni, F. L. Bertotti, D. Campos
This paper presents the development of a biotelemetry system comprising a microcontrolled sensing unit and a reading unit. Through the magnetic coupling between the coils of an inductive link, the reading unit is able to provide power and establish data communication with the sensing unit. A signal generator and a current driver in the reading unit allow energy transfer to the sensing unit, which has a microcontroller that performs the signal acquisition of a temperature sensor and sends the resulting digital data to the reading unit by means of a LSK modulator. The ASK demodulator of the reading unit retrieves the data that is processed by another microcontroller, which provides the measurement result to a computer over a serial communication interface. The results showed that the sensing unit operates at a coupling distance of up to 21 mm between the sensing and reading unit coils for a 9600 bps data communication rate, whereas the maximum achieved data rate was 38400 kbps for a coupling distance of 8 mm.
{"title":"Development of a biotelemetry system with a microcontrolled sensing unit","authors":"Luian H. Zanoni, F. L. Bertotti, D. Campos","doi":"10.1109/LASCAS.2016.7451028","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451028","url":null,"abstract":"This paper presents the development of a biotelemetry system comprising a microcontrolled sensing unit and a reading unit. Through the magnetic coupling between the coils of an inductive link, the reading unit is able to provide power and establish data communication with the sensing unit. A signal generator and a current driver in the reading unit allow energy transfer to the sensing unit, which has a microcontroller that performs the signal acquisition of a temperature sensor and sends the resulting digital data to the reading unit by means of a LSK modulator. The ASK demodulator of the reading unit retrieves the data that is processed by another microcontroller, which provides the measurement result to a computer over a serial communication interface. The results showed that the sensing unit operates at a coupling distance of up to 21 mm between the sensing and reading unit coils for a 9600 bps data communication rate, whereas the maximum achieved data rate was 38400 kbps for a coupling distance of 8 mm.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132350466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451014
Magdalena Fuentes, Pablo Zinemanas, Pablo Cancela, J. A. Apolinário
A Phase Locked Loop (PLL) based method for determining audio authenticity is proposed in this work. Assuming that the power grid signal is embedded in an audio signal, certain pre-processing techniques are applied in order to obtain the Electrical Network Frequency (ENF). A PLL is then used to estimate the time-varying phase of the ENF signal. Postprocessing is carried out so as to improve system performance. Finally, an automatic decision on the authenticity of the audio is conducted by quantifying the frequency variations of the VCO output. The performance of the proposed method is evaluated on digitally edited and original audio signals, with promising results (achieving an accuracy of 96%).
{"title":"Detection of ENF discontinuities using PLL for audio authenticity","authors":"Magdalena Fuentes, Pablo Zinemanas, Pablo Cancela, J. A. Apolinário","doi":"10.1109/LASCAS.2016.7451014","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451014","url":null,"abstract":"A Phase Locked Loop (PLL) based method for determining audio authenticity is proposed in this work. Assuming that the power grid signal is embedded in an audio signal, certain pre-processing techniques are applied in order to obtain the Electrical Network Frequency (ENF). A PLL is then used to estimate the time-varying phase of the ENF signal. Postprocessing is carried out so as to improve system performance. Finally, an automatic decision on the authenticity of the audio is conducted by quantifying the frequency variations of the VCO output. The performance of the proposed method is evaluated on digitally edited and original audio signals, with promising results (achieving an accuracy of 96%).","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128262750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451072
Eduardo V. P. Anjos, F. Barúqui
In this paper, a high-linearity version of the zero voltage switching (ZVS) current memory cell is presented. The linearity improvement is achieved by using a high-linear differential pair and compensation switch. Higher power efficiency is also obtained by utilizing a Recycling Folded Cascode (RFC). The proposed memory cell is implemented using CMOS 0.35μm and Cadence Spectre simulations are presented to validate the improvements. The proposed structure is used to implement an integrator which achieved a DC gain of 89.44 dB.
{"title":"High-linearity zero-voltage switching current memory cell for measurement applications","authors":"Eduardo V. P. Anjos, F. Barúqui","doi":"10.1109/LASCAS.2016.7451072","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451072","url":null,"abstract":"In this paper, a high-linearity version of the zero voltage switching (ZVS) current memory cell is presented. The linearity improvement is achieved by using a high-linear differential pair and compensation switch. Higher power efficiency is also obtained by utilizing a Recycling Folded Cascode (RFC). The proposed memory cell is implemented using CMOS 0.35μm and Cadence Spectre simulations are presented to validate the improvements. The proposed structure is used to implement an integrator which achieved a DC gain of 89.44 dB.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123144632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451019
C. JhonA.Gomez, H. Klimach, E. Fabris, S. Bampi
This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the -40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than -71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.
{"title":"1.5 ppm/°C nano-Watt resistorless MOS-only voltage reference","authors":"C. JhonA.Gomez, H. Klimach, E. Fabris, S. Bampi","doi":"10.1109/LASCAS.2016.7451019","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451019","url":null,"abstract":"This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the -40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than -71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131665645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7450995
A. Andreou, Tomas Figliolia, Kayode A. Sanni, Thomas S. Murray, Gaspar Tognetti, Daniel R. Mendat, J. Molin, M. Villemur, P. Pouliquen, P. Julián, R. Etienne-Cummings, I. Doxas
In this paper we discuss a brain-inspired system architecture for real-time big velocity BIGDATA processing that originates in large format tiled imaging arrays used in wide area motion imagery ubiquitous surveillance. High performance and high throughput is achieved through approximate computing and fixed point arithmetic in a variable precision (6 bits to 18 bits) architecture. The architecture implements a variety of processing algorithms classes ranging from convolutional networks (Con-vNets) to linear and non-linear morphological processing, probabilistic inference using exact and approximate Bayesian methods and ConvNet based classification. The processing pipeline is implemented entirely using event based neuromorphic and stochastic computational primitives. The system is capable of processing in real-time 160 × 120 raw pixel data running on a reconfigurable computing platform (5 Xilinx Kintex-7 FPGAs). The reconfigurable computing implementation was developed to emulate the computational structures for a 3D System on Chip (3D-SOC) that will be fabricated in the 55nm CMOS technology and it has a dual goal: (i) algorithm exploration and (ii) architecture exploration.
{"title":"Bio-inspired system architecture for energy efficient, BIGDATA computing with application to wide area motion imagery","authors":"A. Andreou, Tomas Figliolia, Kayode A. Sanni, Thomas S. Murray, Gaspar Tognetti, Daniel R. Mendat, J. Molin, M. Villemur, P. Pouliquen, P. Julián, R. Etienne-Cummings, I. Doxas","doi":"10.1109/LASCAS.2016.7450995","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7450995","url":null,"abstract":"In this paper we discuss a brain-inspired system architecture for real-time big velocity BIGDATA processing that originates in large format tiled imaging arrays used in wide area motion imagery ubiquitous surveillance. High performance and high throughput is achieved through approximate computing and fixed point arithmetic in a variable precision (6 bits to 18 bits) architecture. The architecture implements a variety of processing algorithms classes ranging from convolutional networks (Con-vNets) to linear and non-linear morphological processing, probabilistic inference using exact and approximate Bayesian methods and ConvNet based classification. The processing pipeline is implemented entirely using event based neuromorphic and stochastic computational primitives. The system is capable of processing in real-time 160 × 120 raw pixel data running on a reconfigurable computing platform (5 Xilinx Kintex-7 FPGAs). The reconfigurable computing implementation was developed to emulate the computational structures for a 3D System on Chip (3D-SOC) that will be fabricated in the 55nm CMOS technology and it has a dual goal: (i) algorithm exploration and (ii) architecture exploration.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121532559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451070
Jose Avalos, Sergio A. Cortez, Karina Vasquez, Víctor Murray, O. E. Ramos
Several applications require that a telepresence system does not only transmit images, audio and video but also real-time motion. This work presents the implementation of a system that allows for telepresence using a humanoid robot and a motion capture device. The proposed methodology for motion imitation is fast and uses a low-cost motion acquisition sensor. The objective is to make the robot reproduce the motion of a person. In this way, remote actions can be executed through the robot sending also images and audio from the environment. The method has been applied to the humanoid robot called NAO, which has been able to reproduce human motions. This framework can also be used for different education purposes.
{"title":"Telepresence using the kinect sensor and the NAO robot","authors":"Jose Avalos, Sergio A. Cortez, Karina Vasquez, Víctor Murray, O. E. Ramos","doi":"10.1109/LASCAS.2016.7451070","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451070","url":null,"abstract":"Several applications require that a telepresence system does not only transmit images, audio and video but also real-time motion. This work presents the implementation of a system that allows for telepresence using a humanoid robot and a motion capture device. The proposed methodology for motion imitation is fast and uses a low-cost motion acquisition sensor. The objective is to make the robot reproduce the motion of a person. In this way, remote actions can be executed through the robot sending also images and audio from the environment. The method has been applied to the humanoid robot called NAO, which has been able to reproduce human motions. This framework can also be used for different education purposes.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"22 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116643087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451087
D. Santana, H. Klimach, E. Fabris, S. Bampi
This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It uses an input transformer to reduce ground bounce effects and operates around 1 W of output power. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) of 3 branches is separately activated by a 3-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF process and post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 47% under 3.3 V of supply voltage. The 3-bit control allows a total output power dynamic range adjustment of 12.4 dB, divided in 8 steps, with the PAE changing from 13.4% to 47.3%.
{"title":"CMOS RF class-E power amplifier with power control","authors":"D. Santana, H. Klimach, E. Fabris, S. Bampi","doi":"10.1109/LASCAS.2016.7451087","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451087","url":null,"abstract":"This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It uses an input transformer to reduce ground bounce effects and operates around 1 W of output power. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) of 3 branches is separately activated by a 3-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF process and post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 47% under 3.3 V of supply voltage. The 3-bit control allows a total output power dynamic range adjustment of 12.4 dB, divided in 8 steps, with the PAE changing from 13.4% to 47.3%.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124879581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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