Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451058
J. Nieto, M. T. Sanz, N. Medrano-Marqués, B. Calvo
A self-biased current buffer based on the quasi floating gate (QFG) approach to achieve class AB operation is presented in this paper. It was designed in standard 0.18μm CMOS process with 1.8V power supply. The buffer is able to copy an input current range of ±15μA with 8μA bias current. The total harmonic distortion (THD) remains below -84dB for 1 kHz frequency and maximum input current Ipp = 30pA. A comparison with two other class AB architectures in terms of input and output impedances, THD, bandwidth, accuracy and static and dynamic power consumption is also presented.
{"title":"Self-biased class AB CMOS current buffer","authors":"J. Nieto, M. T. Sanz, N. Medrano-Marqués, B. Calvo","doi":"10.1109/LASCAS.2016.7451058","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451058","url":null,"abstract":"A self-biased current buffer based on the quasi floating gate (QFG) approach to achieve class AB operation is presented in this paper. It was designed in standard 0.18μm CMOS process with 1.8V power supply. The buffer is able to copy an input current range of ±15μA with 8μA bias current. The total harmonic distortion (THD) remains below -84dB for 1 kHz frequency and maximum input current Ipp = 30pA. A comparison with two other class AB architectures in terms of input and output impedances, THD, bandwidth, accuracy and static and dynamic power consumption is also presented.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121408653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451083
G. Smaniotto, Joao J. S. Machado, Matheus T. Moreira, A. Ziesemer, F. Marques, L. Rosa
Traditional synthesis flows dedicated to design ASICs typically adopt standard cells approach to generate VLSI circuits. As a consequence, the layouts of these circuits are not fully optimized due to the restricted number of cells present in the library. To solve this problem, ASTRAN, an open source automatic synthesis tool, was developed. This tool generates layouts with unrestricted cell structures and obtains results with similar density compared to state-of-the-art alternatives. A key step on the ASTRAN flow is the transistor folding, which consists in breaking the transistors that exceed the height limit defined in the project rules. This step is executed in ASTRAN only into single transistors. This paper addresses this issue and introduces a new folding methodology that identifies all stacks of transistors series and applies the folding technique for each of these arrangements. The results obtained through this new folding technique show reductions in cell area.
{"title":"Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool","authors":"G. Smaniotto, Joao J. S. Machado, Matheus T. Moreira, A. Ziesemer, F. Marques, L. Rosa","doi":"10.1109/LASCAS.2016.7451083","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451083","url":null,"abstract":"Traditional synthesis flows dedicated to design ASICs typically adopt standard cells approach to generate VLSI circuits. As a consequence, the layouts of these circuits are not fully optimized due to the restricted number of cells present in the library. To solve this problem, ASTRAN, an open source automatic synthesis tool, was developed. This tool generates layouts with unrestricted cell structures and obtains results with similar density compared to state-of-the-art alternatives. A key step on the ASTRAN flow is the transistor folding, which consists in breaking the transistors that exceed the height limit defined in the project rules. This step is executed in ASTRAN only into single transistors. This paper addresses this issue and introduces a new folding methodology that identifies all stacks of transistors series and applies the folding technique for each of these arrangements. The results obtained through this new folding technique show reductions in cell area.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130736837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451061
O. F. Siebel, C. Saraiva, F. J. Ramirez-Fernandez, M. C. Schneider, C. Galup-Montoro
This work presents a low-cost microcontrolled dosimeter based on CD4007 device, a popular off-the-shelf CMOS circuit. This dosimeter is aimed at in vivo radiotherapy applications and combines a simple and accurate readout with a small size, low-cost, and cable-free sensor. The response of this dosimeter to low-dose (10 cGy-1 Gy) and 40 Gy irradiations were tested using X-ray (6 MV).
{"title":"A low-cost microcontrolled dosimeter based on CD4007 devices for in vivo radiotherapy applications","authors":"O. F. Siebel, C. Saraiva, F. J. Ramirez-Fernandez, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/LASCAS.2016.7451061","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451061","url":null,"abstract":"This work presents a low-cost microcontrolled dosimeter based on CD4007 device, a popular off-the-shelf CMOS circuit. This dosimeter is aimed at in vivo radiotherapy applications and combines a simple and accurate readout with a small size, low-cost, and cable-free sensor. The response of this dosimeter to low-dose (10 cGy-1 Gy) and 40 Gy irradiations were tested using X-ray (6 MV).","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115947833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-14DOI: 10.1109/LASCAS.2016.7451050
Azadeh Alsadat Emrani Zarandi, A. S. Molahosseini, L. Sousa, M. Hosseinzadeh, K. Navi
Residue number systems (RNS) are an attractive alternative to conventional weighted number systems for nowadays applications, due to features such as parallelism and low-power consumption. However, a prerequisite for benefiting from these features is to have a suitable design for reverse converters. This paper proposes a practical adder placement method to achieve reverse converters with the desired characteristics based on the target application's requirements and constraints. The presented area-delay-power-aware adder placement method breaks down into four phases. Besides, a linear efficiency function specified for RNS is introduced to choose design with the best trade-off between circuit parameters. The effectiveness of the proposed placement method is experimentally assessed.
{"title":"Area-delay-power-aware adder placement method for RNS reverse converter design","authors":"Azadeh Alsadat Emrani Zarandi, A. S. Molahosseini, L. Sousa, M. Hosseinzadeh, K. Navi","doi":"10.1109/LASCAS.2016.7451050","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451050","url":null,"abstract":"Residue number systems (RNS) are an attractive alternative to conventional weighted number systems for nowadays applications, due to features such as parallelism and low-power consumption. However, a prerequisite for benefiting from these features is to have a suitable design for reverse converters. This paper proposes a practical adder placement method to achieve reverse converters with the desired characteristics based on the target application's requirements and constraints. The presented area-delay-power-aware adder placement method breaks down into four phases. Besides, a linear efficiency function specified for RNS is introduced to choose design with the best trade-off between circuit parameters. The effectiveness of the proposed placement method is experimentally assessed.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125066772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451053
A. Maldonado, G. Huertas, A. Rueda, J. Huertas, P. Pérez, A. Yúfera
A comprehensive system for real-time monitoring of a set of cell-cultures using a Voltage Oscillation (VO) methodology is proposed. The main idea is to connect the bio-electrical elements (electrodes & cell-culture) in such a way that sequentially a suitable electrical oscillator, which only uses a DC power source, is built. Using the employed electrical models given in [1, 2], the attained oscillation parameters (frequency and amplitude) can be directly related to the biological test. A digital circuitry is developed to pick-up the experimental measurements, which are gathered and shown in real-time in a web application.
{"title":"Cell-culture measurements using voltage oscillations","authors":"A. Maldonado, G. Huertas, A. Rueda, J. Huertas, P. Pérez, A. Yúfera","doi":"10.1109/LASCAS.2016.7451053","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451053","url":null,"abstract":"A comprehensive system for real-time monitoring of a set of cell-cultures using a Voltage Oscillation (VO) methodology is proposed. The main idea is to connect the bio-electrical elements (electrodes & cell-culture) in such a way that sequentially a suitable electrical oscillator, which only uses a DC power source, is built. Using the employed electrical models given in [1, 2], the attained oscillation parameters (frequency and amplitude) can be directly related to the biological test. A digital circuitry is developed to pick-up the experimental measurements, which are gathered and shown in real-time in a web application.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126795887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451059
T. R. B. S. Soares, I. F. Silva, L. Melo, O. V. Neto
Field-Coupled nanocomputing alternatives are promising technologies that can outcome the size/energy limitations of CMOS transistors. Nanomagnet Logic (NML) technology is one of their variations, which incorporates processing and memory using single-domain nanomagnets, operating at room temperature with low energy dissipation. While simple NML logic circuits have been experimentally demonstrated recently, considerable less work has been done on the design and simulation of more complex NML circuits. In this paper, we present a tool for the design and simulation of NML circuits, in which the designer is allowed to manually place the magnets in a grid to construct a desired NML circuit. The outputs from the circuit's logic gates are then calculated using a fast tri-state algorithm.
{"title":"A new methodology for design and simulation of NML circuits","authors":"T. R. B. S. Soares, I. F. Silva, L. Melo, O. V. Neto","doi":"10.1109/LASCAS.2016.7451059","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451059","url":null,"abstract":"Field-Coupled nanocomputing alternatives are promising technologies that can outcome the size/energy limitations of CMOS transistors. Nanomagnet Logic (NML) technology is one of their variations, which incorporates processing and memory using single-domain nanomagnets, operating at room temperature with low energy dissipation. While simple NML logic circuits have been experimentally demonstrated recently, considerable less work has been done on the design and simulation of more complex NML circuits. In this paper, we present a tool for the design and simulation of NML circuits, in which the designer is allowed to manually place the magnets in a grid to construct a desired NML circuit. The outputs from the circuit's logic gates are then calculated using a fast tri-state algorithm.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123731431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451020
A. Sarmiento-Reyes, Jesús Jiménez-León, L. Hernández-Martínez, H. Vázquez-Leal
With the fabrication of the nanometric memristor in 2008, a large number of applications in electronic design have been devised for the new device. Despite the current problems involved in its fabrication, the memristor is considered to be the basic circuit cell for the development of modern electronic systems. Unquestionably, it is necessary to develop circuit design verification methodologies and CAD tools for circuits containing memristors as well as traditional electronics. In this paper, we present a circuit simulation methodology for the electrical simulation of memristive circuits. The methodology results in a nonlinear constitutive branch relationship for the memristor that can be straightforwardly combined with models for traditional components in a standard industry package for electrical simulation.
{"title":"A CAD-oriented simulation methodology for memristive circuits","authors":"A. Sarmiento-Reyes, Jesús Jiménez-León, L. Hernández-Martínez, H. Vázquez-Leal","doi":"10.1109/LASCAS.2016.7451020","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451020","url":null,"abstract":"With the fabrication of the nanometric memristor in 2008, a large number of applications in electronic design have been devised for the new device. Despite the current problems involved in its fabrication, the memristor is considered to be the basic circuit cell for the development of modern electronic systems. Unquestionably, it is necessary to develop circuit design verification methodologies and CAD tools for circuits containing memristors as well as traditional electronics. In this paper, we present a circuit simulation methodology for the electrical simulation of memristive circuits. The methodology results in a nonlinear constitutive branch relationship for the memristor that can be straightforwardly combined with models for traditional components in a standard industry package for electrical simulation.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126523695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451054
Lucas Santis, Ronald Valenzuela
A method for early estimation of optimum bulk bias potential is proposed. The suggested strategy removes the requirement for synthesis based exploration, greatly reducing Turn Around Time (TAT). As the core of the method, we present a linear model for estimating the Energy Delay Product (EDP), which relies on characterization of Static and Dynamic Energy, as well as Delay for a single Inverter cell under different bulk bias operating conditions. This model weights these vectors using design constraint parameters such as switching activity and clock period. We have validated the model by means of statistical analysis. The method was then tested by comparison of Quality of Results (QoR) obtained from implementation of an open source System on a Chip (SoC) design, first using our predicted bias voltages and then using an estimate of the optimum found by exploration over a post layout annotated Netlist. Our method has achieved a 6.3% of improvement on EDP with a very low TAT.
{"title":"A method for quick estimation of optimum bulk bias voltages for SoC designs","authors":"Lucas Santis, Ronald Valenzuela","doi":"10.1109/LASCAS.2016.7451054","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451054","url":null,"abstract":"A method for early estimation of optimum bulk bias potential is proposed. The suggested strategy removes the requirement for synthesis based exploration, greatly reducing Turn Around Time (TAT). As the core of the method, we present a linear model for estimating the Energy Delay Product (EDP), which relies on characterization of Static and Dynamic Energy, as well as Delay for a single Inverter cell under different bulk bias operating conditions. This model weights these vectors using design constraint parameters such as switching activity and clock period. We have validated the model by means of statistical analysis. The method was then tested by comparison of Quality of Results (QoR) obtained from implementation of an open source System on a Chip (SoC) design, first using our predicted bias voltages and then using an estimate of the optimum found by exploration over a post layout annotated Netlist. Our method has achieved a 6.3% of improvement on EDP with a very low TAT.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127826249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451090
Tiago Schiavon, Guilherme Paim, M. Fonseca, E. Costa, S. Almeida
This paper proposes the use of efficient adder compressors for the power-efficient 2-D Discrete Cosine Transform (DCT) implementation. Due to the increasing use of the discrete transforms in image compression, and its dedicated hardware design, the search for efficient and fast approaches to the DCTs reached a special place in the state-of-art researches. The DCT is an approximation of the cosine function, whose resultant matrix is only composed of 0 and 1 values. Therefore, the DCT can be easily implemented using only adders and subtractors rather than general purpose multipliers. In this work we use combinations of efficient 4-2 and 8-2 adder compressors for the state-of-the approximate DCT implementations. The approximate DCT performance combined with its lower computational effort makes this transform an excellent choice to be applied to dedicated hardware for image compression. We present an environment for the synthesis of the DCTs in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the hardwired state-of-the-art approximate DCT solutions, with adder compressors, minimizes both cells area and power consumption with good overall quality images.
{"title":"Exploiting adder compressors for power-efficient 2-D approximate DCT realization","authors":"Tiago Schiavon, Guilherme Paim, M. Fonseca, E. Costa, S. Almeida","doi":"10.1109/LASCAS.2016.7451090","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451090","url":null,"abstract":"This paper proposes the use of efficient adder compressors for the power-efficient 2-D Discrete Cosine Transform (DCT) implementation. Due to the increasing use of the discrete transforms in image compression, and its dedicated hardware design, the search for efficient and fast approaches to the DCTs reached a special place in the state-of-art researches. The DCT is an approximation of the cosine function, whose resultant matrix is only composed of 0 and 1 values. Therefore, the DCT can be easily implemented using only adders and subtractors rather than general purpose multipliers. In this work we use combinations of efficient 4-2 and 8-2 adder compressors for the state-of-the approximate DCT implementations. The approximate DCT performance combined with its lower computational effort makes this transform an excellent choice to be applied to dedicated hardware for image compression. We present an environment for the synthesis of the DCTs in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the hardwired state-of-the-art approximate DCT solutions, with adder compressors, minimizes both cells area and power consumption with good overall quality images.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127104607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a multi-phase Direct Digital Synthesizer (DDS) based Digital to Time Converter (DTC), for application in fractional-N Digital Phase Locked Loops (DPLLs). The proposed DTC employs (i) multiple DDSs operating with incremental delay for reduced quantization step size, and (ii) a phase-advanced ROM in these DDSs for correct waveform extrapolation. The incrementally delayed output from multiple DDSs allows reduction in harmonics associated with the quantized steps, and the look-ahead feature of phase advanced ROM allows DTC operation even at the Nyquist rate. The DTC, designed in 65 nm CMOS-LL technology, achieves 1.2 ps jitter with 10 mW power consumption, while operating at 4.8 GHz input frequency. Also, the fractional-N DPLL employing the proposed multi-phase DDS based DTC in its feedback path is able to attain -341 dB as Figure of Merit, which is the best amongst the published results, with a very low settling time-jitter product.
{"title":"A low-jitter digital-to-time converter with look-ahead multi-phase DDS","authors":"Harishankar Sahu, Pallavi Paliwal, Vivek Yadav, Shalabh Gupta","doi":"10.1109/LASCAS.2016.7451049","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451049","url":null,"abstract":"We propose a multi-phase Direct Digital Synthesizer (DDS) based Digital to Time Converter (DTC), for application in fractional-N Digital Phase Locked Loops (DPLLs). The proposed DTC employs (i) multiple DDSs operating with incremental delay for reduced quantization step size, and (ii) a phase-advanced ROM in these DDSs for correct waveform extrapolation. The incrementally delayed output from multiple DDSs allows reduction in harmonics associated with the quantized steps, and the look-ahead feature of phase advanced ROM allows DTC operation even at the Nyquist rate. The DTC, designed in 65 nm CMOS-LL technology, achieves 1.2 ps jitter with 10 mW power consumption, while operating at 4.8 GHz input frequency. Also, the fractional-N DPLL employing the proposed multi-phase DDS based DTC in its feedback path is able to attain -341 dB as Figure of Merit, which is the best amongst the published results, with a very low settling time-jitter product.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128836161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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