Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451055
Ana Mativi, Eduarda Monteiro, S. Bampi
In this work we present a framework that profiles HEVC (High Efficiency Video Coding) encoders modules focusing on cache memory performance and energy. This framework considers the HEVC reference software (HM) and analyzes the impact of some coding parameters on the cache hierarchy. HEVC was proposed in 2013, presenting new video coding techniques to deal with the demand for higher resolutions. The tools included in the HEVC increase significantly the computational effort and energy consumption required to encode videos when compared to its predecessor, H.264/AVC. For this analysis we used the proposed framework MAP-HEVC (Memory Access Profiling for HEVC) considering seven different video coding configurations and four video resolutions. In the prediction module, the results showed that using Full Search (FS) results in 75% more accesses than using Test Zonal (TZ) Search. The results also suggest that using 16×16 search ranges is a very viable option to reduce the memory accesses achieving a better compression. For the residual coding, the Rate-Distortion Optimized Quantization (RDOQ) was evaluated and our analysis showed that this tool adds 10% more accesses to the memory.
{"title":"Memory access profiling for HEVC encoders","authors":"Ana Mativi, Eduarda Monteiro, S. Bampi","doi":"10.1109/LASCAS.2016.7451055","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451055","url":null,"abstract":"In this work we present a framework that profiles HEVC (High Efficiency Video Coding) encoders modules focusing on cache memory performance and energy. This framework considers the HEVC reference software (HM) and analyzes the impact of some coding parameters on the cache hierarchy. HEVC was proposed in 2013, presenting new video coding techniques to deal with the demand for higher resolutions. The tools included in the HEVC increase significantly the computational effort and energy consumption required to encode videos when compared to its predecessor, H.264/AVC. For this analysis we used the proposed framework MAP-HEVC (Memory Access Profiling for HEVC) considering seven different video coding configurations and four video resolutions. In the prediction module, the results showed that using Full Search (FS) results in 75% more accesses than using Test Zonal (TZ) Search. The results also suggest that using 16×16 search ranges is a very viable option to reduce the memory accesses achieving a better compression. For the residual coding, the Rate-Distortion Optimized Quantization (RDOQ) was evaluated and our analysis showed that this tool adds 10% more accesses to the memory.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131951781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451022
Sergio Chaparro, J. Carrillo, H. Alarcon
A temperature sensor used to compensate the crystal oscillator frequency instability of a real time clock (RTC) is proposed in this paper. The sensor utilizes the difference of a current proportional to the absolute temperature (PTAT) and another complementary to the absolute temperature (CTAT), generating a high-slope PTAT voltage with minimum value close to zero. The introduced approach provides a voltage signal range that reduces the power and area consumption of a 7-bit successive approximation analog-to-digital converter (SAR-ADC). The principles of the circuit topology alongside the simulation results of corners and Monte Carlo analyzes are presented. A prototype is fabricated in a 0.18 μm CMOS technology and experimental results showed a temperature inaccuracy of -0.812 to 0.266 °C, with an average resolution of 18.01 mV/°C, using a one-point calibration within the range of 0 to 40 °C. The sensor features an area of 0.08 mm2 and consumes less than 73.8 μW from a 1.8 V voltage supply.
{"title":"A high-slope PTAT temperature sensor for frequency compensation of an RTC oscillator","authors":"Sergio Chaparro, J. Carrillo, H. Alarcon","doi":"10.1109/LASCAS.2016.7451022","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451022","url":null,"abstract":"A temperature sensor used to compensate the crystal oscillator frequency instability of a real time clock (RTC) is proposed in this paper. The sensor utilizes the difference of a current proportional to the absolute temperature (PTAT) and another complementary to the absolute temperature (CTAT), generating a high-slope PTAT voltage with minimum value close to zero. The introduced approach provides a voltage signal range that reduces the power and area consumption of a 7-bit successive approximation analog-to-digital converter (SAR-ADC). The principles of the circuit topology alongside the simulation results of corners and Monte Carlo analyzes are presented. A prototype is fabricated in a 0.18 μm CMOS technology and experimental results showed a temperature inaccuracy of -0.812 to 0.266 °C, with an average resolution of 18.01 mV/°C, using a one-point calibration within the range of 0 to 40 °C. The sensor features an area of 0.08 mm2 and consumes less than 73.8 μW from a 1.8 V voltage supply.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451033
Ouajdi Brini, M. Boukadoum
Since the emergence of large public networks in the 80's, wireless communication protocols have been evolving constantly, forcing frequent changes to the hardware of base stations. This has triggered a lot of research about implementing network functions in software, especially those of the physical layer, in order to allow the use of generic processors in the base stations. However, achieving this goal requires very fast hardware to maintain real time operation. In this work, we describe a hardware system that combines a desktop CPU with a GPU for real time frame demodulation in the LTE protocol physical layer. Our experiments with worst-case LTE frames show that the making of a software-based LTE frame processor that operates in real time is possible with general-purpose hardware architectures such as the one described, thus opening the door for upscaling to complete base stations.
{"title":"Real-time CPU-GPU demodulator for the LTE physical layer","authors":"Ouajdi Brini, M. Boukadoum","doi":"10.1109/LASCAS.2016.7451033","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451033","url":null,"abstract":"Since the emergence of large public networks in the 80's, wireless communication protocols have been evolving constantly, forcing frequent changes to the hardware of base stations. This has triggered a lot of research about implementing network functions in software, especially those of the physical layer, in order to allow the use of generic processors in the base stations. However, achieving this goal requires very fast hardware to maintain real time operation. In this work, we describe a hardware system that combines a desktop CPU with a GPU for real time frame demodulation in the LTE protocol physical layer. Our experiments with worst-case LTE frames show that the making of a software-based LTE frame processor that operates in real time is possible with general-purpose hardware architectures such as the one described, thus opening the door for upscaling to complete base stations.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451092
A. Perez-Fajardo, D. M. Cortés-Hernández, R. Torres‐Torres, A. Torres-Jácome
In this work a method for characterization of transmission line (TL) in high-frequency laminates is proposed. The method is performed in a novel PCB laminate based in PTFE for high-frequency applications with low conductor roughness (hrms) and low loss tangent (tanδ). In order to apply the characterization method, S-parameters were taken up to 30 GHz in a microstrip interconnect. Time domain simulation was performed to validate the model, showing good agreement with experimental results.
{"title":"Characterization of transmission lines in a novel high-frequency laminate","authors":"A. Perez-Fajardo, D. M. Cortés-Hernández, R. Torres‐Torres, A. Torres-Jácome","doi":"10.1109/LASCAS.2016.7451092","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451092","url":null,"abstract":"In this work a method for characterization of transmission line (TL) in high-frequency laminates is proposed. The method is performed in a novel PCB laminate based in PTFE for high-frequency applications with low conductor roughness (hrms) and low loss tangent (tanδ). In order to apply the characterization method, S-parameters were taken up to 30 GHz in a microstrip interconnect. Time domain simulation was performed to validate the model, showing good agreement with experimental results.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"716 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122571317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451082
L. S. Pereira, D. Suzuki
This article aims to analyze the pore formation in the plasma and nuclear membranes of a single biological cell during the electroporation process. For this purpose, were studied mathematical models of electroporation and electrical pulse characteristics, in order to analyze the influence of variations in the amplitude and duration. Thus, it seeks to obtain configurations that provide better results and less damage to the structure of the cell membrane during the electroporation process.
{"title":"Effects of nanoelectroporation on plasma and nuclear membranes","authors":"L. S. Pereira, D. Suzuki","doi":"10.1109/LASCAS.2016.7451082","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451082","url":null,"abstract":"This article aims to analyze the pore formation in the plasma and nuclear membranes of a single biological cell during the electroporation process. For this purpose, were studied mathematical models of electroporation and electrical pulse characteristics, in order to analyze the influence of variations in the amplitude and duration. Thus, it seeks to obtain configurations that provide better results and less damage to the structure of the cell membrane during the electroporation process.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122715321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451088
Gustavo Ott, E. Costa, S. Almeida, M. Fonseca
Digital filters are widely used in digital systems, which can make use of integer arithmetic to achieve higher performance. The use of integer operands can compromise the filter operation, due to the inherently error caused by truncation operations. Addressing this kind of problem, we propose an IIR filter for biomedical signals using the truncation error feedback (TEF), in which a feedback signal is obtained from the division remainder of the truncation operation. Two dedicated fully-sequential and parallel architectures were implemented and simulated using VHDL language, and synthesized in Cadence environment using the 45 nm Nangate Open Cell Library. A simulated ECG signal was used as input to verify the functionality of an IIR high pass filter with TEF. The results of our analysis indicate that the use of TEF can be an important approach in digital systems, where integer arithmetic for computation is adequate for performance requirements. Using this feedback signal, the design specifications of the filter remained significantly the same compared to the filter specification, independently of the cut-off and sample frequency ratio.
数字滤波器广泛应用于数字系统中，它可以利用整数运算来获得更高的性能。整数操作数的使用可能会影响过滤器操作，因为截断操作会导致固有的错误。针对这类问题，我们提出了一种使用截断误差反馈(TEF)的生物医学信号IIR滤波器，其中从截断运算的除法余数中获得反馈信号。采用VHDL语言实现和模拟了两个专用的全顺序和并行架构，并在Cadence环境下使用45 nm的Nangate Open Cell Library进行了合成。采用模拟心电信号作为输入，验证了带TEF的IIR高通滤波器的功能。我们的分析结果表明，在数字系统中，使用TEF可以是一种重要的方法，其中用于计算的整数算法足以满足性能要求。使用该反馈信号，与截止频率和采样频率比无关，滤波器的设计规格与滤波器规格保持明显相同。
{"title":"Exploiting architectural solutions for IIR filter architecture with truncation error feedback","authors":"Gustavo Ott, E. Costa, S. Almeida, M. Fonseca","doi":"10.1109/LASCAS.2016.7451088","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451088","url":null,"abstract":"Digital filters are widely used in digital systems, which can make use of integer arithmetic to achieve higher performance. The use of integer operands can compromise the filter operation, due to the inherently error caused by truncation operations. Addressing this kind of problem, we propose an IIR filter for biomedical signals using the truncation error feedback (TEF), in which a feedback signal is obtained from the division remainder of the truncation operation. Two dedicated fully-sequential and parallel architectures were implemented and simulated using VHDL language, and synthesized in Cadence environment using the 45 nm Nangate Open Cell Library. A simulated ECG signal was used as input to verify the functionality of an IIR high pass filter with TEF. The results of our analysis indicate that the use of TEF can be an important approach in digital systems, where integer arithmetic for computation is adequate for performance requirements. Using this feedback signal, the design specifications of the filter remained significantly the same compared to the filter specification, independently of the cut-off and sample frequency ratio.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114569711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451037
Renato H. Neuenfeld, M. Fonseca, E. Costa
In the FFT computation, the butterflies play a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this paper different and dedicated structures for the 16 bit-width radix-2 and radix-4 DIT butterflies are implemented, where the main goal is to minimize the number of arithmetic operators in order to produce power-efficient structures. Firstly, we improve a radix-2 butterfly previously presented in literature, reducing one adder and one subtractor in the structure. After that, part of this optimized radix-2 butterfly is used to reduce the number of real multipliers in the radix-4 butterfly. The main results show that the optimization guarantees reduced power consumption for radix-2 butterfly, when compared with previous works from the literature. Moreover, the use of part of the optimized radix-2 into the radix-4 structure leads to the reduction of power consumption for this structure.
{"title":"Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time","authors":"Renato H. Neuenfeld, M. Fonseca, E. Costa","doi":"10.1109/LASCAS.2016.7451037","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451037","url":null,"abstract":"In the FFT computation, the butterflies play a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this paper different and dedicated structures for the 16 bit-width radix-2 and radix-4 DIT butterflies are implemented, where the main goal is to minimize the number of arithmetic operators in order to produce power-efficient structures. Firstly, we improve a radix-2 butterfly previously presented in literature, reducing one adder and one subtractor in the structure. After that, part of this optimized radix-2 butterfly is used to reduce the number of real multipliers in the radix-4 butterfly. The main results show that the optimization guarantees reduced power consumption for radix-2 butterfly, when compared with previous works from the literature. Moreover, the use of part of the optimized radix-2 into the radix-4 structure leads to the reduction of power consumption for this structure.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127986987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451080
M. Cardoso, Regis Zanandrea, R. S. Souza, Joao J. S. Machado, L. Rosa, F. Marques
Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts directly in the layout. This paper presents a methodology to identify these aspects in order to guide the cell layout generation. The results were performed over a set of intensively used benchmarks and pointed that 67.69% of the investigated networks presents a planar topology, while 21.85% shows a different number of transistors between its logic plans and 93.73% of the physical cells will contain at least one gap in its diffusion areas.
{"title":"Topological characteristics of logic networks generated by a graph-based methodology","authors":"M. Cardoso, Regis Zanandrea, R. S. Souza, Joao J. S. Machado, L. Rosa, F. Marques","doi":"10.1109/LASCAS.2016.7451080","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451080","url":null,"abstract":"Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts directly in the layout. This paper presents a methodology to identify these aspects in order to guide the cell layout generation. The results were performed over a set of intensively used benchmarks and pointed that 67.69% of the investigated networks presents a planar topology, while 21.85% shows a different number of transistors between its logic plans and 93.73% of the physical cells will contain at least one gap in its diffusion areas.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122047214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451068
F. Balasa, I. Luican, Hongwei Zhu
The signal processing algorithms are typically described in a high-level programming language. In data-dominated applications, particularly in the multimedia and telecommunication domains, the code of these behavioral specifications is organized in sequences of loop nests; the main data structures are multidimensional arrays. This paper proposes a memory management algorithm for mapping multidimensional signals (arrays) to the physical memories. The proposed technique is well-suited to a dynamic multithreading implementation, which makes it computationally efficient. Another advantage is that it can be applied to multi-layer memory hierarchies, which makes it particularly useful in embedded systems design.
{"title":"Parallel algorithm mapping to memory multidimensional signals","authors":"F. Balasa, I. Luican, Hongwei Zhu","doi":"10.1109/LASCAS.2016.7451068","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451068","url":null,"abstract":"The signal processing algorithms are typically described in a high-level programming language. In data-dominated applications, particularly in the multimedia and telecommunication domains, the code of these behavioral specifications is organized in sequences of loop nests; the main data structures are multidimensional arrays. This paper proposes a memory management algorithm for mapping multidimensional signals (arrays) to the physical memories. The proposed technique is well-suited to a dynamic multithreading implementation, which makes it computationally efficient. Another advantage is that it can be applied to multi-layer memory hierarchies, which makes it particularly useful in embedded systems design.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116783855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451051
Andres M. A. Valdes, V. Possani, F. Marranghello, A. Reis, R. Ribas
MOS planar technology has been used in fabrication of integrated circuits in the last decades. However, the short channel effects in the subthreshold operation region are becoming a critical restriction to the channel length reduction. With the use of FinFET devices, the scaling increases due the reduction of short channel effects. FinFET offers the possibility of independent gate controlling that can be efficiently exploited in logic reduction (network optimization), but with direct impact in the electrical performance of logic gates. In this work, it is presented the electrical analysis in terms of signal delay propagation and energy consumption of compacted transistor networks. Different logic gate implementations corresponding to the same Boolean function behavior are compared. The results demonstrate the existing tradeoff between these two parameters.
{"title":"Performance evaluation of optimized transistor networks built using independent-gate FinFET","authors":"Andres M. A. Valdes, V. Possani, F. Marranghello, A. Reis, R. Ribas","doi":"10.1109/LASCAS.2016.7451051","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451051","url":null,"abstract":"MOS planar technology has been used in fabrication of integrated circuits in the last decades. However, the short channel effects in the subthreshold operation region are becoming a critical restriction to the channel length reduction. With the use of FinFET devices, the scaling increases due the reduction of short channel effects. FinFET offers the possibility of independent gate controlling that can be efficiently exploited in logic reduction (network optimization), but with direct impact in the electrical performance of logic gates. In this work, it is presented the electrical analysis in terms of signal delay propagation and energy consumption of compacted transistor networks. Different logic gate implementations corresponding to the same Boolean function behavior are compared. The results demonstrate the existing tradeoff between these two parameters.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129673601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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