Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451007
Luis Gustavo Perpetuo Costa Marques, M. H. D. Queiroz, J. Farines
In this paper we present a synthesizable VHDL design methodology that includes exhaustive verification of properties. The work was developed in a company environment with the goal of increasing reliability of products and reduce time of verification procedure. In this methodology the properties are represented using VHDL oriented patterns based on the OVL library and applied, with the VHDL code, into a verification environment (based on open source tools) that returns the results. Counterexamples are generated for properties that failed and returned as VHDL testbench, allowing the user to identify the faulty behavior with simulation. The methodology is illustrated with a simple memory controller application.
{"title":"Improving a design methodology of synthesizable VHDL with formal verification","authors":"Luis Gustavo Perpetuo Costa Marques, M. H. D. Queiroz, J. Farines","doi":"10.1109/LASCAS.2016.7451007","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451007","url":null,"abstract":"In this paper we present a synthesizable VHDL design methodology that includes exhaustive verification of properties. The work was developed in a company environment with the goal of increasing reliability of products and reduce time of verification procedure. In this methodology the properties are represented using VHDL oriented patterns based on the OVL library and applied, with the VHDL code, into a verification environment (based on open source tools) that returns the results. Counterexamples are generated for properties that failed and returned as VHDL testbench, allowing the user to identify the faulty behavior with simulation. The methodology is illustrated with a simple memory controller application.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120949896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451041
R. Sanchez, Benjamín T. Reyes, Ariel L. Pola, M. Hueda
This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implement the transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm.
{"title":"An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems","authors":"R. Sanchez, Benjamín T. Reyes, Ariel L. Pola, M. Hueda","doi":"10.1109/LASCAS.2016.7451041","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451041","url":null,"abstract":"This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time, gain, offset, and frequency response among the interleaves of a TI-ADC limit the performance of the converter unless they are compensated. Typically, long computer simulation run time is required to evaluate the performance of mixed-signal calibration algorithms. We show that the FPGA-based system described in this paper drastically reduces the emulation time by more than hundreds of magnitude orders. The proposed FPGA framework includes: (i) a diagnostic and control unit built upon an embedded processor NIOSII, (ii) DSP blocks to implement the transmitter and the receiver, and (iii) a Gaussian number generator to emulate the noise channel component. Experimental results with a 2 GS/s 6-bit CMOS TI-ADC demonstrate the excellent capability of the implemented FPGA-based emulator to evaluate the performance of a mixed-signal calibration algorithm.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124582736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451077
Bruno Bellini, A. Arnaud, Stephania Rezk, Maximiliano Chiossi
H-Bridges are well known circuits to connect a load to a DC supply in both forward/reverse bias. These circuits are commonly used to drive DC and stepper motors among many other power electronics applications. In this work, a fully integrated 12V H-Bridge is designed in a 0.6μm HV technology as a replacement of an obsolete commercial part. The main objective is to provide an OEM in Uruguay with a flexible and low cost substitute of an off the shelf IC currently utilized on its products, that is being discontinued. The new H-Bridge was designed for the same package and improves some characteristics like power consumption, maximum switching frequency, over the old one. Because the cost is a major constrain to reach production stage in this project, the silicon area was reduced as much as possible. The resulting circuit is a low cost 12 V H-Bridge, with a logic input `1' down to 2.8V, switching up to 300kHz, in a 1.8mm2 die area.
{"title":"An integrated H-bridge circuit in a HV technology","authors":"Bruno Bellini, A. Arnaud, Stephania Rezk, Maximiliano Chiossi","doi":"10.1109/LASCAS.2016.7451077","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451077","url":null,"abstract":"H-Bridges are well known circuits to connect a load to a DC supply in both forward/reverse bias. These circuits are commonly used to drive DC and stepper motors among many other power electronics applications. In this work, a fully integrated 12V H-Bridge is designed in a 0.6μm HV technology as a replacement of an obsolete commercial part. The main objective is to provide an OEM in Uruguay with a flexible and low cost substitute of an off the shelf IC currently utilized on its products, that is being discontinued. The new H-Bridge was designed for the same package and improves some characteristics like power consumption, maximum switching frequency, over the old one. Because the cost is a major constrain to reach production stage in this project, the silicon area was reduced as much as possible. The resulting circuit is a low cost 12 V H-Bridge, with a logic input `1' down to 2.8V, switching up to 300kHz, in a 1.8mm2 die area.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124832968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451052
Rafael Tolentino-Rabelo, Daniel M. Muñoz Arboleda
This work proposes a Field Programmable Gate Array implementation of a multilayer perceptron neural network for terrain classification. A 3-axis accelerometer was used for acquiring the acceleration variation that a robot suffers when moving on four different terrains: sand, asphalt, grass and soil. A multilayer perceptron neural network was trained in order to perform the classification process. Afterward, the trained weights and biases were used to implement in hardware the mathematical model of the proposed network. The implemented circuits were characterized in terms of the hardware resources consumption, operational frequency and power consumption. Numerical comparisons between hardware and software results were used in order to validate the hardware implementation and to estimate the classification error. In addition, an execution time comparison using three software-based embedded platforms was performed.
{"title":"Online terrain classification for mobile robots using FPGAs","authors":"Rafael Tolentino-Rabelo, Daniel M. Muñoz Arboleda","doi":"10.1109/LASCAS.2016.7451052","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451052","url":null,"abstract":"This work proposes a Field Programmable Gate Array implementation of a multilayer perceptron neural network for terrain classification. A 3-axis accelerometer was used for acquiring the acceleration variation that a robot suffers when moving on four different terrains: sand, asphalt, grass and soil. A multilayer perceptron neural network was trained in order to perform the classification process. Afterward, the trained weights and biases were used to implement in hardware the mathematical model of the proposed network. The implemented circuits were characterized in terms of the hardware resources consumption, operational frequency and power consumption. Numerical comparisons between hardware and software results were used in order to validate the hardware implementation and to estimate the classification error. In addition, an execution time comparison using three software-based embedded platforms was performed.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122860053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451086
A. K. Sinha, R. L. Radin, D. Caviglia, C. Galup-Montoro, M. C. Schneider
In this paper, we present measurement results from a prototype chip (fabricated in 130 nm CMOS technology), designed to extract maximum power from a Thermoelectric Generator (TEG). From analytical expression, we prove that the maximum extracted power is around 75% of the available power in a TEG, without using a closed loop maximum peak power tracking to regulate the input voltage. In our measurements, the TEG is modeled by a voltage source (50mV-200mV) with a series resistance of 5 Ohms. The prototype is fully electric, starts from 50 mV and can extract 60% (at 50 mV) to 65% (at 200 mV) of the available power. Hence the measurement result closely agrees with the analytical expression.
{"title":"An energy harvesting chip designed to extract maximum power from a TEG","authors":"A. K. Sinha, R. L. Radin, D. Caviglia, C. Galup-Montoro, M. C. Schneider","doi":"10.1109/LASCAS.2016.7451086","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451086","url":null,"abstract":"In this paper, we present measurement results from a prototype chip (fabricated in 130 nm CMOS technology), designed to extract maximum power from a Thermoelectric Generator (TEG). From analytical expression, we prove that the maximum extracted power is around 75% of the available power in a TEG, without using a closed loop maximum peak power tracking to regulate the input voltage. In our measurements, the TEG is modeled by a voltage source (50mV-200mV) with a series resistance of 5 Ohms. The prototype is fully electric, starts from 50 mV and can extract 60% (at 50 mV) to 65% (at 200 mV) of the available power. Hence the measurement result closely agrees with the analytical expression.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129943100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451018
S. J. Filho, Matheus T. Moreira, Ney Laert Vilar Calazans, Fabiano Hessel
This paper presents HF-RISC, a 32-bit RISC processor, along with its associated programming toolchain. The instruction set architecture of the processor is based on MIPS I and its hardware organization comprises three pipeline stages. The processor was synthesized in four different technology nodes for maximum frequency and simulated using CoreMark, an industry-standard performance evaluation benchmark. Using data obtained from synthesis and benchmarking we analyze the processor performance and compare it to similar commercial products. Obtained results indicate that HF-RISC is a good option for embedded design, as it presents performance figures similar to state-of-the-art ARM processors. Furthermore, its partially reconfigurable hardware organization allows the designer to explore performance and area trade offs.
{"title":"The HF-RISC processor: Performance assessment","authors":"S. J. Filho, Matheus T. Moreira, Ney Laert Vilar Calazans, Fabiano Hessel","doi":"10.1109/LASCAS.2016.7451018","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451018","url":null,"abstract":"This paper presents HF-RISC, a 32-bit RISC processor, along with its associated programming toolchain. The instruction set architecture of the processor is based on MIPS I and its hardware organization comprises three pipeline stages. The processor was synthesized in four different technology nodes for maximum frequency and simulated using CoreMark, an industry-standard performance evaluation benchmark. Using data obtained from synthesis and benchmarking we analyze the processor performance and compare it to similar commercial products. Obtained results indicate that HF-RISC is a good option for embedded design, as it presents performance figures similar to state-of-the-art ARM processors. Furthermore, its partially reconfigurable hardware organization allows the designer to explore performance and area trade offs.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124411834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451064
G. Cardoso, T. Balen
This paper presents an investigation regarding the model adopted by a commercial layout extraction tool to estimate the aspect ratio (W/L) of enclosed layout transistors (ELT). The method used by the EDA (Electronic Design Automation) tool to obtain an equivalent W/L is compared with well know mathematical models presented on the literature. The influences in the aspect ratio estimation regarding designer-controlled layout variables are also target of investigation. Results indicate that the EDA tool analyzed in this work, overestimates the extraction of aspect ratio from ELT layout, when compared with a more accurate mathematical model used to calculate the effective aspect ratio of square ELT devices. The results also show that designer-controlled layout variables may contribute to increase the divergences among the extraction tool method and the studied models in the estimation of the ELT aspect ratio.
{"title":"Study of layout extraction accuracy on W/L estimation of ELT in analog design flow","authors":"G. Cardoso, T. Balen","doi":"10.1109/LASCAS.2016.7451064","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451064","url":null,"abstract":"This paper presents an investigation regarding the model adopted by a commercial layout extraction tool to estimate the aspect ratio (W/L) of enclosed layout transistors (ELT). The method used by the EDA (Electronic Design Automation) tool to obtain an equivalent W/L is compared with well know mathematical models presented on the literature. The influences in the aspect ratio estimation regarding designer-controlled layout variables are also target of investigation. Results indicate that the EDA tool analyzed in this work, overestimates the extraction of aspect ratio from ELT layout, when compared with a more accurate mathematical model used to calculate the effective aspect ratio of square ELT devices. The results also show that designer-controlled layout variables may contribute to increase the divergences among the extraction tool method and the studied models in the estimation of the ELT aspect ratio.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126617102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451056
H. Yamauchi, Worawit Somha
This paper demonstrates a blind deconvolution technique for decoupling the two variation factors caused by the Random Telegraph Noise (RTN) and the Random Dopant Fluctuation (RDF). Unlike the non-blind deconvolution, the blind deconvolution has to seek both of the two unknown factors for RTN and RDF simultaneously, given only the information about the overall SRAM margin distribution. This paper proposes a new filter design technique for the Richardson-Lucy (R-L) blind deconvolutions. This allows to enjoy the benefits of the R-L algorithm while avoiding the inherent pitfall or ringing errors even in the blind deconvolution. The relative errors of the blind-deconvolution for RDF and RTN are reduced to less than 1% within only 300-iteration cycles. This is 400-times shorter than the conventional one.
{"title":"A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations","authors":"H. Yamauchi, Worawit Somha","doi":"10.1109/LASCAS.2016.7451056","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451056","url":null,"abstract":"This paper demonstrates a blind deconvolution technique for decoupling the two variation factors caused by the Random Telegraph Noise (RTN) and the Random Dopant Fluctuation (RDF). Unlike the non-blind deconvolution, the blind deconvolution has to seek both of the two unknown factors for RTN and RDF simultaneously, given only the information about the overall SRAM margin distribution. This paper proposes a new filter design technique for the Richardson-Lucy (R-L) blind deconvolutions. This allows to enjoy the benefits of the R-L algorithm while avoiding the inherent pitfall or ringing errors even in the blind deconvolution. The relative errors of the blind-deconvolution for RDF and RTN are reduced to less than 1% within only 300-iteration cycles. This is 400-times shorter than the conventional one.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126105262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-01-28DOI: 10.1109/LASCAS.2016.7451017
Martha Johanna Sepúlveda, Daniel Flórez, Mathias Soeken, J. Diguet, G. Gogniat
Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infect IPs and open doors to perform timing attacks. By monitoring the Network-on-Chip (NoC) traffic, an attacker is able to spy sensitive information such as secret keys. Previous works have shown that NoC routers can be used to avoid timing attacks. However, such approaches may lead to overall system performance degradation. In this paper we propose SER, a secure enhanced router architecture that dynamically configures the router memory space according to the communication and security properties of the traffic. Timing attacks are avoided by turning the attacker oblivious of the sensitive traffic. We evaluate the security, performance and cost of our approach. We show that our architecture is able to secure paths during runtime while adding only low cost and performance penalties to the MPSoC.
{"title":"Dynamic NoC buffer allocation for MPSoC timing side channel attack protection","authors":"Martha Johanna Sepúlveda, Daniel Flórez, Mathias Soeken, J. Diguet, G. Gogniat","doi":"10.1109/LASCAS.2016.7451017","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451017","url":null,"abstract":"Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infect IPs and open doors to perform timing attacks. By monitoring the Network-on-Chip (NoC) traffic, an attacker is able to spy sensitive information such as secret keys. Previous works have shown that NoC routers can be used to avoid timing attacks. However, such approaches may lead to overall system performance degradation. In this paper we propose SER, a secure enhanced router architecture that dynamically configures the router memory space according to the communication and security properties of the traffic. Timing attacks are avoided by turning the attacker oblivious of the sensitive traffic. We evaluate the security, performance and cost of our approach. We show that our architecture is able to secure paths during runtime while adding only low cost and performance penalties to the MPSoC.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132093124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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