Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451027
Sreenil Saha, F. Lesage, M. Sawan
In this paper we have developed an ultrafast pulse generator to turn on a Single Photon Avalanche Diode (SPAD) sensor with picosecond resolution, at specific time windows. The pulse amplitude and duration is user tunable to provide a variable excess bias voltage to the detector. The transition times (rise and fall time) of the pulse is in the range of 250 to 550 ps depending on the amplitude. The generator was designed to be applied in reflectance optical spectroscopy measurements where the diffusive medium is illuminated from a point source and diffused photons are collected at a given distance from the source. To increase the sensitivity to higher penetration depth of investigation, the source and the detector separation should be small which in turn increases the number of unwanted early arriving photons. This system will keep the detector off for the first 500-600ps, thus rejecting the early arriving photons, and will only turn-ON the detector when it is expected to detect the late photons coming from the deeper regions. The proposed fully CMOS integrated system is the first of its kind to be introduced for the ultra-fast gating of the single photon detectors.
{"title":"High-voltage pulse generator with variable delay for ultrafast gating of single photon detector","authors":"Sreenil Saha, F. Lesage, M. Sawan","doi":"10.1109/LASCAS.2016.7451027","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451027","url":null,"abstract":"In this paper we have developed an ultrafast pulse generator to turn on a Single Photon Avalanche Diode (SPAD) sensor with picosecond resolution, at specific time windows. The pulse amplitude and duration is user tunable to provide a variable excess bias voltage to the detector. The transition times (rise and fall time) of the pulse is in the range of 250 to 550 ps depending on the amplitude. The generator was designed to be applied in reflectance optical spectroscopy measurements where the diffusive medium is illuminated from a point source and diffused photons are collected at a given distance from the source. To increase the sensitivity to higher penetration depth of investigation, the source and the detector separation should be small which in turn increases the number of unwanted early arriving photons. This system will keep the detector off for the first 500-600ps, thus rejecting the early arriving photons, and will only turn-ON the detector when it is expected to detect the late photons coming from the deeper regions. The proposed fully CMOS integrated system is the first of its kind to be introduced for the ultra-fast gating of the single photon detectors.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114083665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451076
Ismael Seidel, M. Monteiro, José Luís Almada Güntzel, L. Agostini
The main reason for the long time and high energy requirements of state-of-the-art Video Coding (VC) standards, such as the HEVC, is the large amount of distortion calculations. Among the most known and used ones is the Sum of Squared Differences (SSD) which has a strong correlation with the Peak Signal-to-Noise Ratio (PSNR). Such correlation is explored by current encoders to provide a good trade-off between rate and distortion. Once VC is mandatory in current battery-powered devices, the adopted distortion metric must be as energy-efficient as possible. Although simple, the SSD requires a square operation, which hardware realization is costly. Thus, some VC hardware designs replace the SSD by the Sum of Absolute Differences (SAD). However, using SAD instead of SSD pays a price in coding efficiency. In this work we investigate four hardware designs for the square operation. Synthesis results for the designed architectures are compared to a reference SAD design from the literature. The best SSD architecture, using clock gating, requires only 20% more energy than SAD.
{"title":"Squarer exploration for energy-efficient sum of squared differences","authors":"Ismael Seidel, M. Monteiro, José Luís Almada Güntzel, L. Agostini","doi":"10.1109/LASCAS.2016.7451076","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451076","url":null,"abstract":"The main reason for the long time and high energy requirements of state-of-the-art Video Coding (VC) standards, such as the HEVC, is the large amount of distortion calculations. Among the most known and used ones is the Sum of Squared Differences (SSD) which has a strong correlation with the Peak Signal-to-Noise Ratio (PSNR). Such correlation is explored by current encoders to provide a good trade-off between rate and distortion. Once VC is mandatory in current battery-powered devices, the adopted distortion metric must be as energy-efficient as possible. Although simple, the SSD requires a square operation, which hardware realization is costly. Thus, some VC hardware designs replace the SSD by the Sum of Absolute Differences (SAD). However, using SAD instead of SSD pays a price in coding efficiency. In this work we investigate four hardware designs for the square operation. Synthesis results for the designed architectures are compared to a reference SAD design from the literature. The best SSD architecture, using clock gating, requires only 20% more energy than SAD.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133433306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451046
T. Prego, A. Lima, S. L. Netto, E. Silva
This paper addresses the problem of anomaly detection on rotating machinery in industrial environments using single channel audio signals. The proposed algorithm is based on image processing feature analysis obtained from the image representation of the Short-time Fourier Transform of reference and degraded audio signals. In order to assess the potential of the algorithm, a 8 signals database is recorded. The proposed algorithm is able to separate signals of machinery normal behavior from signals of machinery anomalous behavior with 100% hit rate using the recorded database.
{"title":"Audio anomaly detection on rotating machinery using image signal processing","authors":"T. Prego, A. Lima, S. L. Netto, E. Silva","doi":"10.1109/LASCAS.2016.7451046","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451046","url":null,"abstract":"This paper addresses the problem of anomaly detection on rotating machinery in industrial environments using single channel audio signals. The proposed algorithm is based on image processing feature analysis obtained from the image representation of the Short-time Fourier Transform of reference and degraded audio signals. In order to assess the potential of the algorithm, a 8 signals database is recorded. The proposed algorithm is able to separate signals of machinery normal behavior from signals of machinery anomalous behavior with 100% hit rate using the recorded database.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130389799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451079
Uldric A. Antao, J. Choma, A. Dibazar, T. Berger
Unattended ground sensors (UGS) are widely used for persistent, surveillance that detects potential threats from intruders without generating false alarms. Battery life is the limiting factor for solutions using digital processing. A 40nW subthreshold analog CMOS (complementary metal oxide semiconductor) chip is fabricated and tested, that wakes up a threat classifying stage. Subthreshold circuits are prone to mismatches and temperature variations, and methods to reduce them are also proposed promising a sturdy UGS. The chip is compared with a previous generation all digital system, consuming 160,000 times less power.
{"title":"Mismatch and temperature compensation for subthreshold seismic sensor system","authors":"Uldric A. Antao, J. Choma, A. Dibazar, T. Berger","doi":"10.1109/LASCAS.2016.7451079","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451079","url":null,"abstract":"Unattended ground sensors (UGS) are widely used for persistent, surveillance that detects potential threats from intruders without generating false alarms. Battery life is the limiting factor for solutions using digital processing. A 40nW subthreshold analog CMOS (complementary metal oxide semiconductor) chip is fabricated and tested, that wakes up a threat classifying stage. Subthreshold circuits are prone to mismatches and temperature variations, and methods to reduce them are also proposed promising a sturdy UGS. The chip is compared with a previous generation all digital system, consuming 160,000 times less power.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125943541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451036
D. Muratore, E. Bonizzoni, F. Maloberti, C. Fiocchi
This paper presents a novel architecture for capacitive sensor interfaces that is insensitive to electro magnetic interferers in hostile environments. A bridge structure, with a feedback control and a special band-pass filter, overcomes the problems that affect the standard approaches. Behavioural level simulations demonstrate the feasibility of the idea for 12-bit resolution.
{"title":"A capacitive sensor interface for high-resolution acquisitions in hostile environments","authors":"D. Muratore, E. Bonizzoni, F. Maloberti, C. Fiocchi","doi":"10.1109/LASCAS.2016.7451036","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451036","url":null,"abstract":"This paper presents a novel architecture for capacitive sensor interfaces that is insensitive to electro magnetic interferers in hostile environments. A bridge structure, with a feedback control and a special band-pass filter, overcomes the problems that affect the standard approaches. Behavioural level simulations demonstrate the feasibility of the idea for 12-bit resolution.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129765197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451065
Luis Sanchez, G. Patino, V. Murray, J. Lyke
We present a novel version of the FPGA-based Universal Link for LVDS (low-voltage differential signaling) communications that reduces the power consumption by sending the information only when a new data is input. In the a regular LVDS protocol, 4 wires are required for a full duplex communication. The aim of the Universal Link is to reduce the amount of wires in the network by sending data from N signal through a single connection. These new approach reduces the number of bits transmitted to 84% of the original system, when N = 2, and up to 23% for N > 130. Also, the sampling frequency is considerable reduced.
{"title":"Reduced power consumption in the FPGA-based Universal Link for LVDS communications","authors":"Luis Sanchez, G. Patino, V. Murray, J. Lyke","doi":"10.1109/LASCAS.2016.7451065","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451065","url":null,"abstract":"We present a novel version of the FPGA-based Universal Link for LVDS (low-voltage differential signaling) communications that reduces the power consumption by sending the information only when a new data is input. In the a regular LVDS protocol, 4 wires are required for a full duplex communication. The aim of the Universal Link is to reduce the amount of wires in the network by sending data from N signal through a single connection. These new approach reduces the number of bits transmitted to 84% of the original system, when N = 2, and up to 23% for N > 130. Also, the sampling frequency is considerable reduced.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117025103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451091
A. W. Zomagboguelou, C. Galup-Montoro, M. C. Schneider
A relaxation oscillator is presented that makes use of a current-mode Schmitt trigger to reduce the effects of process, voltage and temperature (PVT) variations. A detailed analysis of the oscillator, including the temperature performance, is presented and verified by experimental results. A test chip with a typical frequency of 32 kHz was fabricated in a 0.18 μm standard CMOS process. The measured frequency variations were +/- 30 ppm/°C for temperature variation from -20 °C to 80°C and +/- 500 ppm/V for supply voltage variation from 0.7 V to 1.8 V. The short term stability is 66 ppm (2 ns) of jitter while the long term stability is 500 ppm of Allan deviation after 10 seconds. A careful design results in a total area of 0.1 mm2 and a power consumption of 150 nW.
{"title":"A 150nW 32 kHz mobility-compensated relaxation oscillator with +/−30ppm/°C temperature stability","authors":"A. W. Zomagboguelou, C. Galup-Montoro, M. C. Schneider","doi":"10.1109/LASCAS.2016.7451091","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451091","url":null,"abstract":"A relaxation oscillator is presented that makes use of a current-mode Schmitt trigger to reduce the effects of process, voltage and temperature (PVT) variations. A detailed analysis of the oscillator, including the temperature performance, is presented and verified by experimental results. A test chip with a typical frequency of 32 kHz was fabricated in a 0.18 μm standard CMOS process. The measured frequency variations were +/- 30 ppm/°C for temperature variation from -20 °C to 80°C and +/- 500 ppm/V for supply voltage variation from 0.7 V to 1.8 V. The short term stability is 66 ppm (2 ns) of jitter while the long term stability is 500 ppm of Allan deviation after 10 seconds. A careful design results in a total area of 0.1 mm2 and a power consumption of 150 nW.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128290363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451089
Julio de Oliveira, L. Soares, E. Costa, S. Bampi
This paper proposes the exploration of approximate adders for the implementation of power-efficient Gaussian and Gradient filters for Image Processing. The Gaussian filter is a convolution operator which is used to blur images and to remove noise. On the other hand, the Gradient of an image measures how it is changing. Both blocks can be designed in hardware using only shifts and additions. In this work we exploit a set of approximate adders in order to implement energy-efficient filters. The tree of adders of Gaussian and Gradient filters are implemented using one RCA-based approximate adder, as well as an Error-Tolerant Adder ETAI. The approximate architectures are compared to the best precise implementation of the filters. As the Gaussian and Gradient blocks are part of the Canny edge detector algorithm, we have implemented the adder trees of the filters aiming this application. Our main results show that for an efficient power realization of this algorithm, the best strategy consists in the implementation of the Gaussian filter with ETA I adder, and the Gradient filter with the RCA-based adder.
{"title":"Exploiting approximate adder circuits for power-efficient Gaussian and Gradient filters for Canny edge detector algorithm","authors":"Julio de Oliveira, L. Soares, E. Costa, S. Bampi","doi":"10.1109/LASCAS.2016.7451089","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451089","url":null,"abstract":"This paper proposes the exploration of approximate adders for the implementation of power-efficient Gaussian and Gradient filters for Image Processing. The Gaussian filter is a convolution operator which is used to blur images and to remove noise. On the other hand, the Gradient of an image measures how it is changing. Both blocks can be designed in hardware using only shifts and additions. In this work we exploit a set of approximate adders in order to implement energy-efficient filters. The tree of adders of Gaussian and Gradient filters are implemented using one RCA-based approximate adder, as well as an Error-Tolerant Adder ETAI. The approximate architectures are compared to the best precise implementation of the filters. As the Gaussian and Gradient blocks are part of the Canny edge detector algorithm, we have implemented the adder trees of the filters aiming this application. Our main results show that for an efficient power realization of this algorithm, the best strategy consists in the implementation of the Gaussian filter with ETA I adder, and the Gradient filter with the RCA-based adder.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131868675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451075
A. F. Jaimes, F. Sousa
When a DC voltage source supplies energy to an electric load, it can operate either for maximum power transfer and low efficiency (50%), or with an acceptable efficiency with less power transferred. In this paper an analytic expression is developed and used to quantify this trade off. Moreover, this expression is validated by an experimental circuit demonstrator.
{"title":"Revisiting the power-efficiency trade-off on a DC voltage source","authors":"A. F. Jaimes, F. Sousa","doi":"10.1109/LASCAS.2016.7451075","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451075","url":null,"abstract":"When a DC voltage source supplies energy to an electric load, it can operate either for maximum power transfer and low efficiency (50%), or with an acceptable efficiency with less power transferred. In this paper an analytic expression is developed and used to quantify this trade off. Moreover, this expression is validated by an experimental circuit demonstrator.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134054954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451095
F. Maloberti, E. Bonizzoni, P. B. Basyurt
This paper gives an overview on the key features of the several building blocks constituting modern nomadic systems. Different micro-power energy harvesting techniques are described and discussed. In addition, this paper reviews the state of the art and provides recently published examples of low power low voltage analog circuits, such as operational amplifiers, reference generators, and data converters.
{"title":"Very-low-voltage and ultra-low-power analog circuits for nomadic applications","authors":"F. Maloberti, E. Bonizzoni, P. B. Basyurt","doi":"10.1109/LASCAS.2016.7451095","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451095","url":null,"abstract":"This paper gives an overview on the key features of the several building blocks constituting modern nomadic systems. Different micro-power energy harvesting techniques are described and discussed. In addition, this paper reviews the state of the art and provides recently published examples of low power low voltage analog circuits, such as operational amplifiers, reference generators, and data converters.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128983981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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