Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451034
F. Santos, A. Mariano, B. Leite
This paper presents the simulation results of a linear, fully integrated, two-stage digitally programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is composed of a set of amplifying cells which can be enabled or disabled independently by a digital control circuit. All seven operational modes are univocal in terms of 1 dB output compression point (OCP1dB), saturated output power (PSAT) and power gain at 2.4 GHz. The lowest power mode achieves an 8.1 dBm PSAT, a 13.5 dB power gain and consumes 171 mW DC power (PDC) at an OCPMB of 6 dBm, whereas the highest power mode reaches an 18.9 dBm PSAT and a 21.1 dB power gain and consumes 415 mW PDC at an OCPmb of 18.2 dBm.
{"title":"2.4 GHz CMOS digitally programmable power amplifier for power back-off operation","authors":"F. Santos, A. Mariano, B. Leite","doi":"10.1109/LASCAS.2016.7451034","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451034","url":null,"abstract":"This paper presents the simulation results of a linear, fully integrated, two-stage digitally programmable 130 nm CMOS power amplifier (PA) operating at 2.4 GHz. Its power stage is composed of a set of amplifying cells which can be enabled or disabled independently by a digital control circuit. All seven operational modes are univocal in terms of 1 dB output compression point (OCP1dB), saturated output power (PSAT) and power gain at 2.4 GHz. The lowest power mode achieves an 8.1 dBm PSAT, a 13.5 dB power gain and consumes 171 mW DC power (PDC) at an OCPMB of 6 dBm, whereas the highest power mode reaches an 18.9 dBm PSAT and a 21.1 dB power gain and consumes 415 mW PDC at an OCPmb of 18.2 dBm.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123352014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451093
Julio Saldaña Pumarica, C. S. Cárdenas, E. Del-Moral-Hernandez
This paper presents a strategy for implementing the discrete time version of the Nonlinear Energy Operator (NEO). The proposed implementation approach is based on the utilization of a circuit that produces an output current proportional to the square of its input voltage, which we call transconductor-squarer circuit. In order to avoid adverse effects of mismatch between circuits that should be identical, we propose the reuse of a single transconductor-squarer circuit for the realization of the NEO formula. The NEO system was evaluated simulating its ability to emphasize the presence of neural spikes in a synthetic noisy extracellular neural signal. The circuit is designed aiming at a standard CMOS fabrication process with 90nm minimum channel length and its circuit simulation shows energy consumption of 60pJ per spike. Simulations also show that the circuit is capable of operating at about 30 Ksample/s, compatible with current state-of-the-art neural recording systems.
{"title":"A CMOS implementation of the discrete time nonlinear energy operator based on a transconductor-squarer circuit","authors":"Julio Saldaña Pumarica, C. S. Cárdenas, E. Del-Moral-Hernandez","doi":"10.1109/LASCAS.2016.7451093","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451093","url":null,"abstract":"This paper presents a strategy for implementing the discrete time version of the Nonlinear Energy Operator (NEO). The proposed implementation approach is based on the utilization of a circuit that produces an output current proportional to the square of its input voltage, which we call transconductor-squarer circuit. In order to avoid adverse effects of mismatch between circuits that should be identical, we propose the reuse of a single transconductor-squarer circuit for the realization of the NEO formula. The NEO system was evaluated simulating its ability to emphasize the presence of neural spikes in a synthetic noisy extracellular neural signal. The circuit is designed aiming at a standard CMOS fabrication process with 90nm minimum channel length and its circuit simulation shows energy consumption of 60pJ per spike. Simulations also show that the circuit is capable of operating at about 30 Ksample/s, compatible with current state-of-the-art neural recording systems.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"38 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120813441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451038
V. RenatoCampana, H. Klimach, S. Bampi
The analysis and design of a resistorless sub-bandgap voltage reference using Schottky diode and Low-VTo transistors is presented herein. The circuit is self-biased and works in the nano-ampere consumption range, achieving full operation at 0.3 V of supply voltage. The design is validated through post-layout simulations including process variability analysis, for a commercial 130 nm CMOS process. A voltage reference of 102.8 mV is reached under VDD = 1.2V and 92.5 mV for VDD = 0.3V, with a temperature coefficient (TC) of 215.7 ppm/°C and 216 ppm/°C, respectively using curvature correction to improve the TC in the range from -40° C to 120° C. The current consumption is 212 nA with VDD = 1.2V at 27°C, and the chip area is 0.0068 mm2.
{"title":"Nano-watt 0.3 V supply resistorless voltage reference with Schottky diode","authors":"V. RenatoCampana, H. Klimach, S. Bampi","doi":"10.1109/LASCAS.2016.7451038","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451038","url":null,"abstract":"The analysis and design of a resistorless sub-bandgap voltage reference using Schottky diode and Low-V<sub>To</sub> transistors is presented herein. The circuit is self-biased and works in the nano-ampere consumption range, achieving full operation at 0.3 V of supply voltage. The design is validated through post-layout simulations including process variability analysis, for a commercial 130 nm CMOS process. A voltage reference of 102.8 mV is reached under V<sub>DD</sub> = 1.2V and 92.5 mV for V<sub>DD</sub> = 0.3V, with a temperature coefficient (TC) of 215.7 ppm/°C and 216 ppm/°C, respectively using curvature correction to improve the TC in the range from -40° C to 120° C. The current consumption is 212 nA with V<sub>DD</sub> = 1.2V at 27°C, and the chip area is 0.0068 mm<sup>2</sup>.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116892168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451074
Henrique Maich, Mateus Melo, L. Agostini, B. Zatt, M. Porto
This paper presents a memory-transference analysis to a parallel Motion Estimation (ME) algorithms for current embedded processors, that usually are composed by a CPU and GPU with OpenCL parallel-programming support. However, in this scope, the CPU and GPU memories are different, thus being necessary a memory transference data between then. This paper introduces the main concepts of the ME, discusses its related problems and proposes different approaches for CPU and GPU memory transference. Three different approaches for reference frame transference was evaluated and tested using three different ME algorithms. The experiments evaluated the time performance and the energy consumption of all tests considering each proposed memory transference approaches. The results indicate that the best solution of memory transference is using the Full Frame approach, where each reference frame was transferred to the GPU memory for every new current frame.
{"title":"Energy analisys of motion estimation memory transference on embedded processors","authors":"Henrique Maich, Mateus Melo, L. Agostini, B. Zatt, M. Porto","doi":"10.1109/LASCAS.2016.7451074","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451074","url":null,"abstract":"This paper presents a memory-transference analysis to a parallel Motion Estimation (ME) algorithms for current embedded processors, that usually are composed by a CPU and GPU with OpenCL parallel-programming support. However, in this scope, the CPU and GPU memories are different, thus being necessary a memory transference data between then. This paper introduces the main concepts of the ME, discusses its related problems and proposes different approaches for CPU and GPU memory transference. Three different approaches for reference frame transference was evaluated and tested using three different ME algorithms. The experiments evaluated the time performance and the energy consumption of all tests considering each proposed memory transference approaches. The results indicate that the best solution of memory transference is using the Full Frame approach, where each reference frame was transferred to the GPU memory for every new current frame.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115631971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451015
Nihat Akkan, B. Erkmen
Current mirrors are important basic building blocks of analog electronic circuits. In this paper graphene field effect transistor (GFET) based basic and cascode current mirrors are studied. Drain current equations of the GFET model are coded with Verilog-A language and integrated to SPICE simulator. DC output characteristics of current mirror circuits are analyzed and compared for both configuration with the help of simulation results. AC analysis is also performed and frequency response of the circuits are observed. The simulation results show that GFET based current mirrors can operate properly, however there are some drawbacks to overcome.
{"title":"Analysis of graphene field effect transistor based current mirrors","authors":"Nihat Akkan, B. Erkmen","doi":"10.1109/LASCAS.2016.7451015","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451015","url":null,"abstract":"Current mirrors are important basic building blocks of analog electronic circuits. In this paper graphene field effect transistor (GFET) based basic and cascode current mirrors are studied. Drain current equations of the GFET model are coded with Verilog-A language and integrated to SPICE simulator. DC output characteristics of current mirror circuits are analyzed and compared for both configuration with the help of simulation results. AC analysis is also performed and frequency response of the circuits are observed. The simulation results show that GFET based current mirrors can operate properly, however there are some drawbacks to overcome.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129713056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451063
Luís Henrique Rodovalho, E. Fabris, H. Klimach
This paper presents an alternative to crystal based oscillators for reference frequencies in highly integrated SoCs. The frequency reference through the usage of an active bias controlled ring oscillator operating with a supply voltage from 300 to 500 mV for an temperature from -40 to 125 ° C. The oscillator shows a very good temperature and supply voltage frequency stability coming from the active biasing using a stable current reference.
{"title":"Stable ring oscillator for ultra low supply voltages","authors":"Luís Henrique Rodovalho, E. Fabris, H. Klimach","doi":"10.1109/LASCAS.2016.7451063","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451063","url":null,"abstract":"This paper presents an alternative to crystal based oscillators for reference frequencies in highly integrated SoCs. The frequency reference through the usage of an active bias controlled ring oscillator operating with a supply voltage from 300 to 500 mV for an temperature from -40 to 125 ° C. The oscillator shows a very good temperature and supply voltage frequency stability coming from the active biasing using a stable current reference.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129863620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451023
Denys Pestana-Viana, Rafael Zambrano-Lopez, A. Lima, T. Prego, S. L. Netto, E. Silva
This paper investigates the problem of automatic detection of rotating-machine faults based on vibration signals acquired during machine operation. In particular, two new signal features, namely the kurtosis and entropy, are considered along with main spectral peaks to discriminate between several machine conditions: normal operation, (vertical and horizontal) misalignment, unbalanced load and bearing faults. Moreover, the inclusion of one set of three accelerometers for each roller bearing associated to the system acquiring more vibration signals also affects the generation of feature vector and is part of our proposal. In order to evaluate the rotating machine fault classification, a database of 1951 fault scenarios with several different fault intensities and rotating frequencies was designed and recorded, taking into consideration the specificities of the proposed machine learning task. The artificial neural networks recognition system employed in this work reached 95.8% of overall accuracy, showing the efficiency of the proposed approach.
{"title":"The influence of feature vector on the classification of mechanical faults using neural networks","authors":"Denys Pestana-Viana, Rafael Zambrano-Lopez, A. Lima, T. Prego, S. L. Netto, E. Silva","doi":"10.1109/LASCAS.2016.7451023","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451023","url":null,"abstract":"This paper investigates the problem of automatic detection of rotating-machine faults based on vibration signals acquired during machine operation. In particular, two new signal features, namely the kurtosis and entropy, are considered along with main spectral peaks to discriminate between several machine conditions: normal operation, (vertical and horizontal) misalignment, unbalanced load and bearing faults. Moreover, the inclusion of one set of three accelerometers for each roller bearing associated to the system acquiring more vibration signals also affects the generation of feature vector and is part of our proposal. In order to evaluate the rotating machine fault classification, a database of 1951 fault scenarios with several different fault intensities and rotating frequencies was designed and recorded, taking into consideration the specificities of the proposed machine learning task. The artificial neural networks recognition system employed in this work reached 95.8% of overall accuracy, showing the efficiency of the proposed approach.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122333378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451016
Gabriele Costa Goncalves, F. Andrade, Henrique Alves Gaspar Ribeiro, Shirlene de Santana Soares, I. Nassiffe, E. Santana, A. Cunha
This work presents a theoretical comparison between three distinct criteria for evaluating distortion of analog multipliers: the two dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. DC measurements have been accomplished over commercially available devices in order to identify difficulties and advantages implied in the methodology for determining the two dimensional integral nonlinear function.
{"title":"Distortion analysis of integrated analog multipliers: DC versus AC approaches","authors":"Gabriele Costa Goncalves, F. Andrade, Henrique Alves Gaspar Ribeiro, Shirlene de Santana Soares, I. Nassiffe, E. Santana, A. Cunha","doi":"10.1109/LASCAS.2016.7451016","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451016","url":null,"abstract":"This work presents a theoretical comparison between three distinct criteria for evaluating distortion of analog multipliers: the two dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. DC measurements have been accomplished over commercially available devices in order to identify difficulties and advantages implied in the methodology for determining the two dimensional integral nonlinear function.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131975564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451025
Juan Felipe Medina Lee, A. López-Parrado, Jaime Velasco-Medina
This paper presents the hardware implementation of FFT-based spectral correlation and pilot sensing spectrum sensing techniques defined in IEEE 802.22 standard. Both techniques estimate the spectrum of the incoming signal, where the spectral correlation technique calculates the ratio between two specific frequency components of the signal and evaluates if there is signal present in the channel; and the pilot sensing technique calculates the greatest value of the spectrum and compares that value for two consecutive spectrums to determine if there is signal present in the channel. Both spectrum sensing techniques are implemented on an FPGA and their performances were tested using an ATSC signal captured with a spectrum analyzer. Our implementation of the spectral correlation technique can detect an ATSC signal with a signal to noise ratio greater than -24.3 dB, and the pilot sensing technique can detect the ATSC signal with a signal to noise ratio greater than -33 dB.
{"title":"Hardware implementation of FFT-based spectrum sensing techniques for cognitive radio","authors":"Juan Felipe Medina Lee, A. López-Parrado, Jaime Velasco-Medina","doi":"10.1109/LASCAS.2016.7451025","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451025","url":null,"abstract":"This paper presents the hardware implementation of FFT-based spectral correlation and pilot sensing spectrum sensing techniques defined in IEEE 802.22 standard. Both techniques estimate the spectrum of the incoming signal, where the spectral correlation technique calculates the ratio between two specific frequency components of the signal and evaluates if there is signal present in the channel; and the pilot sensing technique calculates the greatest value of the spectrum and compares that value for two consecutive spectrums to determine if there is signal present in the channel. Both spectrum sensing techniques are implemented on an FPGA and their performances were tested using an ATSC signal captured with a spectrum analyzer. Our implementation of the spectral correlation technique can detect an ATSC signal with a signal to noise ratio greater than -24.3 dB, and the pilot sensing technique can detect the ATSC signal with a signal to noise ratio greater than -33 dB.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451043
David Kwong-Heng Phoon, T. Lehmann, T. J. Hamilton, Julian Jenkins
In this paper we will demonstrate the implementation of a low-dropout hybrid regulator (LDO) that includes a continuous to discrete time feedback loop, in a 28 nm TSMC CMOS technology. The proposed LDO will be given an apriori signal to differentiate between low and high load current states. This mixed mode design is scalable ensuring the best regulation at different load currents for dual or multichannel LDO designs. It has a maximum overshoot of less than 5 mV and undershoot of less than 50 mV with steady state ripple of less than 5 mV. The maximum switching transient time to steady state regulation was found by simulation to be under 830 ps.
{"title":"Hybrid dual-mode low voltage dropout regulator with infinite impulse response digital filters","authors":"David Kwong-Heng Phoon, T. Lehmann, T. J. Hamilton, Julian Jenkins","doi":"10.1109/LASCAS.2016.7451043","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451043","url":null,"abstract":"In this paper we will demonstrate the implementation of a low-dropout hybrid regulator (LDO) that includes a continuous to discrete time feedback loop, in a 28 nm TSMC CMOS technology. The proposed LDO will be given an apriori signal to differentiate between low and high load current states. This mixed mode design is scalable ensuring the best regulation at different load currents for dual or multichannel LDO designs. It has a maximum overshoot of less than 5 mV and undershoot of less than 50 mV with steady state ripple of less than 5 mV. The maximum switching transient time to steady state regulation was found by simulation to be under 830 ps.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131876317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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