Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451067
J. S. Filho, C. A. Costa, G. Cunha, D. Belfort, S. Catunda, E. N. Santos, M. J. Silva
This paper proposes an architecture of a conditioning circuit for dual-modality wire-mesh sensors, applied to multiphase flow measuring. The proposed circuit topology uses an AC-based impedance measurement technique, and is able to process signals from a 4×4 wire-mesh structure, performing an I/Q demodulation for the direct extraction of fluid permittivity and conductivity values. System-level considerations are taken into account to derive the requirements for the main circuit blocks, which are aimed to be integrated on standard CMOS technology.
{"title":"Requirements for an integrated conditioning circuit for multiphase flow imaging using impedance wire-mesh sensors","authors":"J. S. Filho, C. A. Costa, G. Cunha, D. Belfort, S. Catunda, E. N. Santos, M. J. Silva","doi":"10.1109/LASCAS.2016.7451067","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451067","url":null,"abstract":"This paper proposes an architecture of a conditioning circuit for dual-modality wire-mesh sensors, applied to multiphase flow measuring. The proposed circuit topology uses an AC-based impedance measurement technique, and is able to process signals from a 4×4 wire-mesh structure, performing an I/Q demodulation for the direct extraction of fluid permittivity and conductivity values. System-level considerations are taken into account to derive the requirements for the main circuit blocks, which are aimed to be integrated on standard CMOS technology.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"446 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116187188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7450998
M. Kousoulis, G. Antoniou
A circuit realization is presented for four-dimensional (4D) lattice-ladder discrete filters. The proposed 4D circuit realization requires, for its implementation, a minimum number of delay elements. Further, the dimension of the state-vector, of the derived 4D state-space model, is minimal and its 4D transfer function is characterized by the all-pass property. A step-by-step low-order example is provided to demonstrate the proposed minimality of both, circuit, and state-space realizations. An educational conjointment of 4D lattice filters with lower dimension filters (2D, 1D), is imparted.
{"title":"Realization of 4D lattice-ladder digital filters","authors":"M. Kousoulis, G. Antoniou","doi":"10.1109/LASCAS.2016.7450998","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7450998","url":null,"abstract":"A circuit realization is presented for four-dimensional (4D) lattice-ladder discrete filters. The proposed 4D circuit realization requires, for its implementation, a minimum number of delay elements. Further, the dimension of the state-vector, of the derived 4D state-space model, is minimal and its 4D transfer function is characterized by the all-pass property. A step-by-step low-order example is provided to demonstrate the proposed minimality of both, circuit, and state-space realizations. An educational conjointment of 4D lattice filters with lower dimension filters (2D, 1D), is imparted.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127639849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451021
Dalton Martini Colombo, R. Soares, Fabricio Mattos
Passive RFID circuits depend on low voltage low power area-efficient current references. This work presents two current source implementations using 180 nm CMOS process. Both circuits work with a minimum supply voltage of 0.8 V and with a current consumption lower than 150 nA. The first one has a positive temperature coefficient while the second one is temperature compensated. Silicon results from 10 measured samples show an average output current of 21.8 nA and 20.1 nA for the PTAT and the temperature-compensated (COMP) references, respectively. Their measured temperature variations were about 41% and 5% in temperature range of -40 to 65 °C, for the PTAT and COMP, respectively.
{"title":"Low voltage low power current reference circuit for passive RFID applications","authors":"Dalton Martini Colombo, R. Soares, Fabricio Mattos","doi":"10.1109/LASCAS.2016.7451021","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451021","url":null,"abstract":"Passive RFID circuits depend on low voltage low power area-efficient current references. This work presents two current source implementations using 180 nm CMOS process. Both circuits work with a minimum supply voltage of 0.8 V and with a current consumption lower than 150 nA. The first one has a positive temperature coefficient while the second one is temperature compensated. Silicon results from 10 measured samples show an average output current of 21.8 nA and 20.1 nA for the PTAT and the temperature-compensated (COMP) references, respectively. Their measured temperature variations were about 41% and 5% in temperature range of -40 to 65 °C, for the PTAT and COMP, respectively.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132879687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451009
Marcos T. Leipnitz, Geferson L. H. Júnior, G. Nazar
Field Programmable Gate Arrays (FPGAs) are successful platforms for the implementation of communication systems, due to their potential high throughput and low development costs. In such systems, however, investigating the system's resilience to soft errors is crucial in many scenarios, such as when facing stringent dependability constraints or when operating in radiation-harsh environments. Therefore, in this paper we present a fault injection platform that targets specifically FPGA-based communication systems. The platform operates partially on the device and partially on a host computer, aiming at both flexibility and high performance. A Reed-Solomon decoder is used as a case study to validate the platform, showing its ability to measure metrics that are relevant both for critical systems (e.g., fault sensitivity) as well as for communication systems in general (e.g., bit error rate).
{"title":"A fault injection platform for FPGA-based communication systems","authors":"Marcos T. Leipnitz, Geferson L. H. Júnior, G. Nazar","doi":"10.1109/LASCAS.2016.7451009","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451009","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) are successful platforms for the implementation of communication systems, due to their potential high throughput and low development costs. In such systems, however, investigating the system's resilience to soft errors is crucial in many scenarios, such as when facing stringent dependability constraints or when operating in radiation-harsh environments. Therefore, in this paper we present a fault injection platform that targets specifically FPGA-based communication systems. The platform operates partially on the device and partially on a host computer, aiming at both flexibility and high performance. A Reed-Solomon decoder is used as a case study to validate the platform, showing its ability to measure metrics that are relevant both for critical systems (e.g., fault sensitivity) as well as for communication systems in general (e.g., bit error rate).","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114309378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451071
Rai Saraiva, Julio C. Ruzicki, A. Souza, R. Soares
Stochastic Computing (SC) is a fault tolerant design paradigm where numeric data are converted to probabilities on streams of random digital bits. This representation allows computing on low complexity hardware. SC allows a significant area reduction and an increased tolerance to transient errors, but presents high latency to achieve a moderate accuracy. Recent papers address this issue using parallelism and stochastic multibit number representations. In this paper, Multilevel Stochastic Coding (MSC), a new stochastic representation based on range segmentation is presented and its operators are developed using FPGA design flow and compared to alternative approaches. A comparison in terms of area and latency is applied between approaches to achieve a given signal to noise ratio (SNR). Results show that MSC presents a significant latency reduction with a smaller area penalty.
{"title":"Range segmentation to improve latency in parallel stochastic computing","authors":"Rai Saraiva, Julio C. Ruzicki, A. Souza, R. Soares","doi":"10.1109/LASCAS.2016.7451071","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451071","url":null,"abstract":"Stochastic Computing (SC) is a fault tolerant design paradigm where numeric data are converted to probabilities on streams of random digital bits. This representation allows computing on low complexity hardware. SC allows a significant area reduction and an increased tolerance to transient errors, but presents high latency to achieve a moderate accuracy. Recent papers address this issue using parallelism and stochastic multibit number representations. In this paper, Multilevel Stochastic Coding (MSC), a new stochastic representation based on range segmentation is presented and its operators are developed using FPGA design flow and compared to alternative approaches. A comparison in terms of area and latency is applied between approaches to achieve a given signal to noise ratio (SNR). Results show that MSC presents a significant latency reduction with a smaller area penalty.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116044432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451001
E. Spinelli, A. Veiga
Modern instrumentation is moving towards fully differential conditioning circuits. They provide an elegant and efficient way to adapt differential signals, like those provided by balanced sensors, to differential-input analog-to-digital converters (ADC). For that to be possible, many well-known Single-Ended (SE) conditioning circuits must be converted to their Fully-Differential (FD) versions. This work presents a FD dc servo circuit, able to restore both common mode and differential mode dc levels to their desirable values, suited to those required by the ADC to optimize its input range. The general scheme and the design procedure to adapt the circuit to particular needs are presented. Also experimental data obtained from a FD dc restoration circuit are presented.
{"title":"A fully-differential DC restoration circuit","authors":"E. Spinelli, A. Veiga","doi":"10.1109/LASCAS.2016.7451001","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451001","url":null,"abstract":"Modern instrumentation is moving towards fully differential conditioning circuits. They provide an elegant and efficient way to adapt differential signals, like those provided by balanced sensors, to differential-input analog-to-digital converters (ADC). For that to be possible, many well-known Single-Ended (SE) conditioning circuits must be converted to their Fully-Differential (FD) versions. This work presents a FD dc servo circuit, able to restore both common mode and differential mode dc levels to their desirable values, suited to those required by the ADC to optimize its input range. The general scheme and the design procedure to adapt the circuit to particular needs are presented. Also experimental data obtained from a FD dc restoration circuit are presented.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134639463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451035
Calebe Conceição, G. Posser, R. Reis
In this work a greedy cell clustering technique is proposed to reduce the number of transistors of circuits. Reducing the amount of transistors can provide leakage power reduction. The clusterization is applied to a set of connected cells with fanout one. These cells are replaced by a equivalent logic complex cell. Hereafter, the layout of any cluster can be automatically designed by using a layout generation tool. The ITC'99 benchmark circuits are synthesized to the 45nm Open Cell Library. The clustering technique presented in this work is able to provide a reduction in the number of transistors of 9.8%, on average, over the synthesis using all cells available in the library. We show that the set of logic functions used by the input netlist influences the results obtained by clustering. For a netlist synthesized without the complex cells of the library our clustering technique reduced the number of transistors in up to 22.3% when compared to the original netlist.
本文提出了一种贪婪单元聚类技术，以减少电路中晶体管的数量。减少晶体管的数量可以提供泄漏功率的降低。该聚类应用于一组扇出为1的连接单元。这些单元被等效的逻辑复杂单元所取代。此后，可以使用布局生成工具自动设计任意集群的布局。将ITC'99基准电路合成为45nm Open Cell Library。与使用库中所有可用单元的合成相比，本工作中提出的聚类技术能够平均减少9.8%的晶体管数量。我们证明了输入网表使用的逻辑函数集会影响聚类得到的结果。对于没有复杂单元库的网络列表，我们的聚类技术与原始网络列表相比，最多减少了22.3%的晶体管数量。
{"title":"Reducing the number of transistors with gate clustering","authors":"Calebe Conceição, G. Posser, R. Reis","doi":"10.1109/LASCAS.2016.7451035","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451035","url":null,"abstract":"In this work a greedy cell clustering technique is proposed to reduce the number of transistors of circuits. Reducing the amount of transistors can provide leakage power reduction. The clusterization is applied to a set of connected cells with fanout one. These cells are replaced by a equivalent logic complex cell. Hereafter, the layout of any cluster can be automatically designed by using a layout generation tool. The ITC'99 benchmark circuits are synthesized to the 45nm Open Cell Library. The clustering technique presented in this work is able to provide a reduction in the number of transistors of 9.8%, on average, over the synthesis using all cells available in the library. We show that the set of logic functions used by the input netlist influences the results obtained by clustering. For a netlist synthesized without the complex cells of the library our clustering technique reduced the number of transistors in up to 22.3% when compared to the original netlist.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134048440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451062
D. Campos, P. J. Abatti, F. L. Bertotti, A. L. F. D. Silveira, João Ari Gualberto Hill
Monitoring grazing ruminants ingestive behaviour has applications in measuring animal welfare, animal diseases detection and animal production system modelling. Current monitoring methods are mostly laborious, time expensive or invasive. In this work, it is presented a non-invasive method for chewing activity identification on goats by masseter muscle surface Electromyography (sEMG). Short-term chewing/resting time and chewing count were successfully predicted on male goats comparing to visual observation.
{"title":"Surface electromyography measurements for ingestive behaviour identification on goats","authors":"D. Campos, P. J. Abatti, F. L. Bertotti, A. L. F. D. Silveira, João Ari Gualberto Hill","doi":"10.1109/LASCAS.2016.7451062","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451062","url":null,"abstract":"Monitoring grazing ruminants ingestive behaviour has applications in measuring animal welfare, animal diseases detection and animal production system modelling. Current monitoring methods are mostly laborious, time expensive or invasive. In this work, it is presented a non-invasive method for chewing activity identification on goats by masseter muscle surface Electromyography (sEMG). Short-term chewing/resting time and chewing count were successfully predicted on male goats comparing to visual observation.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126074437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451000
E. Napoli, G. Castellano, D. Esposito, A. Strollo
The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems only provide white noise sources while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a programmable colored noise generator that, while generating noise signals with features matching the state of the art, overcomes the previously proposed circuits in terms of speed (+10%) and logic resource occupation (-75%).
{"title":"Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence","authors":"E. Napoli, G. Castellano, D. Esposito, A. Strollo","doi":"10.1109/LASCAS.2016.7451000","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451000","url":null,"abstract":"The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems only provide white noise sources while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a programmable colored noise generator that, while generating noise signals with features matching the state of the art, overcomes the previously proposed circuits in terms of speed (+10%) and logic resource occupation (-75%).","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127281488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-02-01DOI: 10.1109/LASCAS.2016.7451047
Mário Saldanha, B. Zatt, M. Porto, L. Agostini, G. Sanchez
This paper proposes a space exploration over gradient-based algorithms to obtain time savings when applying Depth Modeling Mode (DMM) 1 on 3D High Efficiency Video Coding (3D-HEVC) depth maps coding. Four filtering algorithms exploring depth maps characteristics by applying a gradient filter in the depth block borders were evaluated. These filters are applied to detect the best positions to evaluate DMM-1 algorithm, without the use of a semi-brute force approach. Experimental analysis demonstrates that the proposed solutions are capable to achieve time saving results ranging from 4.9% to 8.2%, with a drawback ranging from 0.33% to 1.47% in terms of BD-Rate increase.
{"title":"Solutions for DMM-1 complexity reduction in 3D-HEVC based on gradient calculation","authors":"Mário Saldanha, B. Zatt, M. Porto, L. Agostini, G. Sanchez","doi":"10.1109/LASCAS.2016.7451047","DOIUrl":"https://doi.org/10.1109/LASCAS.2016.7451047","url":null,"abstract":"This paper proposes a space exploration over gradient-based algorithms to obtain time savings when applying Depth Modeling Mode (DMM) 1 on 3D High Efficiency Video Coding (3D-HEVC) depth maps coding. Four filtering algorithms exploring depth maps characteristics by applying a gradient filter in the depth block borders were evaluated. These filters are applied to detect the best positions to evaluate DMM-1 algorithm, without the use of a semi-brute force approach. Experimental analysis demonstrates that the proposed solutions are capable to achieve time saving results ranging from 4.9% to 8.2%, with a drawback ranging from 0.33% to 1.47% in terms of BD-Rate increase.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121496942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：