Pub Date : 2025-04-25DOI: 10.1109/TCSI.2025.3561511
Ke Long;Taotao Xu;Haoshen Zhu;Shuai Deng;Pei Qin;Wenquan Che;Quan Xue
This paper presents a 6-bit bidirectional variable-gain vector-summing active phase shifter (BVG-AVSPS) in TSMC 65nm CMOS technology. The proposed BVG-AVSPS consists of a novel bidirectional quadrature generator, four dual-function bidirectional amplifiers and two input/output matching networks. The proposed hybrid-based quadrature generator achieves low orthogonal amplitude and phase mismatches over a wideband with bidirectionality. Dual-function bidirectional amplifiers are employed to achieve either vector modulation or gain control functions in different operational directions. To improve the phase shifting accuracy during gain tuning, compensation transistors are employed in the dual-function bidirectional amplifiers to minimize additional phase variation. The proposed input/output networks based on L-type coupled inductors ensure proper impedance matching for both input and output in TX and RX modes. For both TX and RX modes over 24 GHz~32 GHz, the measured RMS phase and gain errors are $1.25^{circ } sim 2.4^{circ }$ and 0.42 dB~0.56 dB throughout 12.3 dB gain tuning range, respectively. With the help of the compensation transistors, measured phase variation is less than ±2.1° during output gain tuning. The core area of proposed BVG-AVSPS is $625~mu $ m$times 355~mu $ m.
提出了一种采用台积电65nm CMOS技术的6位双向可变增益矢量和有源移相器（BVG-AVSPS）。提出的BVG-AVSPS由一个新型双向正交发生器、四个双功能双向放大器和两个输入/输出匹配网络组成。所提出的基于混合的正交发生器在双向宽带上实现了低正交幅度和相位失配。双功能双向放大器在不同的操作方向上实现矢量调制或增益控制功能。为了提高增益调谐时的移相精度，在双功能双向放大器中采用了补偿晶体管来减小附加相位变化。所提出的基于l型耦合电感的输入/输出网络确保了在TX和RX模式下输入和输出的阻抗匹配。对于24 GHz和32 GHz以上的TX和RX模式，在12.3 dB增益调谐范围内，测量的均方根相位和增益误差分别为$1.25^{circ } sim 2.4^{circ }$和0.42 dB 0.56 dB。在补偿晶体管的帮助下，在输出增益调谐期间测量到的相位变化小于±2.1°。BVG-AVSPS的核心区为$625~mu $ m $times 355~mu $ m。
{"title":"A 24–32 GHz Bidirectional Variable-Gain Phase Shifter Using a Novel Quadrature Generator and Dual-Function Bidirectional Amplifier With Phase Compensation","authors":"Ke Long;Taotao Xu;Haoshen Zhu;Shuai Deng;Pei Qin;Wenquan Che;Quan Xue","doi":"10.1109/TCSI.2025.3561511","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3561511","url":null,"abstract":"This paper presents a 6-bit bidirectional variable-gain vector-summing active phase shifter (BVG-AVSPS) in TSMC 65nm CMOS technology. The proposed BVG-AVSPS consists of a novel bidirectional quadrature generator, four dual-function bidirectional amplifiers and two input/output matching networks. The proposed hybrid-based quadrature generator achieves low orthogonal amplitude and phase mismatches over a wideband with bidirectionality. Dual-function bidirectional amplifiers are employed to achieve either vector modulation or gain control functions in different operational directions. To improve the phase shifting accuracy during gain tuning, compensation transistors are employed in the dual-function bidirectional amplifiers to minimize additional phase variation. The proposed input/output networks based on L-type coupled inductors ensure proper impedance matching for both input and output in TX and RX modes. For both TX and RX modes over 24 GHz~32 GHz, the measured RMS phase and gain errors are <inline-formula> <tex-math>$1.25^{circ } sim 2.4^{circ }$ </tex-math></inline-formula> and 0.42 dB~0.56 dB throughout 12.3 dB gain tuning range, respectively. With the help of the compensation transistors, measured phase variation is less than ±2.1° during output gain tuning. The core area of proposed BVG-AVSPS is <inline-formula> <tex-math>$625~mu $ </tex-math></inline-formula>m<inline-formula> <tex-math>$times 355~mu $ </tex-math></inline-formula>m.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2614-2625"},"PeriodicalIF":5.2,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-23DOI: 10.1109/TCSI.2025.3560980
T. C. Jayasree;J. C. Suneina;T. Bindima;M. P. Gilesh
Variable filters with adjustable bandwidth are vital components in diverse communication scenarios. This paper presents an innovative architecture for a continuously variable bandwidth filter using a fixed hardware. Our approach integrates a fixed finite impulse response filter between two arbitrary fractional delay filters implemented through a novel Farrow-equivalent-Newton structure. The proposed architecture provides a low-complexity implementation structure compared to the state-of-the-art approaches. A precise mapping equation for the edge frequencies of the filters generated from the proposed continuously variable bandwidth filter, in terms of a variable parameter called the resampling ratio, is also formulated. Validation experiments encompass the design of continuously variable bandwidth filters tailored to various wireless communication standards. The hardware utilization report of the proposed continuously variable bandwidth filter obtained by synthesizing the structure using Xilinx Vivado 2020.2 on a Kintex-7 device is also included, which proves the hardware complexity reduction and efficiency of the proposed structure.
{"title":"Design and Implementation of a Low-Complexity Continuously Variable Digital Filter Using a Novel Farrow-Equivalent-Newton Structure-Based Fractional Delay Filter","authors":"T. C. Jayasree;J. C. Suneina;T. Bindima;M. P. Gilesh","doi":"10.1109/TCSI.2025.3560980","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560980","url":null,"abstract":"Variable filters with adjustable bandwidth are vital components in diverse communication scenarios. This paper presents an innovative architecture for a continuously variable bandwidth filter using a fixed hardware. Our approach integrates a fixed finite impulse response filter between two arbitrary fractional delay filters implemented through a novel Farrow-equivalent-Newton structure. The proposed architecture provides a low-complexity implementation structure compared to the state-of-the-art approaches. A precise mapping equation for the edge frequencies of the filters generated from the proposed continuously variable bandwidth filter, in terms of a variable parameter called the resampling ratio, is also formulated. Validation experiments encompass the design of continuously variable bandwidth filters tailored to various wireless communication standards. The hardware utilization report of the proposed continuously variable bandwidth filter obtained by synthesizing the structure using Xilinx Vivado 2020.2 on a Kintex-7 device is also included, which proves the hardware complexity reduction and efficiency of the proposed structure.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3425-3435"},"PeriodicalIF":5.2,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
How to achieve synchronization control for Piecewise Homogeneous Markov Delayed Neural Networks (PHMDNNs) under hybrid cyber-attacks is the primary focus of this research. Firstly, a Piecewise Homogeneous Markov Process (PHMP) is employed to model the mode transitions of system parameters and controllers, accurately capturing the dynamic characteristics of practical systems and providing a solid foundation for subsequent controller design. In response to the challenges arising from hybrid cyber-attacks, a novel controller is developed based on an input retention strategy. This ensures system stability under hybrid cyber-attacks, effectively avoiding the instability issues caused by traditional zero-input strategies and enhancing control robustness. To further optimize system performance, an improved Resilient Adaptive Event-triggered Mechanism (RAETM) is proposed. By optimizing triggering conditions and thresholds, the mechanism reduces communication overhead while strengthening system security, making it well-suited for networked control systems. In addition, a generalized common Lyapunov functional is constructed by incorporating sampling instants, time delays, and Markov jump parameters. Sufficient conditions for system synchronization and stability are derived, providing a simplified analytical framework. Finally, the effectiveness and superiority of the proposed approach are confirmed through simulation results, showcasing its robust performance against hybrid cyber-attacks and its ability to achieve secure synchronization.
{"title":"Input-Retention Strategies for Secure Synchronization of Piecewise Markov Neural Networks Under Hybrid Cyber-Attacks","authors":"Yuting Cao;Shanshan Zhao;Shiping Wen;Tingwen Huang","doi":"10.1109/TCSI.2025.3559210","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559210","url":null,"abstract":"How to achieve synchronization control for Piecewise Homogeneous Markov Delayed Neural Networks (PHMDNNs) under hybrid cyber-attacks is the primary focus of this research. Firstly, a Piecewise Homogeneous Markov Process (PHMP) is employed to model the mode transitions of system parameters and controllers, accurately capturing the dynamic characteristics of practical systems and providing a solid foundation for subsequent controller design. In response to the challenges arising from hybrid cyber-attacks, a novel controller is developed based on an input retention strategy. This ensures system stability under hybrid cyber-attacks, effectively avoiding the instability issues caused by traditional zero-input strategies and enhancing control robustness. To further optimize system performance, an improved Resilient Adaptive Event-triggered Mechanism (RAETM) is proposed. By optimizing triggering conditions and thresholds, the mechanism reduces communication overhead while strengthening system security, making it well-suited for networked control systems. In addition, a generalized common Lyapunov functional is constructed by incorporating sampling instants, time delays, and Markov jump parameters. Sufficient conditions for system synchronization and stability are derived, providing a simplified analytical framework. Finally, the effectiveness and superiority of the proposed approach are confirmed through simulation results, showcasing its robust performance against hybrid cyber-attacks and its ability to achieve secure synchronization.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 11","pages":"7252-7262"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCSI.2025.3559805
Fakir Sharif Hossain;Ashek Seum;Md. Reasad Zaman Chowdhury;Foisal Ahmed
Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.
{"title":"ZDD: A Zero Delay Deviation Variability-Aware Golden Free Hardware Trojan Detection Using Physical Unclonable Function","authors":"Fakir Sharif Hossain;Ashek Seum;Md. Reasad Zaman Chowdhury;Foisal Ahmed","doi":"10.1109/TCSI.2025.3559805","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559805","url":null,"abstract":"Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4153-4166"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCSI.2025.3559719
Hong Jiang;Guangren Duan;Mingzhe Hou
In this paper, a robust adaptive control scheme based on the unknown input observer is proposed for fully actuated systems with uncertainties. First, a nonlinear reduced-order unknown input observer with an integral term is introduced to decouple the uncertainties in the system and suppresses the output noises via the action of integral term. Then the linear matrix inequality for solving the observer gains is given by using the linear parameter varying method to treat the nonlinearity. Second, a robust adaptive controller based on the proposed observer, with the adaptive law to estimate the bound of uncertainties, is designed to make the states uniformly ultimately bounded. Due to the design of robust part, the ultimate bounds of states of the closed-loop system can be adjusted via the designed parameters. A simulation of the electromechanical system is given to demonstrate the effectiveness of the proposed method.
{"title":"Robust Adaptive Control Based on Reduced-Order Unknown Input Observer for Fully Actuated Systems With Uncertainties","authors":"Hong Jiang;Guangren Duan;Mingzhe Hou","doi":"10.1109/TCSI.2025.3559719","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559719","url":null,"abstract":"In this paper, a robust adaptive control scheme based on the unknown input observer is proposed for fully actuated systems with uncertainties. First, a nonlinear reduced-order unknown input observer with an integral term is introduced to decouple the uncertainties in the system and suppresses the output noises via the action of integral term. Then the linear matrix inequality for solving the observer gains is given by using the linear parameter varying method to treat the nonlinearity. Second, a robust adaptive controller based on the proposed observer, with the adaptive law to estimate the bound of uncertainties, is designed to make the states uniformly ultimately bounded. Due to the design of robust part, the ultimate bounds of states of the closed-loop system can be adjusted via the designed parameters. A simulation of the electromechanical system is given to demonstrate the effectiveness of the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 9","pages":"4946-4956"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145057454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCSI.2025.3560295
Kai Yu;Ruixin Wu;Sizhen Li;Junfeng Gao;Mo Huang
This paper presents an enhanced three-level buck converter (E3LBC) with configurable power stage (CPS) and configurable control stage (CCS) for fast load transient response. Compared with the conventional 3LBC and existing solutions, the proposed CPS can raise the inductor current slope significantly by changing the switching node voltage to 3/2 times or −1/2 times the input voltage ($V_{mathrm {IN}}$ ) during the load-increasing or load-decreasing transient, which will improve the load transient response. Moreover, the CPS can realize the series or parallel operations of flying capacitors ($C_{mathrm {F1,}}~C_{mathrm {F2}}$ ) and make their voltages ($V_{mathrm {CF1}}$ , $V_{mathrm {CF2}}$ ) eventually converge to $V_{mathrm {IN}}$ /2. On the other hand, the proposed CCS can eliminate the minimum off or on time by using hysteresis control and keep the inductor charging or discharging all the time during the load-increasing or load-decreasing transient for further improving load transient response. Besides, the CCS can provide an adaptive-on-time control in the steady state to acquire a pseudo-constant frequency for small output voltage ripple. The prototype design has been fabricated with the 0.18-$mu $ m CMOS process. According to the measurement results, the E3LBC exhibits undershoot/overshoot voltages and settling time of −19/+30 mV and 1.2/$1.1~mu $ s, when the load current is changed between 100 mA and 500 mA. The other measurements and comparisons also verify the effectiveness of CPS and CCS for the E3LBC.
{"title":"Design of Enhanced Three-Level Buck Converter With Configurable Power and Control Stages for Fast Load Transient Response","authors":"Kai Yu;Ruixin Wu;Sizhen Li;Junfeng Gao;Mo Huang","doi":"10.1109/TCSI.2025.3560295","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560295","url":null,"abstract":"This paper presents an enhanced three-level buck converter (E3LBC) with configurable power stage (CPS) and configurable control stage (CCS) for fast load transient response. Compared with the conventional 3LBC and existing solutions, the proposed CPS can raise the inductor current slope significantly by changing the switching node voltage to 3/2 times or −1/2 times the input voltage (<inline-formula> <tex-math>$V_{mathrm {IN}}$ </tex-math></inline-formula>) during the load-increasing or load-decreasing transient, which will improve the load transient response. Moreover, the CPS can realize the series or parallel operations of flying capacitors (<inline-formula> <tex-math>$C_{mathrm {F1,}}~C_{mathrm {F2}}$ </tex-math></inline-formula>) and make their voltages (<inline-formula> <tex-math>$V_{mathrm {CF1}}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$V_{mathrm {CF2}}$ </tex-math></inline-formula>) eventually converge to <inline-formula> <tex-math>$V_{mathrm {IN}}$ </tex-math></inline-formula>/2. On the other hand, the proposed CCS can eliminate the minimum off or on time by using hysteresis control and keep the inductor charging or discharging all the time during the load-increasing or load-decreasing transient for further improving load transient response. Besides, the CCS can provide an adaptive-on-time control in the steady state to acquire a pseudo-constant frequency for small output voltage ripple. The prototype design has been fabricated with the 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process. According to the measurement results, the E3LBC exhibits undershoot/overshoot voltages and settling time of −19/+30 mV and 1.2/<inline-formula> <tex-math>$1.1~mu $ </tex-math></inline-formula>s, when the load current is changed between 100 mA and 500 mA. The other measurements and comparisons also verify the effectiveness of CPS and CCS for the E3LBC.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 11","pages":"7401-7410"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A tradeoff between bandwidth and back-off range is commonly found in the Doherty power amplifier (DPA). This paper proposes an input phase control mechanism together with a cooperative asymmetric out-phased current load modulation technique. The cooperative asymmetric out-phased current load modulation can extend the output back-off range (OBO). The input phase control mechanism together with modified impedance transforming load modulation networks (LMNs) is used to widen the DPA bandwidth. An input coupled-line coupler is implemented to realize this phase requirement. For demonstration purposes, a DPA with an operating frequency from 1.7 GHz to 2.9 GHz and with a 9-dB OBO range is designed and fabricated using GaN HEMT devices. Continuous-wave measurements show that the implemented DPA exhibits a drain efficiency ranging from 54.5% to 75.6% at saturation and from 41% to 50.6% at 9-dB OBO across the operating bandwidth. When excited by a 20-MHz long-term evolution (LTE) signal with a 9-dB peak-to-average power ratio (PAPR), the implemented DPA achieves average drain efficiencies of 41%- 53.8% with an adjacent channel leakage ratio (ACLR) better than −48.1 dBc after digital predistortion (DPD).
{"title":"Input Phase Controlled Doherty Power Amplifier With Out-Phased Current Load Modulation for Arbitrary Output Back-Off","authors":"Bai Hua Zeng;Yu Fei Pan;Fu Cheng Yuan;Wing Shing Chan;Shao Yong Zheng","doi":"10.1109/TCSI.2025.3557496","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557496","url":null,"abstract":"A tradeoff between bandwidth and back-off range is commonly found in the Doherty power amplifier (DPA). This paper proposes an input phase control mechanism together with a cooperative asymmetric out-phased current load modulation technique. The cooperative asymmetric out-phased current load modulation can extend the output back-off range (OBO). The input phase control mechanism together with modified impedance transforming load modulation networks (LMNs) is used to widen the DPA bandwidth. An input coupled-line coupler is implemented to realize this phase requirement. For demonstration purposes, a DPA with an operating frequency from 1.7 GHz to 2.9 GHz and with a 9-dB OBO range is designed and fabricated using GaN HEMT devices. Continuous-wave measurements show that the implemented DPA exhibits a drain efficiency ranging from 54.5% to 75.6% at saturation and from 41% to 50.6% at 9-dB OBO across the operating bandwidth. When excited by a 20-MHz long-term evolution (LTE) signal with a 9-dB peak-to-average power ratio (PAPR), the implemented DPA achieves average drain efficiencies of 41%- 53.8% with an adjacent channel leakage ratio (ACLR) better than −48.1 dBc after digital predistortion (DPD).","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2626-2638"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-21DOI: 10.1109/TCSI.2025.3559987
Jun-Lan Wang;Xiao-Jian Li
This paper investigates the data-based attack detection and identification for cyber-physical systems (CPSs) under sparse sensor attacks. In order to improve the identification performance, a novel scheme based on an iterative reweighted $l_{2}/l_{1}$ minimization algorithm is presented. Firstly, a threshold that characterizes the maximum number of identifiable attacks is determined. By introducing the reweighting technique, smaller weights are assigned to the relatively easy-to-identify attacks, namely, blocks with larger $l_{2}$ -norms, thus forcing the minimization to focus on the ones with smaller $l_{2}$ -norms. Then, the number of identifiable attacks is enhanced and a higher identification accuracy is guaranteed compared with the existing results. Finally, three examples are given to verify the effectiveness and advantages of the proposed scheme in both noisy and noiseless cases.
{"title":"Data-Driven Attack Detection and Identification for Cyber-Physical Systems Under Sparse Sensor Attacks: Iterative Reweighted l2/l1 Recovery Approach","authors":"Jun-Lan Wang;Xiao-Jian Li","doi":"10.1109/TCSI.2025.3559987","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559987","url":null,"abstract":"This paper investigates the data-based attack detection and identification for cyber-physical systems (CPSs) under sparse sensor attacks. In order to improve the identification performance, a novel scheme based on an iterative reweighted <inline-formula> <tex-math>$l_{2}/l_{1}$ </tex-math></inline-formula> minimization algorithm is presented. Firstly, a threshold that characterizes the maximum number of identifiable attacks is determined. By introducing the reweighting technique, smaller weights are assigned to the relatively easy-to-identify attacks, namely, blocks with larger <inline-formula> <tex-math>$l_{2}$ </tex-math></inline-formula>-norms, thus forcing the minimization to focus on the ones with smaller <inline-formula> <tex-math>$l_{2}$ </tex-math></inline-formula>-norms. Then, the number of identifiable attacks is enhanced and a higher identification accuracy is guaranteed compared with the existing results. Finally, three examples are given to verify the effectiveness and advantages of the proposed scheme in both noisy and noiseless cases.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2890-2902"},"PeriodicalIF":5.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the DC microgrid cluster system, due to the large number of converters, there are many operation modes and switching frequencies. The traditional modeling methods are difficult to balance the accuracy of the model and the simplicity of calculation and are not suitable for different switching frequency systems. In view of the above problems, this paper uses simplified discrete time mapping model to model the system. It combines the state space average model with the discrete time mapping model, which greatly improves the simplicity and accuracy of modeling. Taking the photovoltaic-energy storage system as an example, this paper analyzes the nonlinear behavior of the system and predicts the critical control parameters when the Hopf bifurcation occurs in the system. The eigenvalue sensitivity analysis is used to determine the eigenvalue change rate and change trend when the control parameters change, which provides guidance for the selection of parameters in practical applications. Finally, the high precision of the model is verified by simulation, and the applicability and effectiveness of the method in different switching frequency systems are verified by experiments.
{"title":"Modeling and Nonlinear Dynamic Behavior Analysis of Photovoltaic-Energy Storage DC Microgrid","authors":"Ronglong Wang;Fan Xie;Bo Zhang;Dongyuan Qiu;Wenxun Xiao;Yanfeng Chen","doi":"10.1109/TCSI.2025.3558905","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3558905","url":null,"abstract":"In the DC microgrid cluster system, due to the large number of converters, there are many operation modes and switching frequencies. The traditional modeling methods are difficult to balance the accuracy of the model and the simplicity of calculation and are not suitable for different switching frequency systems. In view of the above problems, this paper uses simplified discrete time mapping model to model the system. It combines the state space average model with the discrete time mapping model, which greatly improves the simplicity and accuracy of modeling. Taking the photovoltaic-energy storage system as an example, this paper analyzes the nonlinear behavior of the system and predicts the critical control parameters when the Hopf bifurcation occurs in the system. The eigenvalue sensitivity analysis is used to determine the eigenvalue change rate and change trend when the control parameters change, which provides guidance for the selection of parameters in practical applications. Finally, the high precision of the model is verified by simulation, and the applicability and effectiveness of the method in different switching frequency systems are verified by experiments.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2778-2791"},"PeriodicalIF":5.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-18DOI: 10.1109/TCSI.2025.3559727
Dong Liang;Hui Zhang;Yetong Wang;Linhao Ma;Shiyue Ma;Zhijun Zhou;Fanyi Meng;Kaixue Ma;Keping Wang
An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.
{"title":"Design of Oscillator-Based Reconfigurable Modulator With High-Q FBAR Resonators Supporting Fast OOK/BFSK/ BPSK Modulation","authors":"Dong Liang;Hui Zhang;Yetong Wang;Linhao Ma;Shiyue Ma;Zhijun Zhou;Fanyi Meng;Kaixue Ma;Keping Wang","doi":"10.1109/TCSI.2025.3559727","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559727","url":null,"abstract":"An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2543-2555"},"PeriodicalIF":5.2,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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