Pub Date : 2024-09-24DOI: 10.1109/TCSI.2024.3461770
Amina Haroon;Ram Krishna Ghosh;Sneh Saurabh
Probabilistic computing is a promising computational paradigm that harnesses the inherent stochasticity of devices to tackle problems that can benefit from stochastic-driven search. A probabilistic bit (p-bit), the workhorse of probabilistic computing, is popularly implemented using energy-efficient low-barrier nanomagnets, highly-scaled transistors, and unstable memory elements. These implementations are prone to process- and environmental-induced variations and aging-induced non-idealities. These non-idealities can manifest as unwanted bias in a p-bit and its incoming signals, impacting the figures of merit of probabilistic computing. For the first time, this work systematically investigates this aspect of probabilistic computing. First, we investigate the behavior of a non-ideal p-bit using an analytical model proposed in this work and corroborate the results using numerical computation. Then, we examine the impact of these non-idealities on the functionality and robustness of the probabilistic computing using Boolean logic implementation and image completion networks in the forward and backward modes of operation, respectively. For Boolean logic implementation, the weight matrix is found to be robust enough to allow p-bit network to retain its intended functionality despite non-idealities. Moreover, we show that there can be canceling effects of non-idealities, which can potentially be utilized in compensating reliability-induced degradation in a p-bit network. Additionally, using 1T-1MTJ-based p-bit implementation and SPICE simulations, we illustrate the applicability of the proposed model in analyzing and assessing the impact of non-idealities and process-induced variations on a p-bit network. We also demonstrate that statistical analysis techniques, such as Monte Carlo simulations, can help derive application-dependent constraints on the non-ideality of p-bits. These constraints will serve as critical design criteria for future p-bit implementations.
概率计算是一种前景广阔的计算范式，它利用设备固有的随机性来解决可以受益于随机驱动搜索的问题。概率比特（p-bit）是概率计算的主力，目前普遍使用高能效低势垒纳米磁体、高比例晶体管和不稳定存储元件来实现。这些实现方式很容易受到工艺和环境引起的变化以及老化引起的非理想状态的影响。这些非理想性可能会在 p 位及其输入信号中表现为不必要的偏差，从而影响概率计算的性能指标。这项工作首次系统地研究了概率计算的这一方面。首先，我们利用本文提出的分析模型研究了非理想 p 位的行为，并利用数值计算证实了结果。然后，我们利用布尔逻辑实现和图像补全网络，分别在前向和后向操作模式下研究了这些非理想性对概率计算功能和鲁棒性的影响。对于布尔逻辑实现，我们发现权重矩阵具有足够的稳健性，可以让 p 位网络在非理想情况下保持其预期功能。此外，我们还展示了非理想状态的抵消效应，这种效应可用于补偿 p 位网络中由可靠性引起的性能下降。此外，我们还利用基于 1T-1MTJ 的 p 位实现和 SPICE 仿真，说明了所提模型在分析和评估非理想性和流程引起的变化对 p 位网络的影响方面的适用性。我们还证明了蒙特卡罗模拟等统计分析技术有助于得出 p 位非理想性的应用约束。这些约束将作为未来 p 位实施的关键设计标准。
{"title":"Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis","authors":"Amina Haroon;Ram Krishna Ghosh;Sneh Saurabh","doi":"10.1109/TCSI.2024.3461770","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3461770","url":null,"abstract":"Probabilistic computing is a promising computational paradigm that harnesses the inherent stochasticity of devices to tackle problems that can benefit from stochastic-driven search. A probabilistic bit (p-bit), the workhorse of probabilistic computing, is popularly implemented using energy-efficient low-barrier nanomagnets, highly-scaled transistors, and unstable memory elements. These implementations are prone to process- and environmental-induced variations and aging-induced non-idealities. These non-idealities can manifest as unwanted bias in a p-bit and its incoming signals, impacting the figures of merit of probabilistic computing. For the first time, this work systematically investigates this aspect of probabilistic computing. First, we investigate the behavior of a non-ideal p-bit using an analytical model proposed in this work and corroborate the results using numerical computation. Then, we examine the impact of these non-idealities on the functionality and robustness of the probabilistic computing using Boolean logic implementation and image completion networks in the forward and backward modes of operation, respectively. For Boolean logic implementation, the weight matrix is found to be robust enough to allow p-bit network to retain its intended functionality despite non-idealities. Moreover, we show that there can be canceling effects of non-idealities, which can potentially be utilized in compensating reliability-induced degradation in a p-bit network. Additionally, using 1T-1MTJ-based p-bit implementation and SPICE simulations, we illustrate the applicability of the proposed model in analyzing and assessing the impact of non-idealities and process-induced variations on a p-bit network. We also demonstrate that statistical analysis techniques, such as Monte Carlo simulations, can help derive application-dependent constraints on the non-ideality of p-bits. These constraints will serve as critical design criteria for future p-bit implementations.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6279-6291"},"PeriodicalIF":5.2,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-24DOI: 10.1109/TCSI.2024.3461741
Xiaowei Wang;Zhiqun Li;Zhennan Li;Yan Yao;Hongwei Guo;Dong Chen;Zhiying Xia;Jiancong Du
A wideband high dynamic range software radio receiver for sub-6-GHz applications is proposed. The receiver combines three gain variable modules and an automatic gain control module to achieve high gain dynamic range and constant output voltage. A broadband resistive feedback LNA was designed, and two novel gain switching methods were proposed for the resistive feedback LNA, which reduced the LNA gain while optimizing the input matching performance. In addition, the receiver adopts a voltage mode mixer and uses the impedance translation property to achieve blocker-tolerant performance. In analog baseband (ABB), a fourth-order Butterworth active-RC low-pass filter (LPF) is employed for the purpose of attenuating interference. Furthermore, the receiver is furnished with an automatic gain control amplifier to uphold a consistent output voltage amplitude. A 22 nm CMOS receiver prototype occupies 1.85 mm2 and consumes 51 mW from a 1 V power supply over the 2–6 GHz operating frequency range. The receiver achieves a gain dynamic range of 9.1-91.9 dB and a noise figure (NF) of 2.4-3.4 dB. When a 0 dBm blocker with a frequency offset of 80 MHz is injected into the receiver, the NF increases to 13.2 dB. The programmable bandwidth of the LPF can be adjusted from 10 to 160 MHz. Moreover, the receiver achieved an in-band third-order input-referred intercept point (IIP3) of −9.1 dBm and an out-of-band IIP3 of −2.9 dBm respectively.
{"title":"A 2–6 GHz Reconfigurable High Dynamic Range Receiver With Wideband Variable Gain LNA","authors":"Xiaowei Wang;Zhiqun Li;Zhennan Li;Yan Yao;Hongwei Guo;Dong Chen;Zhiying Xia;Jiancong Du","doi":"10.1109/TCSI.2024.3461741","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3461741","url":null,"abstract":"A wideband high dynamic range software radio receiver for sub-6-GHz applications is proposed. The receiver combines three gain variable modules and an automatic gain control module to achieve high gain dynamic range and constant output voltage. A broadband resistive feedback LNA was designed, and two novel gain switching methods were proposed for the resistive feedback LNA, which reduced the LNA gain while optimizing the input matching performance. In addition, the receiver adopts a voltage mode mixer and uses the impedance translation property to achieve blocker-tolerant performance. In analog baseband (ABB), a fourth-order Butterworth active-RC low-pass filter (LPF) is employed for the purpose of attenuating interference. Furthermore, the receiver is furnished with an automatic gain control amplifier to uphold a consistent output voltage amplitude. A 22 nm CMOS receiver prototype occupies 1.85 mm2 and consumes 51 mW from a 1 V power supply over the 2–6 GHz operating frequency range. The receiver achieves a gain dynamic range of 9.1-91.9 dB and a noise figure (NF) of 2.4-3.4 dB. When a 0 dBm blocker with a frequency offset of 80 MHz is injected into the receiver, the NF increases to 13.2 dB. The programmable bandwidth of the LPF can be adjusted from 10 to 160 MHz. Moreover, the receiver achieved an in-band third-order input-referred intercept point (IIP3) of −9.1 dBm and an out-of-band IIP3 of −2.9 dBm respectively.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"741-752"},"PeriodicalIF":5.2,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143184416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-24DOI: 10.1109/TCSI.2024.3461736
Yan Xu;Lin Ding;Penggao He;Zhaojun Lu;Jiliang Zhang
Polynomial multiplication (PM) is the computational bottleneck of lattice-based cryptography, such as post-quantum cryptography (PQC). Designing dedicated hardware accelerators for polynomial multiplication is an effective solution to improve the execution speed. However, current mainstream designs ignore the impact of computing array size, resulting in poor design flexibility and low memory utilization. To address these issues, we propose Meta, a memory-efficient tri-stage PM accelerator. Our proposed tri-stage PM algorithm fuses all isolated substages into a unique stage named fused coefficient-wise multiplication (FCWM), ensuring efficient computation. Meanwhile, in different stages of the algorithm, the circuit of two-dimensional reconfigurable coupled butterfly units (2D-RCBFUs) is fine-grained reconfigured to improve resource utilization. Moreover, the low-complexity memory mapping scheme simplifies the address control logic and reduces the hardware overhead. Meta can efficiently support the PM of an arbitrary power of two, which is impossible for previous designs using a 2D computing array. Compared with the state-of-the-art designs, our Meta demonstrates the best memory utilization, achieving up to $10.0times $ performance improvement.
{"title":"Meta: A Memory-Efficient Tri-Stage Polynomial Multiplication Accelerator Using 2D Coupled-BFUs","authors":"Yan Xu;Lin Ding;Penggao He;Zhaojun Lu;Jiliang Zhang","doi":"10.1109/TCSI.2024.3461736","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3461736","url":null,"abstract":"Polynomial multiplication (PM) is the computational bottleneck of lattice-based cryptography, such as post-quantum cryptography (PQC). Designing dedicated hardware accelerators for polynomial multiplication is an effective solution to improve the execution speed. However, current mainstream designs ignore the impact of computing array size, resulting in poor design flexibility and low memory utilization. To address these issues, we propose Meta, a memory-efficient tri-stage PM accelerator. Our proposed tri-stage PM algorithm fuses all isolated substages into a unique stage named fused coefficient-wise multiplication (FCWM), ensuring efficient computation. Meanwhile, in different stages of the algorithm, the circuit of two-dimensional reconfigurable coupled butterfly units (2D-RCBFUs) is fine-grained reconfigured to improve resource utilization. Moreover, the low-complexity memory mapping scheme simplifies the address control logic and reduces the hardware overhead. Meta can efficiently support the PM of an arbitrary power of two, which is impossible for previous designs using a 2D computing array. Compared with the state-of-the-art designs, our Meta demonstrates the best memory utilization, achieving up to <inline-formula> <tex-math>$10.0times $ </tex-math></inline-formula> performance improvement.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"647-660"},"PeriodicalIF":5.2,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, conducting detailed numerical simulation of power electronic (PE) converters is time-consuming due to the iterative solution of nonlinear equations. While simplified numerical models can reduce the computational burden, they are unable to guarantee fidelity in highly nonlinear systems. To accelerate the detailed numerical simulation while maintaining high fidelity, this paper proposes a novel data-driven approach to modeling PE converters based on neural ordinary differential equations (ODE). This model eliminates the iterative solution of nonlinear equations by being data-driven and thus accelerates the simulation. In addition, to enhance the model fidelity, this approach incorporates prior knowledge about numerical ODE solvers into the model structures and distinguishes multi-scale characteristics from the dataset using a specific filtered MSE loss function. Experiment results demonstrate significant improvement of calculation speed and reduction of computational overheads compared to the detailed numerical methods. In addition, the proposed model has shown excellent modeling fidelity across various input frequencies using variable step solvers.
如今，由于非线性方程的迭代求解，对电力电子（PE）转换器进行详细的数值模拟非常耗时。虽然简化数值模型可以减轻计算负担，但却无法保证高度非线性系统的真实性。为了在保持高保真度的同时加快详细的数值模拟，本文提出了一种基于神经常微分方程（ODE）的新颖数据驱动方法来模拟 PE 转换器。该模型通过数据驱动，消除了非线性方程的迭代求解，从而加快了仿真速度。此外，为了提高模型的保真度，该方法将有关数值 ODE 求解器的先验知识纳入模型结构，并使用特定的滤波 MSE 损失函数从数据集中区分多尺度特征。实验结果表明，与详细的数值方法相比，计算速度明显提高，计算开销明显减少。此外，利用可变步长求解器，所提出的模型在各种输入频率下都显示出出色的建模保真度。
{"title":"Neural ODE Model of Power Electronic Converters With Accelerated Computation and High Fidelity","authors":"Hanchen Ge;Yaofeng Liang;Jinpeng Lei;Canjun Yuan;Zhicong Huang","doi":"10.1109/TCSI.2024.3460803","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3460803","url":null,"abstract":"Nowadays, conducting detailed numerical simulation of power electronic (PE) converters is time-consuming due to the iterative solution of nonlinear equations. While simplified numerical models can reduce the computational burden, they are unable to guarantee fidelity in highly nonlinear systems. To accelerate the detailed numerical simulation while maintaining high fidelity, this paper proposes a novel data-driven approach to modeling PE converters based on neural ordinary differential equations (ODE). This model eliminates the iterative solution of nonlinear equations by being data-driven and thus accelerates the simulation. In addition, to enhance the model fidelity, this approach incorporates prior knowledge about numerical ODE solvers into the model structures and distinguishes multi-scale characteristics from the dataset using a specific filtered MSE loss function. Experiment results demonstrate significant improvement of calculation speed and reduction of computational overheads compared to the detailed numerical methods. In addition, the proposed model has shown excellent modeling fidelity across various input frequencies using variable step solvers.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6363-6374"},"PeriodicalIF":5.2,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-23DOI: 10.1109/TCSI.2024.3443180
Fang-Yi Gu;Cheng-Han Yang;Ing-Chao Lin;Da-Wei Chang;Darsen D. Lu;Ulf Schlichtmann
Emerging resistive random access memory (RRAM) attracts considerable interest in computing-in-memory by its high efficiency in multiply-accumulate operation, which is the key computation in the neural network (NN). However, due to the imperfect fabrication, RRAM cells suffer from the variations, which make the values in RRAM cells deviate from the target values so that the accuracy of the RRAM-based NN accelerator degrades significantly. Moreover, in a practical hardware design of RRAM-based NN accelerators, if the number of wordlines and bitlines in a crossbar array activated at the same time increases, ADCs with a high resolution are required and the power consumption of ADC increases. This paper proposes a novel methodology to mitigate the impact of variations in RRAM-based neural network accelerators. The methodology includes a unary-based non-uniform quantization method and a variation-aware operation unit (OU) based framework. The unary-based non-uniform quantization method equalizes the significance of weights stored in each RRAM cell to reduce the impact of variations. The variation-aware OU-based framework activates only RRAM cells in the same OU at the same time, which reduces the power consumption of ADCs. Additionally, the framework introduces three methods, including OU skipping, OU recombination, and OU compensation, to further mitigate the impact of variations. The experiments show that the proposed approach outperforms the state-of-the-art among four NN models on two datasets with 2-bit cell resolution.
新兴的电阻式随机存取存储器（RRAM）在神经网络（NN）的关键计算--乘积运算中具有很高的效率，因此在内存计算领域引起了广泛关注。然而，由于制造工艺的不完善，RRAM 单元会出现偏差，使 RRAM 单元中的值偏离目标值，从而使基于 RRAM 的神经网络加速器的精度大大降低。此外，在基于 RRAM 的 NN 加速器的实际硬件设计中，如果交叉条阵列中同时激活的字线和位线数量增加，则需要高分辨率的 ADC，ADC 的功耗也会增加。本文提出了一种新方法来减轻基于 RRAM 的神经网络加速器的变化影响。该方法包括基于一元的非均匀量化方法和基于变化感知操作单元（OU）的框架。基于一元的非均匀量化方法均衡了存储在每个 RRAM 单元中的权重的重要性，以减少变异的影响。基于变异感知操作单元的框架只在同一时间激活同一操作单元中的 RRAM 单元，从而降低了 ADC 的功耗。此外，该框架还引入了三种方法，包括 OU 跳过、OU 重组和 OU 补偿，以进一步减轻变化的影响。实验表明，在两个单元分辨率为 2 位的数据集上，在四种 NN 模型中，所提出的方法优于最先进的方法。
{"title":"A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing","authors":"Fang-Yi Gu;Cheng-Han Yang;Ing-Chao Lin;Da-Wei Chang;Darsen D. Lu;Ulf Schlichtmann","doi":"10.1109/TCSI.2024.3443180","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3443180","url":null,"abstract":"Emerging resistive random access memory (RRAM) attracts considerable interest in computing-in-memory by its high efficiency in multiply-accumulate operation, which is the key computation in the neural network (NN). However, due to the imperfect fabrication, RRAM cells suffer from the variations, which make the values in RRAM cells deviate from the target values so that the accuracy of the RRAM-based NN accelerator degrades significantly. Moreover, in a practical hardware design of RRAM-based NN accelerators, if the number of wordlines and bitlines in a crossbar array activated at the same time increases, ADCs with a high resolution are required and the power consumption of ADC increases. This paper proposes a novel methodology to mitigate the impact of variations in RRAM-based neural network accelerators. The methodology includes a unary-based non-uniform quantization method and a variation-aware operation unit (OU) based framework. The unary-based non-uniform quantization method equalizes the significance of weights stored in each RRAM cell to reduce the impact of variations. The variation-aware OU-based framework activates only RRAM cells in the same OU at the same time, which reduces the power consumption of ADCs. Additionally, the framework introduces three methods, including OU skipping, OU recombination, and OU compensation, to further mitigate the impact of variations. The experiments show that the proposed approach outperforms the state-of-the-art among four NN models on two datasets with 2-bit cell resolution.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"6419-6432"},"PeriodicalIF":5.2,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Secure communication techniques can protect data confidentiality during transmission through public channels. Chaotic systems are commonly used in secure communication due to their random-like behavior, unpredictability, and ergodicity. However, existing chaos-based secure communication schemes have some drawbacks concerning the chaotic systems used and the communication structures, so they cannot achieve satisfactory performance to resist transmission channel noise. In light of this, in this paper, we propose a two-dimensional (2D) cyclic chaotic system (2D-CCS) and design a novel chaos-based secure communication scheme called noise-reduced orthogonal frequency division multiplexing based differential chaos shift keying (NR-OFDM-DCSK). The 2D-CCS is a general framework that can generate a large number of new 2D chaotic maps using existing one-dimensional (1D) chaotic maps as seed maps. Theoretical analysis and experiment results demonstrate its robust chaotic behaviors. The NR-OFDM-DCSK employs a new chaotic map generated by 2D-CCS as the chaos generator, and its structure exhibits a strong ability to resist channel noise, as demonstrated by formulaic analysis. Our extensive experiments show that our developed 2D chaotic maps are more suitable for secure communication applications than existing 2D chaotic maps, and our NR-OFDM-DCSK can achieve a lower bit-error-rate (BER) than state-of-the-art secure communication schemes.
{"title":"Two-Dimensional Cyclic Chaotic System for Noise-Reduced OFDM-DCSK Communication","authors":"Zhongyun Hua;Zihua Wu;Yinxing Zhang;Han Bao;Yicong Zhou","doi":"10.1109/TCSI.2024.3454535","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3454535","url":null,"abstract":"Secure communication techniques can protect data confidentiality during transmission through public channels. Chaotic systems are commonly used in secure communication due to their random-like behavior, unpredictability, and ergodicity. However, existing chaos-based secure communication schemes have some drawbacks concerning the chaotic systems used and the communication structures, so they cannot achieve satisfactory performance to resist transmission channel noise. In light of this, in this paper, we propose a two-dimensional (2D) cyclic chaotic system (2D-CCS) and design a novel chaos-based secure communication scheme called noise-reduced orthogonal frequency division multiplexing based differential chaos shift keying (NR-OFDM-DCSK). The 2D-CCS is a general framework that can generate a large number of new 2D chaotic maps using existing one-dimensional (1D) chaotic maps as seed maps. Theoretical analysis and experiment results demonstrate its robust chaotic behaviors. The NR-OFDM-DCSK employs a new chaotic map generated by 2D-CCS as the chaos generator, and its structure exhibits a strong ability to resist channel noise, as demonstrated by formulaic analysis. Our extensive experiments show that our developed 2D chaotic maps are more suitable for secure communication applications than existing 2D chaotic maps, and our NR-OFDM-DCSK can achieve a lower bit-error-rate (BER) than state-of-the-art secure communication schemes.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"323-336"},"PeriodicalIF":5.2,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/tcsi.2024.3455409
Chenyu Wang, Jun Zheng, Yining Qian
{"title":"Structure-Varying Complex Network Chaotic Model and Its Hardware Implementation","authors":"Chenyu Wang, Jun Zheng, Yining Qian","doi":"10.1109/tcsi.2024.3455409","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3455409","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"122 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142268940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/TCSI.2024.3458864
Esfandiar Esmaieli;Yasser Sedaghat;Ali Peiravi
Soft errors in Integrated Circuits (ICs) have always been a major concern, particularly as CMOS technology nodes continue to shrink, resulting in higher frequency, lower power, and smaller areas, exacerbating radiation-induced soft errors. Therefore, Single Event Transient (SET) has become a crucial consideration in designing modern radiation-tolerant circuits, as it has the potential to cause failures in circuit outputs. This paper employs the concept of signal probability for transient fault propagation in circuits. Considering the issue of transient fault-masking, an error propagation model is presented for each fault-masking case. Furthermore, approaches are proposed for both probabilistic and time-based scenarios to address the impact of re-convergent paths on transient error propagation. Since considering re-convergent paths increases computational complexity, three computational algorithms are proposed in this paper aiming to reduce the size of the probability matrix as much as possible. We compared the simulation results with the Monte-Carlo method and HSPICE-based simulation to validate the proposed method. According to the simulation results on ISCAS’85 benchmarks, the proposed approach for estimating the single event rate exhibits an average relative error percentage of less than 5% compared to traditional fault injection estimation.
{"title":"Fanout-Based Reliability Model for SER Estimation in Combinational Circuits","authors":"Esfandiar Esmaieli;Yasser Sedaghat;Ali Peiravi","doi":"10.1109/TCSI.2024.3458864","DOIUrl":"10.1109/TCSI.2024.3458864","url":null,"abstract":"Soft errors in Integrated Circuits (ICs) have always been a major concern, particularly as CMOS technology nodes continue to shrink, resulting in higher frequency, lower power, and smaller areas, exacerbating radiation-induced soft errors. Therefore, Single Event Transient (SET) has become a crucial consideration in designing modern radiation-tolerant circuits, as it has the potential to cause failures in circuit outputs. This paper employs the concept of signal probability for transient fault propagation in circuits. Considering the issue of transient fault-masking, an error propagation model is presented for each fault-masking case. Furthermore, approaches are proposed for both probabilistic and time-based scenarios to address the impact of re-convergent paths on transient error propagation. Since considering re-convergent paths increases computational complexity, three computational algorithms are proposed in this paper aiming to reduce the size of the probability matrix as much as possible. We compared the simulation results with the Monte-Carlo method and HSPICE-based simulation to validate the proposed method. According to the simulation results on ISCAS’85 benchmarks, the proposed approach for estimating the single event rate exhibits an average relative error percentage of less than 5% compared to traditional fault injection estimation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"228-240"},"PeriodicalIF":5.2,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/tcsi.2024.3457838
Zhongding Zhang, Zeyu Guo, Zuo Wang, Shihua Li
{"title":"Universal Finite-Time Observer-Based ITSMC for Converter-Driven Motor Systems With Disturbances","authors":"Zhongding Zhang, Zeyu Guo, Zuo Wang, Shihua Li","doi":"10.1109/tcsi.2024.3457838","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3457838","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"44 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：