Pub Date : 2024-08-13DOI: 10.1109/tcsi.2024.3439580
Xiaofang Wu, Xiao Pan, Peng Sun, Jianyang Zhou
{"title":"Scalable Double Crosstalk Canceling Digital Predistortion for MIMO Transmitters","authors":"Xiaofang Wu, Xiao Pan, Peng Sun, Jianyang Zhou","doi":"10.1109/tcsi.2024.3439580","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3439580","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"13 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-13DOI: 10.1109/TCSI.2024.3430378
Siji Huang;Qifeng Huang;Yifei Fan;Qiwei Zhao;Yanhang Chen;Yihan Zhang;Jie Yuan
This paper presents an efficient 8-MS/s 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed symmetric complementary switching (SCS) and split passive reference segmentation (SPRS). Conventionally, improving the SAR ADC speed compromises the signal-to-noise-and-distortion ratio (SNDR) and energy efficiency due to the high precision requirement and the sequential bit-cycling. In this design, the proposed SCS scheme reduces the parasitic capacitance in the sampling path and the settling error of the capacitive digital-to-analog converter (CDAC) with low SNDR and hardware penalties. In addition, to reduce reference ripples, active reference buffers generally consume high power while the passive methods may degrade the SNDR or occupy large areas. To efficiently reduce reference settling errors, an area-efficient SPRS is developed, which suppresses the reference settling error through the split reference segmentation. The prototype chip is fabricated in a 180-nm CMOS process and occupies an area of 0.57 mm2. Measurements show the ADC achieves a peak SNDR of 89.2 dB at 8 MS/s with a 9.5-mW power consumption. The Schreier-figure-of-merit (FoM) is 175.4 dB.
{"title":"An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process","authors":"Siji Huang;Qifeng Huang;Yifei Fan;Qiwei Zhao;Yanhang Chen;Yihan Zhang;Jie Yuan","doi":"10.1109/TCSI.2024.3430378","DOIUrl":"10.1109/TCSI.2024.3430378","url":null,"abstract":"This paper presents an efficient 8-MS/s 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed symmetric complementary switching (SCS) and split passive reference segmentation (SPRS). Conventionally, improving the SAR ADC speed compromises the signal-to-noise-and-distortion ratio (SNDR) and energy efficiency due to the high precision requirement and the sequential bit-cycling. In this design, the proposed SCS scheme reduces the parasitic capacitance in the sampling path and the settling error of the capacitive digital-to-analog converter (CDAC) with low SNDR and hardware penalties. In addition, to reduce reference ripples, active reference buffers generally consume high power while the passive methods may degrade the SNDR or occupy large areas. To efficiently reduce reference settling errors, an area-efficient SPRS is developed, which suppresses the reference settling error through the split reference segmentation. The prototype chip is fabricated in a 180-nm CMOS process and occupies an area of 0.57 mm2. Measurements show the ADC achieves a peak SNDR of 89.2 dB at 8 MS/s with a 9.5-mW power consumption. The Schreier-figure-of-merit (FoM) is 175.4 dB.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4486-4498"},"PeriodicalIF":5.2,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the system-level discussion, simulation design, and fabrication results of a novel analog ASIC - fabricated in 130nm BiCMOS technology - for interfacing resistive thermal sensors known as Fly Height Sensors (FHSs). FHSs are attached to the magnetic recording heads in modern hard disk drives (HDDs) to monitor the head-disk distance known as “fly height” by measuring the FHS resistance variation. The magnitude of the sensor signal serves as a measure of the proximity between the head and the disk surface which must accurately be controlled to minimize the fly height, thereby increasing the storage capacity of HDDs. The proposed interface includes two parts: 1) a dual-mode precise bias circuit that accurately provides a differential bias with a programmable common-mode voltage to the FHS in both voltage (V) and current (I) modes without requiring any calibrations, as well as featuring fast and smooth transient response, 2) front-end gain stages that create two separate signal paths with low- and high-frequency responses, called LF and HF blocks, utilized for controlling the fly height and mapping the roughness of the disk surface, respectively. The proposed bias circuit demonstrates high-impedance loading behavior on the sensor terminals in both V- and I- modes to have a unity signal gain at the sensor port and deliver it to the front-end amplifiers, resulting in an improvement of the overall noise performance of the interface. In addition, the bias noise power at the output of the LF block is suppressed to the extent of one order of magnitude thanks to deploying a noise cancellation technique. A low-noise and wide-bandwidth front-end is implemented for the HF block that eliminates the need for configuring the bias loop for having a low cutoff frequency, resulting in a reliable design with reduced complexity. Additionally, degenerated differential pairs with resistive loads, split tail currents, and Caprio’s quad offering low gain variation over the temperature and process are implemented as the front-end gain stages. The fabricated chip features an active area of 1.28 mm2with power consumption in the range of 110 to $172~mW$ for the V-mode and 78 to $107~mW$ for the I-mode, considering typical supply voltages of $+3.3; V$ and $-2.6 ;V$ , and the sensor resistance ( $R_{SNS} = 75; Omega $ ) and the sensor current ( $I_{SNS}$ ) from 0.5 to $6;mA$ .
{"title":"An Integrated Dual-Mode Precise Bias Circuit and a Low-Noise and Wideband AFE for Fly Height Sensors in Hard Disk Drives","authors":"Mojtaba Mohammadi Abdevand;Dario Livornesi;Alessio Emanuelle Vergani;Francesco Piscitelli;Enrico Mammei;Edoardo Bonizzoni;Piero Malcovati;Paolo Pulici","doi":"10.1109/TCSI.2024.3436034","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3436034","url":null,"abstract":"This paper presents the system-level discussion, simulation design, and fabrication results of a novel analog ASIC - fabricated in 130nm BiCMOS technology - for interfacing resistive thermal sensors known as Fly Height Sensors (FHSs). FHSs are attached to the magnetic recording heads in modern hard disk drives (HDDs) to monitor the head-disk distance known as “fly height” by measuring the FHS resistance variation. The magnitude of the sensor signal serves as a measure of the proximity between the head and the disk surface which must accurately be controlled to minimize the fly height, thereby increasing the storage capacity of HDDs. The proposed interface includes two parts: 1) a dual-mode precise bias circuit that accurately provides a differential bias with a programmable common-mode voltage to the FHS in both voltage (V) and current (I) modes without requiring any calibrations, as well as featuring fast and smooth transient response, 2) front-end gain stages that create two separate signal paths with low- and high-frequency responses, called LF and HF blocks, utilized for controlling the fly height and mapping the roughness of the disk surface, respectively. The proposed bias circuit demonstrates high-impedance loading behavior on the sensor terminals in both V- and I- modes to have a unity signal gain at the sensor port and deliver it to the front-end amplifiers, resulting in an improvement of the overall noise performance of the interface. In addition, the bias noise power at the output of the LF block is suppressed to the extent of one order of magnitude thanks to deploying a noise cancellation technique. A low-noise and wide-bandwidth front-end is implemented for the HF block that eliminates the need for configuring the bias loop for having a low cutoff frequency, resulting in a reliable design with reduced complexity. Additionally, degenerated differential pairs with resistive loads, split tail currents, and Caprio’s quad offering low gain variation over the temperature and process are implemented as the front-end gain stages. The fabricated chip features an active area of 1.28 mm2with power consumption in the range of 110 to \u0000<inline-formula> <tex-math>$172~mW$ </tex-math></inline-formula>\u0000 for the V-mode and 78 to \u0000<inline-formula> <tex-math>$107~mW$ </tex-math></inline-formula>\u0000 for the I-mode, considering typical supply voltages of \u0000<inline-formula> <tex-math>$+3.3; V$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$-2.6 ;V$ </tex-math></inline-formula>\u0000, and the sensor resistance (\u0000<inline-formula> <tex-math>$R_{SNS} = 75; Omega $ </tex-math></inline-formula>\u0000) and the sensor current (\u0000<inline-formula> <tex-math>$I_{SNS}$ </tex-math></inline-formula>\u0000) from 0.5 to \u0000<inline-formula> <tex-math>$6;mA$ </tex-math></inline-formula>\u0000.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4458-4471"},"PeriodicalIF":5.2,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142377008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Open-switch fault of power transistors is a common problem in bidirectional DC/DC converter, which can cause considerable property loss and personal safety risk. However, the traditional model-based fault diagnosis methods mainly focus on the rapidity and rarely consider the parameter change of bidirectional DC/DC converter, which is poor in robustness. Therefore, this paper proposes a robust open-switch fault diagnosis method for bidirectional DC/DC converters in a hybrid energy storage system (HESS) based on extended Kalman filter (EKF) with multiple corrections, where the measured currents on the battery side and the supercapacitor side are used to correct the observed currents obtained by EKF until the residuals between the observed values and the measured values are less than the set correction thresholds, thus avoiding the influence of the parameter variations. The open-switch fault detection is achieved by judging whether the correction times of the currents on the battery side and the supercapacitor side exceed the maximum correction times. The open-switch fault location is achieved through judging whether the corrected value on the fault side exceeds the set correction threshold. The proposed method is validated through simulation and experimental studies. Both the results show the robustness of fault diagnosis for bidirectional DC/DC converter.
{"title":"Robust Open-Switch Fault Diagnosis of Bidirectional DC/DC Converters Based on Extended Kalman Filter With Multiple Corrections","authors":"Shichuan Ding;Dewei Tang;Jun Hang;Jifeng Zhao;Shuonan Gui","doi":"10.1109/TCSI.2024.3421655","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3421655","url":null,"abstract":"Open-switch fault of power transistors is a common problem in bidirectional DC/DC converter, which can cause considerable property loss and personal safety risk. However, the traditional model-based fault diagnosis methods mainly focus on the rapidity and rarely consider the parameter change of bidirectional DC/DC converter, which is poor in robustness. Therefore, this paper proposes a robust open-switch fault diagnosis method for bidirectional DC/DC converters in a hybrid energy storage system (HESS) based on extended Kalman filter (EKF) with multiple corrections, where the measured currents on the battery side and the supercapacitor side are used to correct the observed currents obtained by EKF until the residuals between the observed values and the measured values are less than the set correction thresholds, thus avoiding the influence of the parameter variations. The open-switch fault detection is achieved by judging whether the correction times of the currents on the battery side and the supercapacitor side exceed the maximum correction times. The open-switch fault location is achieved through judging whether the corrected value on the fault side exceeds the set correction threshold. The proposed method is validated through simulation and experimental studies. Both the results show the robustness of fault diagnosis for bidirectional DC/DC converter.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 9","pages":"4363-4374"},"PeriodicalIF":5.2,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-12DOI: 10.1109/TCSI.2024.3426982
Yuhao Zhou;Biao Luo;Xin Wang;Xiaodong Xu;Lin Xiao
This article investigates a leader-following bipartite consensus issue for uncertain nonlinear heterogeneous multiagent systems (MASs). Initially, within the framework of optimal control theory, we employ the reinforcement learning (RL) algorithm to derive an approximate solution to the Hamilton-Jacobi-Bellman equation (HJBE). Specifically, the neural networks (NNs) are utilized to construct the Actor-Critic structure with the aim of implementing control behavior and evaluating system performance, respectively. An additional network is employed to address nonlinear uncertainties existing in the system. Furthermore, we design a static threshold event-triggered mechanism (ETM) to achieve the event-triggered state feedback-based control strategy. By utilizing this event-triggered state information, we reconstruct the approximate optimal controller and update laws of neural network weights, effectively reducing the communication burden while ensuring that all signals of the MASs remain bounded. Finally, two simulation examples are carried out to demonstrate the feasibility of the proposed method.
本文研究了不确定的非线性异构多代理系统（MAS）的领导者-跟随者两方共识问题。首先，在最优控制理论的框架内，我们采用强化学习（RL）算法推导出汉密尔顿-雅各比-贝尔曼方程（HJBE）的近似解。具体来说，我们利用神经网络（NN）来构建 "行动者-批判者 "结构，目的分别是实施控制行为和评估系统性能。我们还采用了一个额外的网络来解决系统中存在的非线性不确定性。此外，我们还设计了一种静态阈值事件触发机制（ETM），以实现基于事件触发状态反馈的控制策略。通过利用这些事件触发状态信息，我们重建了近似最优控制器和神经网络权重更新规律，在确保 MAS 所有信号保持有界的同时，有效减轻了通信负担。最后，我们通过两个仿真实例证明了所提方法的可行性。
{"title":"RL-Based Adaptive Optimal Bipartite Consensus Control for Nonlinear Heterogeneous MASs via Event-Triggered State Feedback","authors":"Yuhao Zhou;Biao Luo;Xin Wang;Xiaodong Xu;Lin Xiao","doi":"10.1109/TCSI.2024.3426982","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3426982","url":null,"abstract":"This article investigates a leader-following bipartite consensus issue for uncertain nonlinear heterogeneous multiagent systems (MASs). Initially, within the framework of optimal control theory, we employ the reinforcement learning (RL) algorithm to derive an approximate solution to the Hamilton-Jacobi-Bellman equation (HJBE). Specifically, the neural networks (NNs) are utilized to construct the Actor-Critic structure with the aim of implementing control behavior and evaluating system performance, respectively. An additional network is employed to address nonlinear uncertainties existing in the system. Furthermore, we design a static threshold event-triggered mechanism (ETM) to achieve the event-triggered state feedback-based control strategy. By utilizing this event-triggered state information, we reconstruct the approximate optimal controller and update laws of neural network weights, effectively reducing the communication burden while ensuring that all signals of the MASs remain bounded. Finally, two simulation examples are carried out to demonstrate the feasibility of the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 9","pages":"4261-4273"},"PeriodicalIF":5.2,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-12DOI: 10.1109/TCSI.2024.3439338
Yuxing Chen;Zhongfeng Wang
The IEEE 1901 standard plays a crucial role in the extensive fields of smart grids, electric vehicles, and the Internet of Things. The forward error correction (FEC) codes specified in this standard include low-density parity-check convolutional codes (LDPC-CCs), Reed-Solomon (RS) codes, and RS convolutional concatenated (RSCC) codes. This work proposes a low-complexity decoder fully compliant with the standard. First, a heterogeneous scheme is introduced to LDPC-CC decoding. The new scheme assigns different data formats among processing elements (PEs), which reduces the overall storage size and enables a customized datapath down to the PE level. Then, to efficiently support diverse FEC demands in the standard, a reconfigurable architecture is thoroughly explored from both memory and datapath aspects. Leveraging these techniques, the first decoder compatible with the IEEE 1901 standard is developed and implemented with 55nm technology. Implementation results demonstrate that the proposed decoder satisfies the standard’s requirements while exhibiting low hardware complexity.
{"title":"A Heterogeneous and Reconfigurable Decoder for the IEEE 1901 Standard","authors":"Yuxing Chen;Zhongfeng Wang","doi":"10.1109/TCSI.2024.3439338","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3439338","url":null,"abstract":"The IEEE 1901 standard plays a crucial role in the extensive fields of smart grids, electric vehicles, and the Internet of Things. The forward error correction (FEC) codes specified in this standard include low-density parity-check convolutional codes (LDPC-CCs), Reed-Solomon (RS) codes, and RS convolutional concatenated (RSCC) codes. This work proposes a low-complexity decoder fully compliant with the standard. First, a heterogeneous scheme is introduced to LDPC-CC decoding. The new scheme assigns different data formats among processing elements (PEs), which reduces the overall storage size and enables a customized datapath down to the PE level. Then, to efficiently support diverse FEC demands in the standard, a reconfigurable architecture is thoroughly explored from both memory and datapath aspects. Leveraging these techniques, the first decoder compatible with the IEEE 1901 standard is developed and implemented with 55nm technology. Implementation results demonstrate that the proposed decoder satisfies the standard’s requirements while exhibiting low hardware complexity.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4767-4777"},"PeriodicalIF":5.2,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter (ADC)-based high-speed wireline receivers. The proposed technique breaks the loop-unrolled DFE (LU-DFE) chain by computing multiple LU-DFE chains in parallel with all possible seed symbols, and selecting the appropriate output by the post-processing selection logic. The proposed loop-break DFE (LB-DFE) is functionally equivalent to the conventional DFE with any other implementation techniques such as LU-DFE, look-ahead DFE (LA-DFE), or direct DFE. With topographical synthesis in 28nm CMOS process, the proposed LB-DFE achieved up to 54% of DFE area saving as compared to LA-DFE with look-ahead factor (LF) of 16 for 112Gb/s PAM-4 with 875MHz DSP clock speed. The implementation feasibility and functionality are verified using ZCU111 RFSoC platform at 6Gb/s (3GS/s ADC conversion rate) with a channel exhibiting 25dB loss at 1.5GHz, demonstrating the same bit error rate (BER) performance between the LB-DFE and the LA-DFE. Equipment-based measurements using arbitrary waveform generator (AWG) and real-time oscilloscope transmitting/receiving 40GBaud PAM-4 (80Gb/s) to/from the differential cables with software 21-tap feed-forward equalizer (FFE) and LB-DFE on PC was also conducted.
{"title":"A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers","authors":"Donggeon Kim;Yujin Choi;Jaewon Lee;Seoyoung Jang;Sungyu Song;Matthias Braendli;Thomas Morf;Marcel Kossel;Pier-Andrea Francese;Gain Kim","doi":"10.1109/TCSI.2024.3435696","DOIUrl":"10.1109/TCSI.2024.3435696","url":null,"abstract":"This paper presents a novel digital decision feedback equalizer (DFE) design that can relax the feedback timing constraints for analog-to-digital converter (ADC)-based high-speed wireline receivers. The proposed technique breaks the loop-unrolled DFE (LU-DFE) chain by computing multiple LU-DFE chains in parallel with all possible seed symbols, and selecting the appropriate output by the post-processing selection logic. The proposed loop-break DFE (LB-DFE) is functionally equivalent to the conventional DFE with any other implementation techniques such as LU-DFE, look-ahead DFE (LA-DFE), or direct DFE. With topographical synthesis in 28nm CMOS process, the proposed LB-DFE achieved up to 54% of DFE area saving as compared to LA-DFE with look-ahead factor (LF) of 16 for 112Gb/s PAM-4 with 875MHz DSP clock speed. The implementation feasibility and functionality are verified using ZCU111 RFSoC platform at 6Gb/s (3GS/s ADC conversion rate) with a channel exhibiting 25dB loss at 1.5GHz, demonstrating the same bit error rate (BER) performance between the LB-DFE and the LA-DFE. Equipment-based measurements using arbitrary waveform generator (AWG) and real-time oscilloscope transmitting/receiving 40GBaud PAM-4 (80Gb/s) to/from the differential cables with software 21-tap feed-forward equalizer (FFE) and LB-DFE on PC was also conducted.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5115-5128"},"PeriodicalIF":5.2,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/tcsi.2024.3420250
Fanfan Meng, Siang-Yun Lee, Odysseas Zografos, Mohit Gupta, Van D. Nguyen, Giovanni De Micheli, Sorin Cotofana, Inge Asselberghs, Christoph Adelmann, Gouri Sankar Kar, Sebastien Couet, Florin Ciubotaru
{"title":"Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers","authors":"Fanfan Meng, Siang-Yun Lee, Odysseas Zografos, Mohit Gupta, Van D. Nguyen, Giovanni De Micheli, Sorin Cotofana, Inge Asselberghs, Christoph Adelmann, Gouri Sankar Kar, Sebastien Couet, Florin Ciubotaru","doi":"10.1109/tcsi.2024.3420250","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3420250","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"61 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/TCSI.2024.3430114
Jiaxun Teng;Xinlei Liu;Zizhe Wang;Lei Qi;Min Zhang;Wei Zhao;Xin Li;Xiaofeng Sun
Due to differences of solar irradiance, ambient temperatures, or inconsistent degradation of photovoltaic (PV) modules, the unbalanced output power between cascaded H-bridge (CHB) legs will lead to the unbalanced or even distorted grid currents between three phases. This article proposes a novel CHB-based PV grid-tied system integrating centralized energy storage (CHB-PV/ES), which can realize power balanced operation by utilizing the centralized energy storage (ES) interconnecting the CHB three-phase sub-modules (SMs) by isolated DC/DC converter. In addition, the centralized ES group can facilitate the regulation between grid-tied power references and PV power generation, such as stabilizing the power injected into the grid by smoothing the PV power, as well as responding to changes in grid-tied power references. The configuration and security domain of PV and centralized ES SMs are critical factors for CHB-PV/ES, which are thoroughly analyzed in this article to ensure safe system operation. The simulation and experimental results validate the effectiveness of the proposed CHB-PV/ES scheme.
由于太阳辐照度、环境温度的差异或光伏（PV）组件退化的不一致性，级联 H 桥（CHB）支路间不平衡的输出功率将导致三相间不平衡甚至畸变的电网电流。本文提出了一种新型基于 CHB 的光伏并网系统，该系统集成了集中储能（CHB-PV/ES），通过隔离式 DC/DC 转换器将 CHB 三相子模块（SM）与集中储能（ES）互连，从而实现功率平衡运行。此外，集中式 ES 组可促进并网功率基准与光伏发电之间的调节，例如通过平滑光伏功率来稳定注入电网的功率，以及响应并网功率基准的变化。光伏和集中式 ES SM 的配置和安全域是 CHB-PV/ES 的关键因素，本文对此进行了深入分析，以确保系统安全运行。仿真和实验结果验证了所提出的 CHB-PV/ES 方案的有效性。
{"title":"A Novel CHB-Based Photovoltaic Grid-Tied System Integration of Centralized Energy Storage and Its Power Security Domain","authors":"Jiaxun Teng;Xinlei Liu;Zizhe Wang;Lei Qi;Min Zhang;Wei Zhao;Xin Li;Xiaofeng Sun","doi":"10.1109/TCSI.2024.3430114","DOIUrl":"10.1109/TCSI.2024.3430114","url":null,"abstract":"Due to differences of solar irradiance, ambient temperatures, or inconsistent degradation of photovoltaic (PV) modules, the unbalanced output power between cascaded H-bridge (CHB) legs will lead to the unbalanced or even distorted grid currents between three phases. This article proposes a novel CHB-based PV grid-tied system integrating centralized energy storage (CHB-PV/ES), which can realize power balanced operation by utilizing the centralized energy storage (ES) interconnecting the CHB three-phase sub-modules (SMs) by isolated DC/DC converter. In addition, the centralized ES group can facilitate the regulation between grid-tied power references and PV power generation, such as stabilizing the power injected into the grid by smoothing the PV power, as well as responding to changes in grid-tied power references. The configuration and security domain of PV and centralized ES SMs are critical factors for CHB-PV/ES, which are thoroughly analyzed in this article to ensure safe system operation. The simulation and experimental results validate the effectiveness of the proposed CHB-PV/ES scheme.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4837-4850"},"PeriodicalIF":5.2,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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