Fault attacks are effective side-channel attack methods for cryptanalysis. However, existing fault attack methods involve manual derivation of complex fault models or computation-intensive statistical analysis of mass faulty ciphertexts to recover the key. In addition, most methods are only applicable to a specific cryptographic algorithm with strict requirements on the type and quantity of faults injected, lacking scalability and generality. Taking inspiration from machine learning and formal verification, we propose an automated fault attack framework, which supports multi-byte fault attacks on both SPN and generalized Feistel structure ciphers. This framework automates the generation of formal fault propagation models, extraction of fault properties, and formal fault analysis. We construct formal fault propagation models for cipher designs to measure the fault propagation precisely, eliminating the requirement of manually deriving fault propagation models. We mine accurate invariable behaviors in fault propagation effects as fault properties using a small number of fault traces and further utilize property constraints to retrieve the key through formal analysis. This method implements a formal fault attack on SM4 in 25th to 28th rounds for the first time. Experimental results on AES, RSM, LED and SM4 demonstrate the effectiveness of our method, with key search complexity lower than or equal to state-of-the-art methods, while requiring only four faulty ciphertexts to recover a round key.
{"title":"An Automated Fault Attack Framework for Block Ciphers Through Property Mining and Verification","authors":"Xingxin Wang;Wei Hu;Shibo Tang;Xinxin Wang;Huisi Zhou","doi":"10.1109/TCSI.2024.3456787","DOIUrl":"10.1109/TCSI.2024.3456787","url":null,"abstract":"Fault attacks are effective side-channel attack methods for cryptanalysis. However, existing fault attack methods involve manual derivation of complex fault models or computation-intensive statistical analysis of mass faulty ciphertexts to recover the key. In addition, most methods are only applicable to a specific cryptographic algorithm with strict requirements on the type and quantity of faults injected, lacking scalability and generality. Taking inspiration from machine learning and formal verification, we propose an automated fault attack framework, which supports multi-byte fault attacks on both SPN and generalized Feistel structure ciphers. This framework automates the generation of formal fault propagation models, extraction of fault properties, and formal fault analysis. We construct formal fault propagation models for cipher designs to measure the fault propagation precisely, eliminating the requirement of manually deriving fault propagation models. We mine accurate invariable behaviors in fault propagation effects as fault properties using a small number of fault traces and further utilize property constraints to retrieve the key through formal analysis. This method implements a formal fault attack on SM4 in 25th to 28th rounds for the first time. Experimental results on AES, RSM, LED and SM4 demonstrate the effectiveness of our method, with key search complexity lower than or equal to state-of-the-art methods, while requiring only four faulty ciphertexts to recover a round key.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"337-350"},"PeriodicalIF":5.2,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/TCSI.2024.3456237
Guoxiao Cheng;Jin-Dong Zhang;Qiaoyu Chen;Wen Wu
A wideband active single-sideband time modulator (STM) is proposed in this paper, which achieves high-resolution frequency-independent phase shifting performance through high-precision time delay, eliminating the need for calibrations. The analysis starts with N-step time modulation sequences for the active STM, followed by discussions on enhancing the sideband suppression ratio (SSR) and the effects of quadrature mismatch on SSR. The proposed active STM is based on a periodically controlled active vector modulator with regularly scalable gate-widths, and its timing sequences for control bits feature identical duty cycles and modulation frequency ( $f_{mathrm {P}}$ ). For verification, a wideband active STM is implemented using 0.13- $mu $ m CMOS technology, which is composed of an input balun and quadrature generator, a periodically controlled 4-bit active vector modulator and a variable-gain stage. Measurement results indicate root mean square (RMS) phase and gain errors ranging from 0.1 to 0.4° and less than 0.2 dB respectively, within a 3-dB frequency range of 13.0 to 20.6 GHz at the maximum gain state. The active STM provides a peak gain of −0.1 dB, an equivalent 10-bit phase control across a 360° range, and a 3-bit gain control spanning 21.0 dB. The measured SSR is below −23.3 dBc, and the instantaneous bandwidth is expanded to $16f_{mathrm {P}}$ . Additionally, the input 1-dB compression point (IP $_{mathrm {1dB}}$ ) ranges from 6.1 to 9.3 dBm. The chip occupies a 2.4 mm2 area and consumes 58.8 mW from a 1.2 V supply voltage.
{"title":"Analysis and Design of Wideband Active Single-Sideband Time Modulator in 0.13- μm CMOS","authors":"Guoxiao Cheng;Jin-Dong Zhang;Qiaoyu Chen;Wen Wu","doi":"10.1109/TCSI.2024.3456237","DOIUrl":"10.1109/TCSI.2024.3456237","url":null,"abstract":"A wideband active single-sideband time modulator (STM) is proposed in this paper, which achieves high-resolution frequency-independent phase shifting performance through high-precision time delay, eliminating the need for calibrations. The analysis starts with N-step time modulation sequences for the active STM, followed by discussions on enhancing the sideband suppression ratio (SSR) and the effects of quadrature mismatch on SSR. The proposed active STM is based on a periodically controlled active vector modulator with regularly scalable gate-widths, and its timing sequences for control bits feature identical duty cycles and modulation frequency (\u0000<inline-formula> <tex-math>$f_{mathrm {P}}$ </tex-math></inline-formula>\u0000). For verification, a wideband active STM is implemented using 0.13-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m CMOS technology, which is composed of an input balun and quadrature generator, a periodically controlled 4-bit active vector modulator and a variable-gain stage. Measurement results indicate root mean square (RMS) phase and gain errors ranging from 0.1 to 0.4° and less than 0.2 dB respectively, within a 3-dB frequency range of 13.0 to 20.6 GHz at the maximum gain state. The active STM provides a peak gain of −0.1 dB, an equivalent 10-bit phase control across a 360° range, and a 3-bit gain control spanning 21.0 dB. The measured SSR is below −23.3 dBc, and the instantaneous bandwidth is expanded to \u0000<inline-formula> <tex-math>$16f_{mathrm {P}}$ </tex-math></inline-formula>\u0000. Additionally, the input 1-dB compression point (IP\u0000<inline-formula> <tex-math>$_{mathrm {1dB}}$ </tex-math></inline-formula>\u0000) ranges from 6.1 to 9.3 dBm. The chip occupies a 2.4 mm2 area and consumes 58.8 mW from a 1.2 V supply voltage.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"85-98"},"PeriodicalIF":5.2,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/TCSI.2024.3457628
Yang Xu;Huihong Shi;Zhongfeng Wang
The significant computational cost of multiplications hinders the deployment of deep neural networks (DNNs) on edge devices. While multiplication-free models offer enhanced hardware efficiency, they typically sacrifice accuracy. As a solution, multiplication-reduced hybrid models have emerged to combine the benefits of both approaches. Particularly, prior works, i.e., NASA and NASA-F, leverage Neural Architecture Search (NAS) to construct such hybrid models, enhancing hardware efficiency while maintaining accuracy. However, they either entail costly retraining or encounter gradient conflicts, limiting both search efficiency and accuracy. Additionally, they overlook the acceleration opportunity introduced by accelerator search, yielding sub-optimal hardware performance. To overcome these limitations, we propose NASH, a Neural architecture and Accelerator Search framework for multiplication-reduced Hybrid models. Specifically, as for NAS, we propose a tailored zero-shot metric to pre-identify promising hybrid models before training, enhancing search efficiency while alleviating gradient conflicts. Regarding accelerator search, we innovatively introduce coarse-to-fine search to streamline the search process. Furthermore, we seamlessly integrate these two levels of searches to unveil NASH, obtaining optimal model and accelerator pairing. Experiments validate our effectiveness, e.g., when compared with the state-of-the-art multiplication-based system, we can achieve $uparrow 2.14times $ throughput and $uparrow 2.01times $ FPS with $uparrow 0.25%$ accuracy on CIFAR-100, and $uparrow 1.40times $ throughput and $uparrow 1.19times $ FPS with $uparrow 0.56%$ accuracy on Tiny-ImageNet. Codes are available at https://github.com/xuyang527/NASH .
乘法运算的巨大计算成本阻碍了深度神经网络（DNN）在边缘设备上的部署。虽然无乘法模型提高了硬件效率，但通常会牺牲精度。作为一种解决方案，乘法还原混合模型应运而生，它结合了两种方法的优点。特别是之前的工作，即 NASA 和 NASA-F，利用神经架构搜索（NAS）来构建这种混合模型，在保持准确性的同时提高了硬件效率。然而，它们要么需要昂贵的重新训练，要么会遇到梯度冲突，从而限制了搜索效率和准确性。此外，它们还忽视了加速器搜索带来的加速机会，导致硬件性能达不到最优。为了克服这些局限性，我们提出了 NASH，一个用于乘法还原混合模型的神经架构和加速器搜索框架。具体来说，与 NAS 一样，我们提出了一种量身定制的 "0-shot "度量方法，用于在训练前预先识别有前途的混合模型，从而在提高搜索效率的同时缓解梯度冲突。在加速器搜索方面，我们创新性地引入了从粗到细的搜索，以简化搜索过程。此外，我们还无缝整合了这两个层次的搜索，以揭开 NASH 的面纱，获得最佳模型和加速器配对。实验验证了我们的有效性，例如，与最先进的基于乘法的系统相比，我们可以在CIFAR-100上实现$uparrow 2.14倍的吞吐量和$uparrow 2.01倍的FPS，精度为$uparrow 0.25%$；在Tiny-ImageNet上实现$uparrow 1.40倍的吞吐量和$uparrow 1.19倍的FPS，精度为$uparrow 0.56%$。代码见 https://github.com/xuyang527/NASH。
{"title":"NASH: Neural Architecture and Accelerator Search for Multiplication-Reduced Hybrid Models","authors":"Yang Xu;Huihong Shi;Zhongfeng Wang","doi":"10.1109/TCSI.2024.3457628","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3457628","url":null,"abstract":"The significant computational cost of multiplications hinders the deployment of deep neural networks (DNNs) on edge devices. While multiplication-free models offer enhanced hardware efficiency, they typically sacrifice accuracy. As a solution, multiplication-reduced hybrid models have emerged to combine the benefits of both approaches. Particularly, prior works, i.e., NASA and NASA-F, leverage Neural Architecture Search (NAS) to construct such hybrid models, enhancing hardware efficiency while maintaining accuracy. However, they either entail costly retraining or encounter gradient conflicts, limiting both search efficiency and accuracy. Additionally, they overlook the acceleration opportunity introduced by accelerator search, yielding sub-optimal hardware performance. To overcome these limitations, we propose NASH, a Neural architecture and Accelerator Search framework for multiplication-reduced Hybrid models. Specifically, as for NAS, we propose a tailored zero-shot metric to pre-identify promising hybrid models before training, enhancing search efficiency while alleviating gradient conflicts. Regarding accelerator search, we innovatively introduce coarse-to-fine search to streamline the search process. Furthermore, we seamlessly integrate these two levels of searches to unveil NASH, obtaining optimal model and accelerator pairing. Experiments validate our effectiveness, e.g., when compared with the state-of-the-art multiplication-based system, we can achieve \u0000<inline-formula> <tex-math>$uparrow 2.14times $ </tex-math></inline-formula>\u0000 throughput and \u0000<inline-formula> <tex-math>$uparrow 2.01times $ </tex-math></inline-formula>\u0000 FPS with \u0000<inline-formula> <tex-math>$uparrow 0.25%$ </tex-math></inline-formula>\u0000 accuracy on CIFAR-100, and \u0000<inline-formula> <tex-math>$uparrow 1.40times $ </tex-math></inline-formula>\u0000 throughput and \u0000<inline-formula> <tex-math>$uparrow 1.19times $ </tex-math></inline-formula>\u0000 FPS with \u0000<inline-formula> <tex-math>$uparrow 0.56%$ </tex-math></inline-formula>\u0000 accuracy on Tiny-ImageNet. Codes are available at \u0000<uri>https://github.com/xuyang527/NASH</uri>\u0000.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5956-5968"},"PeriodicalIF":5.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The static architecture of artificial neural networks has fixed synaptic weights, whose connections do not change according to new information or learning experience. In contrast, the capacity of synaptic weight empowers biological neural networks to learn and adapt to diverse tasks, resulting in various dynamical behaviors. In this paper, a novel memristor model is designed into the Hopfield neural network for generating any desired number of multi-scroll attractors. Offset booster provides a channel for distance regulation and number control of coexisting attractors. Independent offset boosters determine the coexisting patterns including the types of one-scroll attractor, two-scroll attractor, four-scroll attractor, and other mixed types. In addition, the digital circuit platform of CH32V307 is applied to verify numerical simulations. Finally, the chaotic data generated in the memristive Hopfield neural network is introduced into the northern goshawk optimization (MHNN-NGO), by which the full network optimization is achieved.
{"title":"Offset Boosting-Oriented Construction of Multi-Scroll Attractor via a Memristor Model","authors":"Yongxin Li;Chunbiao Li;Sen Zhang;Yuanjin Zheng;Guanrong Chen","doi":"10.1109/TCSI.2024.3455350","DOIUrl":"10.1109/TCSI.2024.3455350","url":null,"abstract":"The static architecture of artificial neural networks has fixed synaptic weights, whose connections do not change according to new information or learning experience. In contrast, the capacity of synaptic weight empowers biological neural networks to learn and adapt to diverse tasks, resulting in various dynamical behaviors. In this paper, a novel memristor model is designed into the Hopfield neural network for generating any desired number of multi-scroll attractors. Offset booster provides a channel for distance regulation and number control of coexisting attractors. Independent offset boosters determine the coexisting patterns including the types of one-scroll attractor, two-scroll attractor, four-scroll attractor, and other mixed types. In addition, the digital circuit platform of CH32V307 is applied to verify numerical simulations. Finally, the chaotic data generated in the memristive Hopfield neural network is introduced into the northern goshawk optimization (MHNN-NGO), by which the full network optimization is achieved.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"918-931"},"PeriodicalIF":5.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/TCSI.2024.3454774
Yo-Sheng Lin;Chung-Ta Huang
We demonstrate the design and analysis of a K-band (18-27 GHz) divide-by-4 injection-locked frequency-divider (ILFD4) in 90 nm CMOS. A wideband balun is used for converting the single-ended injection signal to differential signals. The balun attains 9 dB gain boosting due to the LC-series-peaking at its differential outputs. Instead of the common topology of the body connected to the source, the injection transistors adopt the topology of the body connected to the gate through a large body floating resistance RB of 2.2 k$Omega $ , i.e., DTMOS-with-RB topology, to enhance their output signals. This leads to 11 dBm (from −29 to −40 dBm) input sensitivity enhancement of the ILFD4 (with output buffers). Divide-by-4 with 8-phase fundamental frequency (f0) output is achieved using the technique of dual linear mixer, i.e., dual linear divide-by-2. The first linear divide-by-2 with differential-quadrature (I/Q) 4-phase 2f0 outputs is performed by the direct-injection of ±4f0 signals to the differential injection transistors (to mix with their fundamental frequency signal at 2f0). The second linear divide-by-2 with 8-phase f0 outputs is carried out by the tail-injection of differential I/Q 4-phase 2f0 signals to the cross-connected four-stage differential ring oscillator (to mix with their fundamental frequency signal at f0). Due to the inherent divide-by-4 feature of the dual linear mixer topology, strong 8-phase divide-by-4 outputs are obtained. In addition to the first-stage FD of a K-band phase-locked loop, the circuit can also be used to provide the required differential-I/Q LO signals (for I/Q modulation and demodulation) of a 28 GHz 5G phased-array transceiver. The ILFD4 consumes 7.2 mW (at VDD of 1 V) and achieves input sensitivity of −40 dBm, locking range (LR) of 52.1% (12.2-20.8 GHz), and the first and second figure-of-merits of 7.24 mW−1 and 3.31, respectively, one of the best results ever reported for CMOS ILFD4s with similar operation frequency. For VDD of 1-1.5 V, a wide LR of 67.4% (12.2-24.6 GHz) is attained. The ILFD4 core only occupies a small chip area of 0.037 mm2.
{"title":"Design and Analysis of Divide-by-4 Injection-Locked Frequency Divider Using Gain-Boosting Injection Balun and Dual Linear Mixer Techniques","authors":"Yo-Sheng Lin;Chung-Ta Huang","doi":"10.1109/TCSI.2024.3454774","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3454774","url":null,"abstract":"We demonstrate the design and analysis of a K-band (18-27 GHz) divide-by-4 injection-locked frequency-divider (ILFD4) in 90 nm CMOS. A wideband balun is used for converting the single-ended injection signal to differential signals. The balun attains 9 dB gain boosting due to the LC-series-peaking at its differential outputs. Instead of the common topology of the body connected to the source, the injection transistors adopt the topology of the body connected to the gate through a large body floating resistance RB of 2.2 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>, i.e., DTMOS-with-RB topology, to enhance their output signals. This leads to 11 dBm (from −29 to −40 dBm) input sensitivity enhancement of the ILFD4 (with output buffers). Divide-by-4 with 8-phase fundamental frequency (f0) output is achieved using the technique of dual linear mixer, i.e., dual linear divide-by-2. The first linear divide-by-2 with differential-quadrature (I/Q) 4-phase 2f0 outputs is performed by the direct-injection of ±4f0 signals to the differential injection transistors (to mix with their fundamental frequency signal at 2f0). The second linear divide-by-2 with 8-phase f0 outputs is carried out by the tail-injection of differential I/Q 4-phase 2f0 signals to the cross-connected four-stage differential ring oscillator (to mix with their fundamental frequency signal at f0). Due to the inherent divide-by-4 feature of the dual linear mixer topology, strong 8-phase divide-by-4 outputs are obtained. In addition to the first-stage FD of a K-band phase-locked loop, the circuit can also be used to provide the required differential-I/Q LO signals (for I/Q modulation and demodulation) of a 28 GHz 5G phased-array transceiver. The ILFD4 consumes 7.2 mW (at VDD of 1 V) and achieves input sensitivity of −40 dBm, locking range (LR) of 52.1% (12.2-20.8 GHz), and the first and second figure-of-merits of 7.24 mW−1 and 3.31, respectively, one of the best results ever reported for CMOS ILFD4s with similar operation frequency. For VDD of 1-1.5 V, a wide LR of 67.4% (12.2-24.6 GHz) is attained. The ILFD4 core only occupies a small chip area of 0.037 mm2.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"763-775"},"PeriodicalIF":5.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The low-density parity-check code (LDPC) has been widely used to significantly enhance the reliability of 3-D NAND flash memory. However, in cases where the raw bit error rate (RBER) of the data is high, it not only demands more sense levels but also requires a large number of iterations, leading to a notable read latency issue. To mitigate this challenge, this paper introduces an innovative lightweight latency decrease (LLD) scheme. Initially, by examining the correlation between the number of iterations and the hard decision level (HDL), a functional model that encapsulates the relationship between iteration and offset is established. Building upon this model, the all-wordlines latency decrease (AWLD) scheme is proposed. In an effort to further decrease latency, an in-depth analysis of the similarities among different wordlines within a flash memory block is conducted, leading to the development of an optimized one-wordline lightweight latency decrease (OWLLD) scheme. For scenarios involving random reading of small data volumes, the interplay between function models of various overlapping regions is delved into, which ultimately results in the proposal of a further optimized one-page lightweight latency decrease (OPLLD) scheme. Experimental findings reveal that the OPLLD scheme can enhance the iterative performance of LDPC by up to 94.63% and reduce latency by up to 66.89% compared to traditional algorithms, while incurring minimal storage and computational overhead. This clearly indicates that the proposed scheme substantially enhances the read latency performance of LDPC in flash memory.
{"title":"LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory","authors":"Debao Wei;Yongchao Wang;Hua Feng;Huqi Xiang;Liyan Qiao","doi":"10.1109/TCSI.2024.3438789","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3438789","url":null,"abstract":"The low-density parity-check code (LDPC) has been widely used to significantly enhance the reliability of 3-D NAND flash memory. However, in cases where the raw bit error rate (RBER) of the data is high, it not only demands more sense levels but also requires a large number of iterations, leading to a notable read latency issue. To mitigate this challenge, this paper introduces an innovative lightweight latency decrease (LLD) scheme. Initially, by examining the correlation between the number of iterations and the hard decision level (HDL), a functional model that encapsulates the relationship between iteration and offset is established. Building upon this model, the all-wordlines latency decrease (AWLD) scheme is proposed. In an effort to further decrease latency, an in-depth analysis of the similarities among different wordlines within a flash memory block is conducted, leading to the development of an optimized one-wordline lightweight latency decrease (OWLLD) scheme. For scenarios involving random reading of small data volumes, the interplay between function models of various overlapping regions is delved into, which ultimately results in the proposal of a further optimized one-page lightweight latency decrease (OPLLD) scheme. Experimental findings reveal that the OPLLD scheme can enhance the iterative performance of LDPC by up to 94.63% and reduce latency by up to 66.89% compared to traditional algorithms, while incurring minimal storage and computational overhead. This clearly indicates that the proposed scheme substantially enhances the read latency performance of LDPC in flash memory.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4611-4623"},"PeriodicalIF":5.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142376906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/TCSI.2024.3454602
Fan Guo;Shashank Alevoor;Rakshit Dambe Nayak;John Pigott;Ryan Goodfellow;Bertan Bakkaloglu
Recently, digital ICs with high current slewing characteristics and tight supply voltage margin put increasing demand on the supply regulators. In this paper, an augmented DC-DC buck converter consisting of a lower-frequency main converter and a normally-off fast-switching secondary stage operating in parallel is proposed. The main-stage of the converter uses emulated-current-mode hysteretic control. For the auxiliary transient-suppression stage a nonlinear control scheme termed multiple-single-cycle nonlinear control (MSCNLC) is developed. The proposed augmented regulator improves the load transient response without compromising the overall efficiency of the converter, breaking the well-known efficiency vs. dynamic response trade-off. The high power-efficiency main-stage operating at $F_{sw}=500$ kHz provides the steady-state DC regulation voltage. The auxiliary-stage adopts a small inductor of 100nH and is only activated when load transient events are detected, providing fast load response, minimizing output voltage deviation. The load transient events are detected through an output capacitor charge tracking circuit, which effectively makes the auxiliary-stage a fast Current-Controlled-Current-Source during transient response. The buck converter is designed for $V_{IN} =3$ V-5.5V, $V_{OUT} =0.5$ V-1.1V and $I_{LOAD} =0.5$ A-8A. It is fabricated in $0.18~mu $ m BCD process. The measurement results show that with MSCNLC enabled, the undershoot and overshoot is reduced to 27mV and 58mV during the step-up and step-down response with 2.5A load step by a factor of close to 2, respectively. The recovery time is improved by ~1.7x.
{"title":"A Buck Converter Using Auxiliary-Stage With Multiple-Single-Cycle Non-Linear Control (MSCNLC) for Fast Load Transient Response","authors":"Fan Guo;Shashank Alevoor;Rakshit Dambe Nayak;John Pigott;Ryan Goodfellow;Bertan Bakkaloglu","doi":"10.1109/TCSI.2024.3454602","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3454602","url":null,"abstract":"Recently, digital ICs with high current slewing characteristics and tight supply voltage margin put increasing demand on the supply regulators. In this paper, an augmented DC-DC buck converter consisting of a lower-frequency main converter and a normally-off fast-switching secondary stage operating in parallel is proposed. The main-stage of the converter uses emulated-current-mode hysteretic control. For the auxiliary transient-suppression stage a nonlinear control scheme termed multiple-single-cycle nonlinear control (MSCNLC) is developed. The proposed augmented regulator improves the load transient response without compromising the overall efficiency of the converter, breaking the well-known efficiency vs. dynamic response trade-off. The high power-efficiency main-stage operating at \u0000<inline-formula> <tex-math>$F_{sw}=500$ </tex-math></inline-formula>\u0000 kHz provides the steady-state DC regulation voltage. The auxiliary-stage adopts a small inductor of 100nH and is only activated when load transient events are detected, providing fast load response, minimizing output voltage deviation. The load transient events are detected through an output capacitor charge tracking circuit, which effectively makes the auxiliary-stage a fast Current-Controlled-Current-Source during transient response. The buck converter is designed for \u0000<inline-formula> <tex-math>$V_{IN} =3$ </tex-math></inline-formula>\u0000 V-5.5V, \u0000<inline-formula> <tex-math>$V_{OUT} =0.5$ </tex-math></inline-formula>\u0000 V-1.1V and \u0000<inline-formula> <tex-math>$I_{LOAD} =0.5$ </tex-math></inline-formula>\u0000 A-8A. It is fabricated in \u0000<inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>\u0000 m BCD process. The measurement results show that with MSCNLC enabled, the undershoot and overshoot is reduced to 27mV and 58mV during the step-up and step-down response with 2.5A load step by a factor of close to 2, respectively. The recovery time is improved by ~1.7x.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"453-466"},"PeriodicalIF":5.2,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-13DOI: 10.1109/TCSI.2024.3454793
Xinchi Xu;Yonggang Wang;Yonghang Zhou;Zhengqi Song;Bo Wu;Xin Lin
A two-step time-to-digital converter (TDC) is designed for the high-precision time measurement of the DIRC-like TOF (DTOF) detector at the Super Tau-Charm Facility (STCF). Extending the measurement range by Nutt’s method, the TDC clock cycle is interpolated with two voltage-controlled tapped delay lines (TDL) connected by a dual-slope time amplifier (TA). By amplifying the residue from the first-step TDL-based interpolation with the TA and measuring it with the second TDL, the TDC resolution is significantly improved to sub-gate delay. Since the residue is extracted by a new method without the need of TA duplication or delay insertion, the TDC power consumption and conversion time are effectively reduced. By adopting the improved TA circuit into the TDC with a high gain, adjustable output offsets, and good linearity, the TDC measurement precision is guaranteed. In addition, a new DLL structure is proposed to stabilize the TDL against process, voltage, and temperature (PVT) variations with less power consumption. Benefiting from the proposed residue extraction method and DLL structure, the TDC exhibits low power consumption. To verify the TDC design, a prototype chip with two TDC channels is fabricated in GlobalFoundries (GF) 180 nm CMOS technology for performance evaluation. With a system clock of 150 MHz, it has a resolution (LSB) of 16.5 ps and a maximum sample rate of 6 MS/s. The differential nonlinearity (DNL) error ranges from −0.98 LSB to 0.87 LSB and the integral nonlinearity error (INL) ranges from −4.21 LSB to 2.83 LSB. With a bin-by-bin calibration method, the measured TDC precision is 12.1 ps on average within the 0–20 ns time interval measurement range. In addition, the TDC has low temperature sensitivity and does not require recalibration within a 20 ° C temperature range. Each TDC channel consumes $434~mu $ W power at 1 MS/s sample rate. The test results confirm that the proposed TDC can achieve high precision with a moderate sample rate and low power consumption without highly scaled technologies, which can meet the requirements of the DTOF detector at STCF.
{"title":"A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 μW at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier","authors":"Xinchi Xu;Yonggang Wang;Yonghang Zhou;Zhengqi Song;Bo Wu;Xin Lin","doi":"10.1109/TCSI.2024.3454793","DOIUrl":"10.1109/TCSI.2024.3454793","url":null,"abstract":"A two-step time-to-digital converter (TDC) is designed for the high-precision time measurement of the DIRC-like TOF (DTOF) detector at the Super Tau-Charm Facility (STCF). Extending the measurement range by Nutt’s method, the TDC clock cycle is interpolated with two voltage-controlled tapped delay lines (TDL) connected by a dual-slope time amplifier (TA). By amplifying the residue from the first-step TDL-based interpolation with the TA and measuring it with the second TDL, the TDC resolution is significantly improved to sub-gate delay. Since the residue is extracted by a new method without the need of TA duplication or delay insertion, the TDC power consumption and conversion time are effectively reduced. By adopting the improved TA circuit into the TDC with a high gain, adjustable output offsets, and good linearity, the TDC measurement precision is guaranteed. In addition, a new DLL structure is proposed to stabilize the TDL against process, voltage, and temperature (PVT) variations with less power consumption. Benefiting from the proposed residue extraction method and DLL structure, the TDC exhibits low power consumption. To verify the TDC design, a prototype chip with two TDC channels is fabricated in GlobalFoundries (GF) 180 nm CMOS technology for performance evaluation. With a system clock of 150 MHz, it has a resolution (LSB) of 16.5 ps and a maximum sample rate of 6 MS/s. The differential nonlinearity (DNL) error ranges from −0.98 LSB to 0.87 LSB and the integral nonlinearity error (INL) ranges from −4.21 LSB to 2.83 LSB. With a bin-by-bin calibration method, the measured TDC precision is 12.1 ps on average within the 0–20 ns time interval measurement range. In addition, the TDC has low temperature sensitivity and does not require recalibration within a 20 ° C temperature range. Each TDC channel consumes <inline-formula> <tex-math>$434~mu $ </tex-math></inline-formula>W power at 1 MS/s sample rate. The test results confirm that the proposed TDC can achieve high precision with a moderate sample rate and low power consumption without highly scaled technologies, which can meet the requirements of the DTOF detector at STCF.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"730-740"},"PeriodicalIF":5.2,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142254109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The visual SLAM (vSLAM) algorithm is becoming a research hotspot in recent years because of its low cost and low delay. Due to the advantage of fitting irregular data input, random sample consensus (RANSAC) has become a commonly used method in vSLAM to eliminate mismatched feature point pairs in adjacent frames. However, the huge number of iterations and computational complexity of the algorithm make the hardware implementation and integration of the entire system challenging. This paper pioneeringly proposes an efficient hardware acceleration design with homography matrix as RANSAC hypothesis model, which achieves high speed and high precision. Through optimizing the direct linear transformation (DLT) method, the delay and resource consumption are reduced. The design is implemented on FPGA. Through the verification of Xilinx Zynq 7100 platform, the processing frame rate on EuRoc dataset is 709 fps, reaching an average speed up of $263.2times $ against ARM CPU, and a speed up of $1.2sim 50.0times $ compared with the advanced implementations in RANSAC part, which fully meets the real-time requirements. In addition, the root-mean-square error (RMSE) based on an open-source SLAM system (ICE-BA) on the EuRoc dataset reached 0.105 m, achieving an improvement of 15.6% in precision compared to the original ICE-BA system.
{"title":"A Real-Time and High Precision Hardware Implementation of RANSAC Algorithm for Visual SLAM Achieving Mismatched Feature Point Pair Elimination","authors":"Wenzheng He;Zikuo Lu;Xin Liu;Ziwei Xu;Jingshuo Zhang;Chen Yang;Li Geng","doi":"10.1109/TCSI.2024.3422082","DOIUrl":"10.1109/TCSI.2024.3422082","url":null,"abstract":"The visual SLAM (vSLAM) algorithm is becoming a research hotspot in recent years because of its low cost and low delay. Due to the advantage of fitting irregular data input, random sample consensus (RANSAC) has become a commonly used method in vSLAM to eliminate mismatched feature point pairs in adjacent frames. However, the huge number of iterations and computational complexity of the algorithm make the hardware implementation and integration of the entire system challenging. This paper pioneeringly proposes an efficient hardware acceleration design with homography matrix as RANSAC hypothesis model, which achieves high speed and high precision. Through optimizing the direct linear transformation (DLT) method, the delay and resource consumption are reduced. The design is implemented on FPGA. Through the verification of Xilinx Zynq 7100 platform, the processing frame rate on EuRoc dataset is 709 fps, reaching an average speed up of \u0000<inline-formula> <tex-math>$263.2times $ </tex-math></inline-formula>\u0000 against ARM CPU, and a speed up of \u0000<inline-formula> <tex-math>$1.2sim 50.0times $ </tex-math></inline-formula>\u0000 compared with the advanced implementations in RANSAC part, which fully meets the real-time requirements. In addition, the root-mean-square error (RMSE) based on an open-source SLAM system (ICE-BA) on the EuRoc dataset reached 0.105 m, achieving an improvement of 15.6% in precision compared to the original ICE-BA system.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5102-5114"},"PeriodicalIF":5.2,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-10DOI: 10.1109/TCSI.2024.3453605
Fuhong Min;Sipeng Yin;Yizi Cheng
Nonlinear circuit can exhibit complex dynamical behaviors, especially the coexisting periodic or chaotic oscillations, by employing various electronic elements. However, oscillation circuits with a simple hybrid diode, which can induce richer dynamical behaviors with only a pair of anti-parallel diodes and an RC filter, are rarely reported, thus hindering the deep cognition and potential applications of such nonlinear circuits. This paper focuses on the dynamical behaviors of a Shinriki circuit modified by applying the hybrid diode, in which multiple coexisting oscillations and antimonotonic evolutions are successfully discovered by varying circuit parameters. To deeply study these phenomena, a discrete mapping structure of the proposed circuit is constructed by the semi-analytical method, and the bifurcation trees of diverse coexisting periodic oscillations are thoroughly investigated via bifurcation diagrams and phase portraits. The emergence and disappearance of antimonotonic phenomena with stable and unstable orbits are also clearly revealed. Notably, the stability and bifurcation points of the motions are precisely judged by eigenvalues, and the unstable routes hidden in chaotic regions can be uncovered. Finally, the coexisting stable and unstable periodic orbits are captured from the oscilloscope via a field programmable gate array (FPGA), which verifies the correctness of the analysis. The research may be devoted to the improvement of nonlinear circuit.
{"title":"Hybrid-Diode-Based Shinriki Circuit: Coexisting Oscillations and Bifurcation Trees","authors":"Fuhong Min;Sipeng Yin;Yizi Cheng","doi":"10.1109/TCSI.2024.3453605","DOIUrl":"10.1109/TCSI.2024.3453605","url":null,"abstract":"Nonlinear circuit can exhibit complex dynamical behaviors, especially the coexisting periodic or chaotic oscillations, by employing various electronic elements. However, oscillation circuits with a simple hybrid diode, which can induce richer dynamical behaviors with only a pair of anti-parallel diodes and an RC filter, are rarely reported, thus hindering the deep cognition and potential applications of such nonlinear circuits. This paper focuses on the dynamical behaviors of a Shinriki circuit modified by applying the hybrid diode, in which multiple coexisting oscillations and antimonotonic evolutions are successfully discovered by varying circuit parameters. To deeply study these phenomena, a discrete mapping structure of the proposed circuit is constructed by the semi-analytical method, and the bifurcation trees of diverse coexisting periodic oscillations are thoroughly investigated via bifurcation diagrams and phase portraits. The emergence and disappearance of antimonotonic phenomena with stable and unstable orbits are also clearly revealed. Notably, the stability and bifurcation points of the motions are precisely judged by eigenvalues, and the unstable routes hidden in chaotic regions can be uncovered. Finally, the coexisting stable and unstable periodic orbits are captured from the oscilloscope via a field programmable gate array (FPGA), which verifies the correctness of the analysis. The research may be devoted to the improvement of nonlinear circuit.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 2","pages":"896-906"},"PeriodicalIF":5.2,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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