In this paper, the dual spacecraft pursuit-evasion game problem under incomplete information is investigated, and a strategy-solving method for the incomplete information pursuit-evasion game based on particle swarm optimization and unscented particle filter (PSO-UPF) estimation is proposed. The completeness of the information available about the target’s cost function, which is determined by the weighting information, has a significant impact on the success of the pursuing strategy. For the cost function is unknown in incomplete information scenarios, a research framework of the pursuit-evasion game based on following observation and one-sided pursuit two stages is established. Besides, to describe the more accurate motion of the spacecraft, a Schweighart-Sedwick (SS) dynamic model is introduced that considers the effect of $J_{2}$ perturbation. Firstly, an equilibrium strategy for the SS model-based pursuit-evasion problem is derived under complete information. Next, for the incomplete information scenarios, an estimation method based on PSO-UPF of weight matrix information is established, which allows the cost function to be determined by the estimation method in the observation stage. Then, the pursuit strategy is re-designed in the one-sided pursuit stage based on the estimated cost function. Finally, the performance of the proposed method is validated by simulation. The results demonstrate that the approach can achieve good performance by efficiently estimating the weight information in the opponent’s cost function.
{"title":"Pursuit-Evasion Game for Spacecraft With Incomplete Information Under J₂ Perturbation","authors":"Zhenxin Mu;Mingjiang Ji;Pengyu Guo;Qufei Zhang;Bing Xiao;Lu Cao;Junzhi Yu","doi":"10.1109/TCSI.2025.3560303","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560303","url":null,"abstract":"In this paper, the dual spacecraft pursuit-evasion game problem under incomplete information is investigated, and a strategy-solving method for the incomplete information pursuit-evasion game based on particle swarm optimization and unscented particle filter (PSO-UPF) estimation is proposed. The completeness of the information available about the target’s cost function, which is determined by the weighting information, has a significant impact on the success of the pursuing strategy. For the cost function is unknown in incomplete information scenarios, a research framework of the pursuit-evasion game based on following observation and one-sided pursuit two stages is established. Besides, to describe the more accurate motion of the spacecraft, a Schweighart-Sedwick (SS) dynamic model is introduced that considers the effect of <inline-formula> <tex-math>$J_{2}$ </tex-math></inline-formula> perturbation. Firstly, an equilibrium strategy for the SS model-based pursuit-evasion problem is derived under complete information. Next, for the incomplete information scenarios, an estimation method based on PSO-UPF of weight matrix information is established, which allows the cost function to be determined by the estimation method in the observation stage. Then, the pursuit strategy is re-designed in the one-sided pursuit stage based on the estimated cost function. Finally, the performance of the proposed method is validated by simulation. The results demonstrate that the approach can achieve good performance by efficiently estimating the weight information in the opponent’s cost function.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4346-4358"},"PeriodicalIF":5.2,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TCSI.2025.3554635
Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu
FPGA accelerators for lightweight convolutional neural networks (LWCNNs) have recently attracted significant attention. Most existing LWCNN accelerators focus on single-Computing-Engine (CE) architecture with local optimization. However, these designs typically suffer from high on-chip/off-chip memory overhead and low computational efficiency due to their layer-by-layer dataflow and unified resource mapping mechanisms. To tackle these issues, a novel multi-CE-based accelerator with balanced dataflow is proposed to efficiently accelerate LWCNN through memory-oriented and computing-oriented optimizations. Firstly, a streaming architecture with hybrid CEs is designed to minimize off-chip memory access while maintaining a low cost of on-chip buffer size. Secondly, a balanced dataflow strategy is introduced for streaming architectures to enhance computational efficiency by improving efficient resource mapping and mitigating data congestion. Furthermore, a resource-aware memory and parallelism allocation methodology is proposed, based on a performance model, to achieve better performance and scalability. The proposed accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and ShuffleNetV2. Implementation results demonstrate that the proposed accelerator can save up to 68.3% of on-chip memory size with reduced off-chip memory access compared to the reference design. It achieves an impressive performance of up to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while maintaining a high DSP utilization of 95%, thus significantly outperforming current LWCNN accelerators.
{"title":"A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow","authors":"Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu","doi":"10.1109/TCSI.2025.3554635","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554635","url":null,"abstract":"FPGA accelerators for lightweight convolutional neural networks (LWCNNs) have recently attracted significant attention. Most existing LWCNN accelerators focus on single-Computing-Engine (CE) architecture with local optimization. However, these designs typically suffer from high on-chip/off-chip memory overhead and low computational efficiency due to their layer-by-layer dataflow and unified resource mapping mechanisms. To tackle these issues, a novel multi-CE-based accelerator with balanced dataflow is proposed to efficiently accelerate LWCNN through memory-oriented and computing-oriented optimizations. Firstly, a streaming architecture with hybrid CEs is designed to minimize off-chip memory access while maintaining a low cost of on-chip buffer size. Secondly, a balanced dataflow strategy is introduced for streaming architectures to enhance computational efficiency by improving efficient resource mapping and mitigating data congestion. Furthermore, a resource-aware memory and parallelism allocation methodology is proposed, based on a performance model, to achieve better performance and scalability. The proposed accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and ShuffleNetV2. Implementation results demonstrate that the proposed accelerator can save up to 68.3% of on-chip memory size with reduced off-chip memory access compared to the reference design. It achieves an impressive performance of up to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while maintaining a high DSP utilization of 95%, thus significantly outperforming current LWCNN accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3338-3351"},"PeriodicalIF":5.2,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TCSI.2025.3559711
Hapsah Aulia Azzahra;Muhammad Fakhri Mauludin;Xi Zhu;Jae-Won Nam;Jusung Kim
This paper presents a current-reused coupled oscillator with improved noise circulating technique for phase noise improvement. The proposed current-reused coupled oscillator with order of 2, where the noise circulation oscillator is stacked on top of PMOS cross-coupled oscillator solves the strict trade-off between power consumption and phase noise. The degeneration transistors for noise circulating operations are biased in triode-region instead of in saturation to provide an optimum delay in loop gain, such that the positive and negative phase change in the normalized impulse sensitivity function (ISF) become more symmetric. Thus, the $1/f^{3}$ phase noise is significantly improved. The voltage-controlled oscillator (VCO) was implemented using CMOS 65nm technology, and the measurement results demonstrated its operation within a frequency range of 15.4–17 GHz (9.8% tuning range). Despite its low power dissipation of 6.3 mW, the VCO design exhibits excellent performance, offering a phase noise of −111.2 dBc/Hz at 1 MHz offset frequency. Furthermore, the proposed VCO attains a figure of merit (FoM) of −187.4 dBc/Hz.
{"title":"15.4–17 GHz, −187.4 dBc/Hz FoM VCO With Current Reused Coupled Oscillator and Improved Noise Circulation","authors":"Hapsah Aulia Azzahra;Muhammad Fakhri Mauludin;Xi Zhu;Jae-Won Nam;Jusung Kim","doi":"10.1109/TCSI.2025.3559711","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559711","url":null,"abstract":"This paper presents a current-reused coupled oscillator with improved noise circulating technique for phase noise improvement. The proposed current-reused coupled oscillator with order of 2, where the noise circulation oscillator is stacked on top of PMOS cross-coupled oscillator solves the strict trade-off between power consumption and phase noise. The degeneration transistors for noise circulating operations are biased in triode-region instead of in saturation to provide an optimum delay in loop gain, such that the positive and negative phase change in the normalized impulse sensitivity function (ISF) become more symmetric. Thus, the <inline-formula> <tex-math>$1/f^{3}$ </tex-math></inline-formula> phase noise is significantly improved. The voltage-controlled oscillator (VCO) was implemented using CMOS 65nm technology, and the measurement results demonstrated its operation within a frequency range of 15.4–17 GHz (9.8% tuning range). Despite its low power dissipation of 6.3 mW, the VCO design exhibits excellent performance, offering a phase noise of −111.2 dBc/Hz at 1 MHz offset frequency. Furthermore, the proposed VCO attains a figure of merit (FoM) of −187.4 dBc/Hz.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 10","pages":"5325-5337"},"PeriodicalIF":5.2,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145315357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TCSI.2025.3559354
Shuai Liu;Yechen Tian;Congyang Sun;Guoyu Li;Hao Xu;Na Yan
This paper presents a design-oriented analysis for the time-interleaved SAR ADC that quantifies different sources of imperfections to provide a unified design framework. This includes both single-channel and interleaving imperfections. A prototype time-interleaved ADC is designed and fabricated in a 28 nm CMOS process to validate the effectiveness of the theory. With one-time foreground timing skew and offset compensation, the 3.5 GS/s 11-bit time-interleaved SAR ADC achieves 55.6 dB SNDR at low input frequency and 54.3 dB SNDR at Nyquist frequency while dissipating 66.0 mW at 1 V supply including 14.8 mW clock buffer power.
本文提出了一种针对时间交错SAR ADC的面向设计的分析方法，该方法量化了不同的缺陷来源，以提供统一的设计框架。这包括单通道和交错缺陷。为了验证该理论的有效性，在28nm CMOS工艺下设计并制作了一个时间交错ADC原型。通过一次性前景时序倾斜和偏移补偿，3.5 GS/s 11位时间交错SAR ADC在低输入频率下可实现55.6 dB SNDR，在奈奎斯特频率下可实现54.3 dB SNDR，而在1v电源下功耗为66.0 mW，其中时钟缓冲功率为14.8 mW。
{"title":"Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency","authors":"Shuai Liu;Yechen Tian;Congyang Sun;Guoyu Li;Hao Xu;Na Yan","doi":"10.1109/TCSI.2025.3559354","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559354","url":null,"abstract":"This paper presents a design-oriented analysis for the time-interleaved SAR ADC that quantifies different sources of imperfections to provide a unified design framework. This includes both single-channel and interleaving imperfections. A prototype time-interleaved ADC is designed and fabricated in a 28 nm CMOS process to validate the effectiveness of the theory. With one-time foreground timing skew and offset compensation, the 3.5 GS/s 11-bit time-interleaved SAR ADC achieves 55.6 dB SNDR at low input frequency and 54.3 dB SNDR at Nyquist frequency while dissipating 66.0 mW at 1 V supply including 14.8 mW clock buffer power.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2483-2496"},"PeriodicalIF":5.2,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-16DOI: 10.1109/TCSI.2025.3559419
Deepank Grover;Tarun Sharma;Sneha Agarwal;Sidhartha Sankar Rout;Anushka;Madhur Kumar;Sujay Deb
Modern Multi-Processor-Systems-on-Chips (MPSoCs) use Network-on-Chips (NoCs) as a scalable and efficient communication fabric. The applications running on these devices rely on frequent communication with central database servers, which are vulnerable to impersonation attacks by adversarial clones. We propose NoCiPUF, a novel NoC-based intrinsic Physically-Unclonable-Function (PUF) framework for MPSoCs authentication. We re-use the circuit switched nature of NoC with path-pairs as challenges to obtain secret responses, collectively called challenge-response-pairs (CRPs). Due to the random nature of manufacturing variations, equal hop paths exhibit unequal delays. We leverage the delay differences of flits traversing in equal-hop paths to generate unique responses. NoCiPUF is fully-synthesizable and readily scalable as it requires changes only at the behavioral level. To counter Machine-Learning (ML)-based modeling attacks on PUFs, we provide a comprehensive technique and reduce the prediction accuracy to ~52%. NoCiPUF framework incurs low area (0.76%) and power (1.14%) overheads and has no impact on NoC performance in normal mode due to independent authentication mode. Obtained responses have near-ideal PUF metrics and are verified against the NIST randomness test suite. This scheme offers high number of CRPs in larger NoC networks (>0.74 million CRPs in $5 times 5$ mesh), proving its scalability.
{"title":"NoCiPUF: NoC-Based Intrinsic PUF for MPSoC Authentication","authors":"Deepank Grover;Tarun Sharma;Sneha Agarwal;Sidhartha Sankar Rout;Anushka;Madhur Kumar;Sujay Deb","doi":"10.1109/TCSI.2025.3559419","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559419","url":null,"abstract":"Modern Multi-Processor-Systems-on-Chips (MPSoCs) use Network-on-Chips (NoCs) as a scalable and efficient communication fabric. The applications running on these devices rely on frequent communication with central database servers, which are vulnerable to impersonation attacks by adversarial clones. We propose NoCiPUF, a novel NoC-based intrinsic Physically-Unclonable-Function (PUF) framework for MPSoCs authentication. We re-use the circuit switched nature of NoC with path-pairs as challenges to obtain secret responses, collectively called challenge-response-pairs (CRPs). Due to the random nature of manufacturing variations, equal hop paths exhibit unequal delays. We leverage the delay differences of flits traversing in equal-hop paths to generate unique responses. NoCiPUF is fully-synthesizable and readily scalable as it requires changes only at the behavioral level. To counter Machine-Learning (ML)-based modeling attacks on PUFs, we provide a comprehensive technique and reduce the prediction accuracy to ~52%. NoCiPUF framework incurs low area (0.76%) and power (1.14%) overheads and has no impact on NoC performance in normal mode due to independent authentication mode. Obtained responses have near-ideal PUF metrics and are verified against the NIST randomness test suite. This scheme offers high number of CRPs in larger NoC networks (>0.74 million CRPs in <inline-formula> <tex-math>$5 times 5$ </tex-math></inline-formula> mesh), proving its scalability.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4167-4180"},"PeriodicalIF":5.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-16DOI: 10.1109/TCSI.2025.3559069
Yuanchen Wu;Zhiheng Xie;Hongbing Pan;Yuxuan Wang
The softmax function needs to be frequently used in the multi-head attention layer of Transformer networks. Compared to DNNs and other networks, Transformers have higher computational complexity, requiring higher accuracy and hardware performance for softmax function calculations. Therefore, we propose mixed-base softmax (MBS) for the first time for the approximation of the softmax function. This method combines exponential functions with bases of 2 and 4, which is advantageous for hardware implementation. MBS has a high similarity to the softmax function and demonstrates advanced performance during inference in Transformer network. Through algorithm transformation and hardware optimization, we have designed a low-complexity and highly parallel hardware architecture, which only occupies few additional hardware resources compared to base-2 softmax but achieves higher accuracy. Experimental results show that, under TSMC 90nm CMOS technology at the frequency of 0.5 GHz, our design can achieve the efficiency of 236.18 Gps/(mm${^{{2}}} cdot $ mW) with the area of $4234~mu $ m2. Furthermore, MBS exhibits higher computational accuracy and inference precision compared with base-2 softmax.
{"title":"MBS: A High-Precision Approximation Method for Softmax and Efficient Hardware Implementation","authors":"Yuanchen Wu;Zhiheng Xie;Hongbing Pan;Yuxuan Wang","doi":"10.1109/TCSI.2025.3559069","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559069","url":null,"abstract":"The softmax function needs to be frequently used in the multi-head attention layer of Transformer networks. Compared to DNNs and other networks, Transformers have higher computational complexity, requiring higher accuracy and hardware performance for softmax function calculations. Therefore, we propose mixed-base softmax (MBS) for the first time for the approximation of the softmax function. This method combines exponential functions with bases of 2 and 4, which is advantageous for hardware implementation. MBS has a high similarity to the softmax function and demonstrates advanced performance during inference in Transformer network. Through algorithm transformation and hardware optimization, we have designed a low-complexity and highly parallel hardware architecture, which only occupies few additional hardware resources compared to base-2 softmax but achieves higher accuracy. Experimental results show that, under TSMC 90nm CMOS technology at the frequency of 0.5 GHz, our design can achieve the efficiency of 236.18 Gps/(mm<inline-formula> <tex-math>${^{{2}}} cdot $ </tex-math></inline-formula>mW) with the area of <inline-formula> <tex-math>$4234~mu $ </tex-math></inline-formula>m2. Furthermore, MBS exhibits higher computational accuracy and inference precision compared with base-2 softmax.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3366-3375"},"PeriodicalIF":5.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-16DOI: 10.1109/TCSI.2025.3558826
Gewei Zuo;Lijun Zhu;Yujuan Wang;Zhiyong Chen;Yongduan Song
This paper investigates the prescribed-time cooperative output regulation (PTCOR) for a class of linear heterogeneous multi-agent systems (MASs) under directed communication graphs. As a special case of PTCOR, the necessary and sufficient condition for prescribed-time output regulation of an individual system is first explored, whereas only sufficient conditions are developed in the literature. A PTCOR algorithm is subsequently developed, composed of prescribed-time distributed observers, local state observers, and tracking controllers, utilizing a distributed feedforward method. This approach converts the PTCOR problem into the prescribed-time stabilization problem of a cascaded subsystem. The criterion for the prescribed-time stabilization of the cascaded system is proposed, differing from that of traditional asymptotic or finite-time stabilization of a cascaded system. It is proven that the regulated outputs converge to zero within a prescribed time and remain at zero afterward, while all internal signals in the closed-loop MASs are uniformly bounded. Finally, the theoretical results are validated through two numerical examples.
{"title":"A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria","authors":"Gewei Zuo;Lijun Zhu;Yujuan Wang;Zhiyong Chen;Yongduan Song","doi":"10.1109/TCSI.2025.3558826","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3558826","url":null,"abstract":"This paper investigates the prescribed-time cooperative output regulation (PTCOR) for a class of linear heterogeneous multi-agent systems (MASs) under directed communication graphs. As a special case of PTCOR, the necessary and sufficient condition for prescribed-time output regulation of an individual system is first explored, whereas only sufficient conditions are developed in the literature. A PTCOR algorithm is subsequently developed, composed of prescribed-time distributed observers, local state observers, and tracking controllers, utilizing a distributed feedforward method. This approach converts the PTCOR problem into the prescribed-time stabilization problem of a cascaded subsystem. The criterion for the prescribed-time stabilization of the cascaded system is proposed, differing from that of traditional asymptotic or finite-time stabilization of a cascaded system. It is proven that the regulated outputs converge to zero within a prescribed time and remain at zero afterward, while all internal signals in the closed-loop MASs are uniformly bounded. Finally, the theoretical results are validated through two numerical examples.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2842-2855"},"PeriodicalIF":5.2,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/TCSI.2025.3552602
Mehdi Golestani;Yongduan Song;Tao Liu;Xiang Xu;Guang-Ren Duan;He Kong
This paper proposes a low-complexity tracking control framework for uncertain nonlinear systems in strict feedback and normal forms, respectively. By leveraging a smooth scaling function, these control schemes ensure unified prescribed performance for the output tracking error of strict feedback nonlinear systems and the full-state tracking errors of normal form nonlinear systems. The notion of unified prescribed performance allows for different performance behaviors via performance functions, which can be either constant or time-varying with arbitrarily large initial values. The main contribution is achieving unified prescribed performance for full-state tracking errors without imposing feasibility conditions, a limitation of existing approaches. To eliminate these strict conditions, we introduce a uniform transformation independent of initial conditions. Additionally, the proposed control schemes are low-complexity since they do not require adaptive mechanisms or function approximation to deal with uncertainties and disturbances. The effectiveness of these frameworks is demonstrated through comparative analysis.
{"title":"A Novel Feasibility Condition-Free Approach for Achieving Desired Precision and Unified Performance Within Prescribed Time","authors":"Mehdi Golestani;Yongduan Song;Tao Liu;Xiang Xu;Guang-Ren Duan;He Kong","doi":"10.1109/TCSI.2025.3552602","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3552602","url":null,"abstract":"This paper proposes a low-complexity tracking control framework for uncertain nonlinear systems in strict feedback and normal forms, respectively. By leveraging a smooth scaling function, these control schemes ensure unified prescribed performance for the output tracking error of strict feedback nonlinear systems and the full-state tracking errors of normal form nonlinear systems. The notion of unified prescribed performance allows for different performance behaviors via performance functions, which can be either constant or time-varying with arbitrarily large initial values. The main contribution is achieving unified prescribed performance for full-state tracking errors without imposing feasibility conditions, a limitation of existing approaches. To eliminate these strict conditions, we introduce a uniform transformation independent of initial conditions. Additionally, the proposed control schemes are low-complexity since they do not require adaptive mechanisms or function approximation to deal with uncertainties and disturbances. The effectiveness of these frameworks is demonstrated through comparative analysis.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2856-2867"},"PeriodicalIF":5.2,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/TCSI.2025.3557837
Tanwei Yan;Junning Jiang;Jose Silva-Martinez
This paper proposes a fractional spur cancellation technique designed for fractional-N frequency synthesizers. A time domain quantitative analysis is conducted to provide an intuitive understanding of the origin of fractional spurs and to formulate the relationship between the phase error of the feedback signal and the division factor of the frequency divider. By utilizing a dual loop charge-pump based architecture that generates two feedback phases, one leading and one lagging the reference phase, the two loops effectively clamp the reference phase between the two feedback phases and inject complementary charge components to achieve spur reduction. Unlike conventional methods, the proposed analog spur cancellation technique eliminates the need for additional signal processing stages within the loop. This offers several advantages, including reduced complexity, no introduction of additional distortion sources, and minimal impact on loop dynamics. Simulation results employing TSMC 40nm technology demonstrate that the proposed technique can achieve a worst-case fractional spur level of -96.6dBc in a charge-pump based fractional-N frequency synthesizer, offering moderate immunity to mismatches while also slightly improving the phase acquisition time and jitter performance.
{"title":"A Fractional Spur Cancellation Technique for Fractional-N Frequency Synthesizers Enabled by Dual Loop Phase Clamping","authors":"Tanwei Yan;Junning Jiang;Jose Silva-Martinez","doi":"10.1109/TCSI.2025.3557837","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557837","url":null,"abstract":"This paper proposes a fractional spur cancellation technique designed for fractional-N frequency synthesizers. A time domain quantitative analysis is conducted to provide an intuitive understanding of the origin of fractional spurs and to formulate the relationship between the phase error of the feedback signal and the division factor of the frequency divider. By utilizing a dual loop charge-pump based architecture that generates two feedback phases, one leading and one lagging the reference phase, the two loops effectively clamp the reference phase between the two feedback phases and inject complementary charge components to achieve spur reduction. Unlike conventional methods, the proposed analog spur cancellation technique eliminates the need for additional signal processing stages within the loop. This offers several advantages, including reduced complexity, no introduction of additional distortion sources, and minimal impact on loop dynamics. Simulation results employing TSMC 40nm technology demonstrate that the proposed technique can achieve a worst-case fractional spur level of -96.6dBc in a charge-pump based fractional-N frequency synthesizer, offering moderate immunity to mismatches while also slightly improving the phase acquisition time and jitter performance.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"3791-3801"},"PeriodicalIF":5.2,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-14DOI: 10.1109/TCSI.2025.3557258
Xu Wang;Michael Peter Kennedy
The digital-to-time converter (DTC) used in fractional-N phase locked loops is designed to cancel the accumulated quantization error (QE) arising from the divider controller. In high-resolution synthesizers, the DTC performs an additional quantization when mapping the required high-resolution phase correction to its coarse-resolution output. This inherent hard quantization nonlinearity of the DTC, which is different from the DTC’s well-known soft integral nonlinearity, causes yet another kind of inexact cancellation of the QE and induces excess spurious tones that degrade the output phase noise and jitter. This paper reveals the root cause of the “DTC’s QE” and spectral manifestation of the DTC-quantization-induced (DQI) spurs. The waveform of the DTC’s QE is derived analytically; it shows that the DQI-spur pattern is (i) determined by the fractional frequency control word and the quantization resolution of the DTC, and (ii) is independent of the type, order, and modulus of the divider controller. In view of the fact that conventional DTC linearity enhancement techniques and stochastic divider controllers have no effect on DQI-spur mitigation, we propose a novel family of DTC-enhancement methods called input-dithered quantization (IDQ). When used in DTCs, the IDQ methods are effective in eliminating DQI spurs at source with negligible phase noise or jitter penalty.
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