Pub Date : 2024-08-20DOI: 10.1109/TCSI.2024.3443188
Niraj Kishore;Kapil Shukla;Nitin Gupta
This article presents a novel topology for a three-phase switched-capacitor (SC) based hybrid multilevel inverter (HMLI) with boosted output voltage. The proposed topology employs generalised structure of SC-based inverters (SCBIs) to improve the output voltage levels utilising SC cells. The proposed structure additionally features self-charging and voltage-balancing capabilities of the SCs, without the need of auxiliary circuit/sensor. A modified PWM (MPWM) technique is utilized to modulate the system. The MPWM results in improved output voltage profile and reduction in voltage ripple across the SCs. The proposed structure is quantitatively compared with the state-of-the-art topologies to demonstrate its advantages in the terms of reduced components count, low maximum blocking voltage (MBV), low total standing voltage (TSV), lessened total harmonic distortion (THD), lowered cost function (CF) per level, and boosted output voltage. The performance of the proposed topology is verified in MATLAB/Simulink environment and a laboratory prototype is developed to confirm the feasibility to operate at steady-state and dynamic conditions.
{"title":"Generalized Switched-Capacitor-Based Hybrid Multilevel Inverter With Reduced Components Count and Inrush Current","authors":"Niraj Kishore;Kapil Shukla;Nitin Gupta","doi":"10.1109/TCSI.2024.3443188","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3443188","url":null,"abstract":"This article presents a novel topology for a three-phase switched-capacitor (SC) based hybrid multilevel inverter (HMLI) with boosted output voltage. The proposed topology employs generalised structure of SC-based inverters (SCBIs) to improve the output voltage levels utilising SC cells. The proposed structure additionally features self-charging and voltage-balancing capabilities of the SCs, without the need of auxiliary circuit/sensor. A modified PWM (MPWM) technique is utilized to modulate the system. The MPWM results in improved output voltage profile and reduction in voltage ripple across the SCs. The proposed structure is quantitatively compared with the state-of-the-art topologies to demonstrate its advantages in the terms of reduced components count, low maximum blocking voltage (MBV), low total standing voltage (TSV), lessened total harmonic distortion (THD), lowered cost function (CF) per level, and boosted output voltage. The performance of the proposed topology is verified in MATLAB/Simulink environment and a laboratory prototype is developed to confirm the feasibility to operate at steady-state and dynamic conditions.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-19DOI: 10.1109/tcsi.2024.3407125
Jikai Chen, Xinhai Chang, Chuang Liu, Haoru Li
{"title":"An Online Monitoring Method for Capacitor Condition of Cascaded H-Bridge STATCOM Based on Sensorless Capacitor Voltage Detection","authors":"Jikai Chen, Xinhai Chang, Chuang Liu, Haoru Li","doi":"10.1109/tcsi.2024.3407125","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3407125","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-19DOI: 10.1109/TCSI.2024.3441852
Xiaoyuan Wang;Xinhui Chen;Jiawei Zhou;Gang Liu;Sung-Mo Kang;Sanjoy Kumar Nandi;Robert G. Elliman;Herbert Ho-Ching Iu
Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3–1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.
{"title":"A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application","authors":"Xiaoyuan Wang;Xinhui Chen;Jiawei Zhou;Gang Liu;Sung-Mo Kang;Sanjoy Kumar Nandi;Robert G. Elliman;Herbert Ho-Ching Iu","doi":"10.1109/TCSI.2024.3441852","DOIUrl":"10.1109/TCSI.2024.3441852","url":null,"abstract":"Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3–1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-19DOI: 10.1109/TCSI.2024.3438164
Zhenlin Pei;Hsiao-Hsuan Liu;Mahta Mayahinia;Mehdi B. Tahoori;Francky Catthoor;Zsolt Tőkei;Dawit Burusie Abdi;James Myers;Chenyun Pan
SRAM performance is highly dominated by interconnects as technology scales down because of the significant parasitic resistance and capacitance in the interconnect. This paper introduces a framework for the co-design of technology, interconnect, and cache memory with tag array overhead, to optimize the performance of cache memory using a variety of emerging interconnect technologies. In addition, we introduce an innovative E-Tree interconnect aimed at further decreasing the average interconnect length with the consideration of realistic workloads and benchmark against its traditional H-Tree counterparts in terms of various performance metrics, such as energy-delay-area product (EDAP) or energy-delay product (EDP) in the SRAM cache memory system. A comprehensive investigation of design space is conducted, employing realistic, deeply scaled subarray designs across a range of cutting-edge technology nodes. Furthermore, the case study examines various cache memory system design parameters to assess the true potential of emerging interconnect technologies in achieving optimal performance at the cache memory system.
{"title":"Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus","authors":"Zhenlin Pei;Hsiao-Hsuan Liu;Mahta Mayahinia;Mehdi B. Tahoori;Francky Catthoor;Zsolt Tőkei;Dawit Burusie Abdi;James Myers;Chenyun Pan","doi":"10.1109/TCSI.2024.3438164","DOIUrl":"10.1109/TCSI.2024.3438164","url":null,"abstract":"SRAM performance is highly dominated by interconnects as technology scales down because of the significant parasitic resistance and capacitance in the interconnect. This paper introduces a framework for the co-design of technology, interconnect, and cache memory with tag array overhead, to optimize the performance of cache memory using a variety of emerging interconnect technologies. In addition, we introduce an innovative E-Tree interconnect aimed at further decreasing the average interconnect length with the consideration of realistic workloads and benchmark against its traditional H-Tree counterparts in terms of various performance metrics, such as energy-delay-area product (EDAP) or energy-delay product (EDP) in the SRAM cache memory system. A comprehensive investigation of design space is conducted, employing realistic, deeply scaled subarray designs across a range of cutting-edge technology nodes. Furthermore, the case study examines various cache memory system design parameters to assess the true potential of emerging interconnect technologies in achieving optimal performance at the cache memory system.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-19DOI: 10.1109/tcsi.2024.3443195
Xingyin Xiong, Zongwei Li, Kedu Han
{"title":"A Nearing-Free Constrained Architecture for Systematic Design of Electromechanical Sigma-Delta Modulator","authors":"Xingyin Xiong, Zongwei Li, Kedu Han","doi":"10.1109/tcsi.2024.3443195","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3443195","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-19DOI: 10.1109/tcsi.2024.3441376
Aasish Boora, Bharatha Kumar Thangarasu, Kiat Seng Yeo
{"title":"A dB-Linear Programmable Gain Amplifier With Mixed-Signal Control for Wide-Gain Range and Low-Power Applications","authors":"Aasish Boora, Bharatha Kumar Thangarasu, Kiat Seng Yeo","doi":"10.1109/tcsi.2024.3441376","DOIUrl":"https://doi.org/10.1109/tcsi.2024.3441376","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-19DOI: 10.1109/TCSI.2024.3441508
David A. Zambrano-Prada;Abdelali El Aroudi;Oswaldo López-Santos;Luis Vázquez-Seisdedos;Luis Martínez-Salamero
A constant power (CP)-constant voltage (CV) protocol for battery charging is implemented in a conventional boost converter with output filter (BOF) by imposing loss-free resistor (LFR) behavior during the CP phase. To compare on equal basis the performance of the new CP-CV technique with the classical constant current (CC)–CV protocol, the latter is also implemented in the same power stage. The CC phase in BOF is attained by imposing a G-gyrator of type II behavior to the converter. A versatile controller uses the same voltage regulation loop for both protocols during the CV phase and a slightly different loop for the CP and CC phases. The latter loop is based in both CP and CC phases on the sliding-mode control (SMC) of the input inductor current of BOF, which in steady-state is made proportional to the input voltage in the LFR case or to the output voltage in the gyrator implementation. To compensate for the slow variations of the battery voltage during the CC phase, a proportional-integral (PI) current regulator has been added in the gyrator realization. The comparison of the corresponding experimental results shows identical behavior in both approaches in the measured waveforms, component stress, efficiency and external temperature. The simplicity of the CP-CV implementation based on LFR allows the extension of the proposed protocol to other hard-switching converters.
通过在 CP 阶段实施无损耗电阻（LFR）行为，在带输出滤波器（BOF）的传统升压转换器中实现了电池充电的恒功率（CP）-恒电压（CV）协议。为了在同等基础上比较新的 CP-CV 技术与经典的恒流 (CC) -CV 协议的性能，后者也在同一功率级中实施。BOF 中的 CC 阶段是通过在转换器中加入第二类行为的 G-gyrator 来实现的。多功能控制器在 CV 阶段对两种协议使用相同的电压调节回路，而在 CP 和 CC 阶段使用略有不同的回路。后一个环路在 CP 和 CC 阶段都基于 BOF 输入电感电流的滑模控制 (SMC)，在稳态情况下，LFR 与输入电压成正比，而在回旋器情况下，则与输出电压成正比。为了补偿 CC 阶段电池电压的缓慢变化，在回旋器中增加了一个比例积分（PI）电流调节器。对相应实验结果的比较显示，两种方法在测量波形、元件应力、效率和外部温度方面的表现完全相同。基于 LFR 的 CP-CV 实现非常简单，因此可以将所提出的协议扩展到其他硬开关转换器。
{"title":"Constant Power-Constant Voltage Battery Charging Based on a Loss-Free Resistor Approach","authors":"David A. Zambrano-Prada;Abdelali El Aroudi;Oswaldo López-Santos;Luis Vázquez-Seisdedos;Luis Martínez-Salamero","doi":"10.1109/TCSI.2024.3441508","DOIUrl":"10.1109/TCSI.2024.3441508","url":null,"abstract":"A constant power (CP)-constant voltage (CV) protocol for battery charging is implemented in a conventional boost converter with output filter (BOF) by imposing loss-free resistor (LFR) behavior during the CP phase. To compare on equal basis the performance of the new CP-CV technique with the classical constant current (CC)–CV protocol, the latter is also implemented in the same power stage. The CC phase in BOF is attained by imposing a G-gyrator of type II behavior to the converter. A versatile controller uses the same voltage regulation loop for both protocols during the CV phase and a slightly different loop for the CP and CC phases. The latter loop is based in both CP and CC phases on the sliding-mode control (SMC) of the input inductor current of BOF, which in steady-state is made proportional to the input voltage in the LFR case or to the output voltage in the gyrator implementation. To compensate for the slow variations of the battery voltage during the CC phase, a proportional-integral (PI) current regulator has been added in the gyrator realization. The comparison of the corresponding experimental results shows identical behavior in both approaches in the measured waveforms, component stress, efficiency and external temperature. The simplicity of the CP-CV implementation based on LFR allows the extension of the proposed protocol to other hard-switching converters.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-16DOI: 10.1109/TCSI.2024.3440842
Óscar Pereira-Rial;Juan M. Carrillo;Paula López
This paper explores the feasibility of a capacitor-less (CL) low-dropout (LDO) regulator to operate efficiently in a low-voltage environment. The CL-LDO scheme selected is based on a unity-gain feedback configuration around the error amplifier (EA), so that the inclusion of high-value on-chip resistors is avoided and different key parameters, such as the power supply rejection or the noise, are optimized. A comparative analysis has been carried out over the same LDO structure including a bulk-driven and a gate-driven EA, respectively. The pass branch of the voltage regulator is provided with pseudo-class-AB operation, in order to lead to a very small quiescent current in the standby operation mode, whereas a very large current can be delivered to the load when required. Both regulators were designed and fabricated in 180 nm CMOS technology to operate with a maximum supply voltage of 1.8 V. The extensive experimental characterization showed that the bulk-driven LDO can achieve a significantly lower minimum supply voltage, i.e., 0.6 V, as compared to the gate-driven counterpart, 1 V, under the same reference voltage and load current conditions.
本文探讨了无电容（CL）低压差（LDO）稳压器在低压环境下高效运行的可行性。所选的 CL-LDO 方案基于误差放大器 (EA) 周围的单增益反馈配置，从而避免了加入高值片上电阻，并优化了不同的关键参数，如电源抑制或噪声。我们对相同的 LDO 结构进行了比较分析，其中分别包括散装驱动型和栅极驱动型 EA。稳压器的通路支路采用伪 AB 类工作方式，以便在待机工作模式下产生极小的静态电流，而在需要时可向负载提供极大的电流。广泛的实验表征表明，在相同的基准电压和负载电流条件下，与栅极驱动型 LDO 的 1 V 电压相比，散装驱动型 LDO 的最低电源电压要低得多，仅为 0.6 V。
{"title":"Low-Voltage CMOS Capacitor-Less LDOs: Bulk-Driven Versus Gate-Driven Comparative Study","authors":"Óscar Pereira-Rial;Juan M. Carrillo;Paula López","doi":"10.1109/TCSI.2024.3440842","DOIUrl":"10.1109/TCSI.2024.3440842","url":null,"abstract":"This paper explores the feasibility of a capacitor-less (CL) low-dropout (LDO) regulator to operate efficiently in a low-voltage environment. The CL-LDO scheme selected is based on a unity-gain feedback configuration around the error amplifier (EA), so that the inclusion of high-value on-chip resistors is avoided and different key parameters, such as the power supply rejection or the noise, are optimized. A comparative analysis has been carried out over the same LDO structure including a bulk-driven and a gate-driven EA, respectively. The pass branch of the voltage regulator is provided with pseudo-class-AB operation, in order to lead to a very small quiescent current in the standby operation mode, whereas a very large current can be delivered to the load when required. Both regulators were designed and fabricated in 180 nm CMOS technology to operate with a maximum supply voltage of 1.8 V. The extensive experimental characterization showed that the bulk-driven LDO can achieve a significantly lower minimum supply voltage, i.e., 0.6 V, as compared to the gate-driven counterpart, 1 V, under the same reference voltage and load current conditions.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10638180","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-15DOI: 10.1109/TCSI.2024.3441834
Zi-Chen Fan;Di Li;Susanto Rahardja
This paper introduces a new fast algorithm for the discrete fractional Hadamard transform (FHT). The proposed algorithm demonstrates superior computational efficiency. For data lengths ranging from $2 leq N leq 1024$ , our algorithm achieves a reduction in the number of multiplications by up to 96.53%, 81.82%, 33.33%, and 90% compared to four existing fast algorithms for the FHT. Additionally, we compare the execution times with those of existing fast algorithms, and the results show that the proposed algorithm has better performance. The reduced computational complexity makes the proposed algorithm a potential candidate for calculating the FHT.
{"title":"Efficient Computation for Discrete Fractional Hadamard Transform","authors":"Zi-Chen Fan;Di Li;Susanto Rahardja","doi":"10.1109/TCSI.2024.3441834","DOIUrl":"10.1109/TCSI.2024.3441834","url":null,"abstract":"This paper introduces a new fast algorithm for the discrete fractional Hadamard transform (FHT). The proposed algorithm demonstrates superior computational efficiency. For data lengths ranging from \u0000<inline-formula> <tex-math>$2 leq N leq 1024$ </tex-math></inline-formula>\u0000, our algorithm achieves a reduction in the number of multiplications by up to 96.53%, 81.82%, 33.33%, and 90% compared to four existing fast algorithms for the FHT. Additionally, we compare the execution times with those of existing fast algorithms, and the results show that the proposed algorithm has better performance. The reduced computational complexity makes the proposed algorithm a potential candidate for calculating the FHT.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-15DOI: 10.1109/TCSI.2024.3431276
Huanqing Wang;Zhu Meng;Junfei Qiao;Siwen Liu
This article considers the issue of adaptive fuzzy predefined-time control for nonlinear systems. Fuzzy logic systems (FLSs) are introduced to estimate the uncertain nonlinear functions. The command filter technology is applied to overcome the difficulty of “explosion of complexity”. The error compensation mechanism is adopted to compensate the error generated via command filter. Based on the backstepping technique, a fuzzy adaptive predefined-time command filter control scheme is presented. The presented control strategy demonstrates that all the signals in closed-loop system are bounded and the tracking error can converge to a small area near zero within predefined time. The simulation results illustrate the validity of the developed control strategy.
{"title":"Command Filtered-Based Adaptive Predefined-Time Control for Uncertain Nonlinear Systems With Applications to RLC Circuit","authors":"Huanqing Wang;Zhu Meng;Junfei Qiao;Siwen Liu","doi":"10.1109/TCSI.2024.3431276","DOIUrl":"10.1109/TCSI.2024.3431276","url":null,"abstract":"This article considers the issue of adaptive fuzzy predefined-time control for nonlinear systems. Fuzzy logic systems (FLSs) are introduced to estimate the uncertain nonlinear functions. The command filter technology is applied to overcome the difficulty of “explosion of complexity”. The error compensation mechanism is adopted to compensate the error generated via command filter. Based on the backstepping technique, a fuzzy adaptive predefined-time command filter control scheme is presented. The presented control strategy demonstrates that all the signals in closed-loop system are bounded and the tracking error can converge to a small area near zero within predefined time. The simulation results illustrate the validity of the developed control strategy.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":null,"pages":null},"PeriodicalIF":5.2,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142179204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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