Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3460265
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSI.2024.3460265","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3460265","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"C3-C3"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702445","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3463708
Zhoujie Wu;Cai Luo;Zhong Guan
This paper proposes a dynamic capacitance matching (DCM)-based RC current response algorithm for calculating the current waveform of a signal line without performing transistor level SPICE simulation. Specifically, unlike previous methods such as current source model, driver linear representation, waveform functional fitting or equivalent load capacitance, our algorithm does not rely on fixed reduced model of standard-cell driver or RC load. Instead, it approaches the current waveform dynamically by computing current responses of the target driver for various load scenarios. Besides, we creatively use symbolic expression to combine the y-parameter of RC network with the pre-characterized driver library in order to perform capacitance matching and simulate current waveform by considering the Miller and over/undershoot effects. Our algorithm is experimentally verified on 40nm CMOS technology and has been adopted by latest commercial tool for different nodes (from 180nm to 3nm). Experimental results show that our algorithm has only about 1% error compared with SPICE golden results while the runtime is improved by 50 to 200 times, which demonstrates overwhelming capability in calculating timing, power and electromigration of signal lines.
{"title":"A Dynamic Capacitance Matching (DCM)-Based Current Response Algorithm for Signal Line RC Network","authors":"Zhoujie Wu;Cai Luo;Zhong Guan","doi":"10.1109/TCSI.2024.3463708","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3463708","url":null,"abstract":"This paper proposes a dynamic capacitance matching (DCM)-based RC current response algorithm for calculating the current waveform of a signal line without performing transistor level SPICE simulation. Specifically, unlike previous methods such as current source model, driver linear representation, waveform functional fitting or equivalent load capacitance, our algorithm does not rely on fixed reduced model of standard-cell driver or RC load. Instead, it approaches the current waveform dynamically by computing current responses of the target driver for various load scenarios. Besides, we creatively use symbolic expression to combine the y-parameter of RC network with the pre-characterized driver library in order to perform capacitance matching and simulate current waveform by considering the Miller and over/undershoot effects. Our algorithm is experimentally verified on 40nm CMOS technology and has been adopted by latest commercial tool for different nodes (from 180nm to 3nm). Experimental results show that our algorithm has only about 1% error compared with SPICE golden results while the runtime is improved by 50 to 200 times, which demonstrates overwhelming capability in calculating timing, power and electromigration of signal lines.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 12","pages":"5804-5813"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3460263
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors","authors":"","doi":"10.1109/TCSI.2024.3460263","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3460263","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4898-4898"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702479","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3464734
Hui-Yang Li;Jin-Xu Xu;Xiu Yin Zhang
In this paper, we propose a compact wideband on-chip millimeter-wave (mm-wave) reconfigurable wideband filtering switch in 28-nm bulk CMOS technology. A dual-mode LC resonator loaded with transistors is used to achieve wideband filtering responses with a transmission zero at the lower frequency band. The resonant frequency of the resonator and the location of the transmission zero can be conveniently tuned to reconfigure the passband and stopband frequencies by turning on and off the transistor. Moreover, the passband can also be switched on and off, enabling the single-pole single-throw filtering switch circuit function. In this way, the proposed mm-wave reconfigurable filtering switch is applicable to the integrated sensing and communication (ISAC) system, where image rejection in communication operation and a wide bandwidth (or high resolution) in sensing operation are both required. Furthermore, to meet the applications in the ISAC systems with different architectures, extension designs of the proposed reconfigurable filtering switch with the impedance conversion function, high-order responses, balanced-to-unbalanced transition, and differential input/output ports are presented in detailed. For demonstration, the wideband reconfigurable filtering switch has been fabricated. The core circuit has a very compact size of $0.205times 0.140$ mm2. Experimental results show that the passband can be reconfigured between 20-55 GHz and 37-44 GHz, with a rejection >17 dB for sensing operation and >12 dB image-band rejection for communication operation, respectively. High off-state isolation of better than 24.8 dB is also achieved.
{"title":"Compact On-Chip mm-wave Reconfigurable Wideband Filtering Switch in 28-nm Bulk CMOS for Integrated Sensing and Communication System Applications","authors":"Hui-Yang Li;Jin-Xu Xu;Xiu Yin Zhang","doi":"10.1109/TCSI.2024.3464734","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3464734","url":null,"abstract":"In this paper, we propose a compact wideband on-chip millimeter-wave (mm-wave) reconfigurable wideband filtering switch in 28-nm bulk CMOS technology. A dual-mode LC resonator loaded with transistors is used to achieve wideband filtering responses with a transmission zero at the lower frequency band. The resonant frequency of the resonator and the location of the transmission zero can be conveniently tuned to reconfigure the passband and stopband frequencies by turning on and off the transistor. Moreover, the passband can also be switched on and off, enabling the single-pole single-throw filtering switch circuit function. In this way, the proposed mm-wave reconfigurable filtering switch is applicable to the integrated sensing and communication (ISAC) system, where image rejection in communication operation and a wide bandwidth (or high resolution) in sensing operation are both required. Furthermore, to meet the applications in the ISAC systems with different architectures, extension designs of the proposed reconfigurable filtering switch with the impedance conversion function, high-order responses, balanced-to-unbalanced transition, and differential input/output ports are presented in detailed. For demonstration, the wideband reconfigurable filtering switch has been fabricated. The core circuit has a very compact size of \u0000<inline-formula> <tex-math>$0.205times 0.140$ </tex-math></inline-formula>\u0000 mm2. Experimental results show that the passband can be reconfigured between 20-55 GHz and 37-44 GHz, with a rejection >17 dB for sensing operation and >12 dB image-band rejection for communication operation, respectively. High off-state isolation of better than 24.8 dB is also achieved.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"125-134"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3460261
{"title":"IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information","authors":"","doi":"10.1109/TCSI.2024.3460261","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3460261","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"C2-C2"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702443","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142376873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3452954
Qingyu Guo;Haoyang Luo;Meng Li;Xiyuan Tang;Yuan Wang
Layer Pipeline (LP) represents an innovative architecture for neural network accelerators, which implements task-level pipelining at the granularity of layers. Despite improvements in throughput, LP architectures face challenges due to complicated dataflow design, intricate design space and high resource requirements. In this paper, we introduce an accelerator synthesis framework, CASCADE. CASCADE leverages a novel dataflow, CARD, to efficiently manage convolutional operations’ irregular memory access patterns using simplified logic and minimal buffers. It also employs advanced design space exploration methods to optimize unrolling parallelism and FIFO depth settings automatically for each layer. Finally, to further enhance resource efficiency, CASCADE leverages Lookup Table-based multiplication and accumulation units. With extensive experimental results, we demonstrate that CASCADE significantly outperforms existing works, achieving a $3times $ improvement in resource efficiency and a $4times $ improvement in power efficiency. It achieves over $1.5times 10^{4}$ frames per second throughput and 71.9% accuracy on ImageNet.
{"title":"CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow","authors":"Qingyu Guo;Haoyang Luo;Meng Li;Xiyuan Tang;Yuan Wang","doi":"10.1109/TCSI.2024.3452954","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3452954","url":null,"abstract":"Layer Pipeline (LP) represents an innovative architecture for neural network accelerators, which implements task-level pipelining at the granularity of layers. Despite improvements in throughput, LP architectures face challenges due to complicated dataflow design, intricate design space and high resource requirements. In this paper, we introduce an accelerator synthesis framework, CASCADE. CASCADE leverages a novel dataflow, CARD, to efficiently manage convolutional operations’ irregular memory access patterns using simplified logic and minimal buffers. It also employs advanced design space exploration methods to optimize unrolling parallelism and FIFO depth settings automatically for each layer. Finally, to further enhance resource efficiency, CASCADE leverages Lookup Table-based multiplication and accumulation units. With extensive experimental results, we demonstrate that CASCADE significantly outperforms existing works, achieving a \u0000<inline-formula> <tex-math>$3times $ </tex-math></inline-formula>\u0000 improvement in resource efficiency and a \u0000<inline-formula> <tex-math>$4times $ </tex-math></inline-formula>\u0000 improvement in power efficiency. It achieves over \u0000<inline-formula> <tex-math>$1.5times 10^{4}$ </tex-math></inline-formula>\u0000 frames per second throughput and 71.9% accuracy on ImageNet.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 11","pages":"5235-5248"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3462329
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSI.2024.3462329","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3462329","url":null,"abstract":"","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"71 10","pages":"4897-4897"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702446","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142368487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TCSI.2024.3457541
Brunno Alves de Abreu;Guilherme Paim;Lilas Alrahis;Paulo Flores;Ozgur Sinanoglu;Sergio Bampi;Hussam Amrouch
The popularity and widespread usage of machine learning (ML) hardware have created challenges for its intellectual property (IP) protection. Logic locking is a widely used technique for IP protection but has received little attention in error-resilient applications such as ML hardware modules. This work investigates the effectiveness of logic locking when applied to tree-based ML circuits and reveals a critical vulnerability that undermines its effectiveness for single-label ML classifiers. We propose a logic locking scheme to eliminate the vulnerabilities in decision trees (DTs) and random forests (RFs) circuits. In our extensive simulation involving 16 DTs and 16 RFs, our solution consistently thwarts the vulnerability. We further evaluated the security of our approach by considering different obfuscation percentages and launching state-of-the-art oracle-less attacks on logic locking. Our method proves resilient, indicating that by fixing the identified vulnerability, we did not introduce new attack vectors. Further, our investigation indicates that DT/RF accelerators are significantly less vulnerable to oracle-less attacks compared to exact circuits. Overall, our work lays the foundation for future investigations into the effectiveness of logic locking for ML circuits.
{"title":"On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning","authors":"Brunno Alves de Abreu;Guilherme Paim;Lilas Alrahis;Paulo Flores;Ozgur Sinanoglu;Sergio Bampi;Hussam Amrouch","doi":"10.1109/TCSI.2024.3457541","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3457541","url":null,"abstract":"The popularity and widespread usage of machine learning (ML) hardware have created challenges for its intellectual property (IP) protection. Logic locking is a widely used technique for IP protection but has received little attention in error-resilient applications such as ML hardware modules. This work investigates the effectiveness of logic locking when applied to tree-based ML circuits and reveals a critical vulnerability that undermines its effectiveness for single-label ML classifiers. We propose a logic locking scheme to eliminate the vulnerabilities in decision trees (DTs) and random forests (RFs) circuits. In our extensive simulation involving 16 DTs and 16 RFs, our solution consistently thwarts the vulnerability. We further evaluated the security of our approach by considering different obfuscation percentages and launching state-of-the-art oracle-less attacks on logic locking. Our method proves resilient, indicating that by fixing the identified vulnerability, we did not introduce new attack vectors. Further, our investigation indicates that DT/RF accelerators are significantly less vulnerable to oracle-less attacks compared to exact circuits. Overall, our work lays the foundation for future investigations into the effectiveness of logic locking for ML circuits.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"180-191"},"PeriodicalIF":5.2,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TCSI.2024.3463184
Xu Zhang;Yaodong Wei;Minghao Li;Jing Tian;Zhongfeng Wang
Recently, four NIST-approved Post-Quantum Cryptography (PQC) algorithms are selected to be standardized. Three of them are lattice-based cryptographic schemes and feature the number-theoretic transform (NTT) as the computing bottleneck compelling fast and low-power hardware implementations. In this work, a high-speed and power-efficient NTT accelerator is presented leveraging the compute-in-memory (CIM) technique with bottom-up optimizations. Firstly, a carry-free modular multiplication (CFMM) algorithm is proposed, which utilizes on-the-fly reduction and hybrid-redundant representation to optimize the butterfly unit operation, the cornerstone of NTT. Based on the optimized algorithm, an efficient butterfly unit in memory (BUIM) is developed by co-designing with SRAM circuit, which saves the memory access energy, decreases operation cycles, and obtains ultra-short critical path. Additionally, the data pattern of CIM array is also improved to avoid redundant memory read/write operations, which further reduces memory access overhead. Finally, a combination of pipelined operation flow and constant interstage data mapping strategy is employed to bestow the proposed hybrid-redundant CIM NTT (HRCIM-NTT) architecture with minimized computing cycles and reduced routing overhead. The implementation under 45nm CMOS technology demonstrates that HRCIM-NTT achieves the highest throughput and lowest latency among the existing CIM-based NTT accelerators.
{"title":"HRCIM-NTT: An Efficient Compute-in-Memory NTT Accelerator With Hybrid-Redundant Numbers","authors":"Xu Zhang;Yaodong Wei;Minghao Li;Jing Tian;Zhongfeng Wang","doi":"10.1109/TCSI.2024.3463184","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3463184","url":null,"abstract":"Recently, four NIST-approved Post-Quantum Cryptography (PQC) algorithms are selected to be standardized. Three of them are lattice-based cryptographic schemes and feature the number-theoretic transform (NTT) as the computing bottleneck compelling fast and low-power hardware implementations. In this work, a high-speed and power-efficient NTT accelerator is presented leveraging the compute-in-memory (CIM) technique with bottom-up optimizations. Firstly, a carry-free modular multiplication (CFMM) algorithm is proposed, which utilizes on-the-fly reduction and hybrid-redundant representation to optimize the butterfly unit operation, the cornerstone of NTT. Based on the optimized algorithm, an efficient butterfly unit in memory (BUIM) is developed by co-designing with SRAM circuit, which saves the memory access energy, decreases operation cycles, and obtains ultra-short critical path. Additionally, the data pattern of CIM array is also improved to avoid redundant memory read/write operations, which further reduces memory access overhead. Finally, a combination of pipelined operation flow and constant interstage data mapping strategy is employed to bestow the proposed hybrid-redundant CIM NTT (HRCIM-NTT) architecture with minimized computing cycles and reduced routing overhead. The implementation under 45nm CMOS technology demonstrates that HRCIM-NTT achieves the highest throughput and lowest latency among the existing CIM-based NTT accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"214-227"},"PeriodicalIF":5.2,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1109/TCSI.2024.3463536
Jafar Shamsi;Wilten Nicola
Pulse-coupled oscillators (PCOs) are used as models for oscillatory systems in diverse fields such as biology, physics, and engineering. When correctly coupled, PCOs can display sophisticated emergent dynamics for a large number of oscillators. Here, we propose an algorithm and hardware implementation of PCOs to emulate arbitrary systems of linear differential equations (DEs) with inputs, which are similar to the equations used in feedback control laws or linearizations of nonlinear systems. We show that m populations of oscillators can solve a set of m-dimensional linear DEs with simple coupling schemes, and crucially, without the matrix multiplications required in Euler integration. The emergence of linear dynamical systems in networks of PCOs occurs when the number of oscillators within a population becomes large, as demonstrated through an analytically exact mean-field derivation. In addition, a hardware architecture of PCOs for digital implementation is proposed and realized on an ultra-low power FPGA as a proof of concept. These results show that there are simple coupling schemes for pulse-coupled oscillator networks that collectively compute complex dynamical systems. These PCO networks also have an immediate implementation as low power neuromorphic edge devices.
{"title":"Implementation of Linear Differential Equations Using Pulse-Coupled Oscillators With an Ultra-Low Power Neuromorphic Realization","authors":"Jafar Shamsi;Wilten Nicola","doi":"10.1109/TCSI.2024.3463536","DOIUrl":"https://doi.org/10.1109/TCSI.2024.3463536","url":null,"abstract":"Pulse-coupled oscillators (PCOs) are used as models for oscillatory systems in diverse fields such as biology, physics, and engineering. When correctly coupled, PCOs can display sophisticated emergent dynamics for a large number of oscillators. Here, we propose an algorithm and hardware implementation of PCOs to emulate arbitrary systems of linear differential equations (DEs) with inputs, which are similar to the equations used in feedback control laws or linearizations of nonlinear systems. We show that m populations of oscillators can solve a set of m-dimensional linear DEs with simple coupling schemes, and crucially, without the matrix multiplications required in Euler integration. The emergence of linear dynamical systems in networks of PCOs occurs when the number of oscillators within a population becomes large, as demonstrated through an analytically exact mean-field derivation. In addition, a hardware architecture of PCOs for digital implementation is proposed and realized on an ultra-low power FPGA as a proof of concept. These results show that there are simple coupling schemes for pulse-coupled oscillator networks that collectively compute complex dynamical systems. These PCO networks also have an immediate implementation as low power neuromorphic edge devices.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 1","pages":"14-24"},"PeriodicalIF":5.2,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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