Pub Date : 2025-04-22DOI: 10.1109/TCSI.2025.3559805
Fakir Sharif Hossain;Ashek Seum;Md. Reasad Zaman Chowdhury;Foisal Ahmed
Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.
{"title":"ZDD: A Zero Delay Deviation Variability-Aware Golden Free Hardware Trojan Detection Using Physical Unclonable Function","authors":"Fakir Sharif Hossain;Ashek Seum;Md. Reasad Zaman Chowdhury;Foisal Ahmed","doi":"10.1109/TCSI.2025.3559805","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559805","url":null,"abstract":"Hardware Trojan detection through side-channel analysis in physical chips is very challenging due to the presence of manufacturing process variations. Numerous Trojan detection approaches are in the literature. However, most of them are limited to netlist level identification and unable to explain the process variation issue in post-silicon chips. In this work, we propose a new detection technique with delay side-channel analysis that can detect all types of Trojans under the presence of high process variations. The technique is termed as zero delay deviation (ZDD) that is capable of diminishing the effect of all variations and other noise sources to identify the Trojan presence in chips. The ZDD approach is achieved by 1) a novel equal-delay circuit partitioning, 2) placing a highly secured camouflaged ring oscillator PUF per partition to generate equal-delay challenge-response pairs that delivers the knowledge of variation trends, 3) generating Identical Delay (ID) neighboring pairs for both, partitions and PUF designs that ensure nullifying the variation effects upon comparing them. The ZDD is examined through an intra-referencing of ID pairs with PUF-RD pairs in ISCAS’85 and 89 benchmarks. 10,000 virtual chips are generated by Monte Carlo simulation considering all physical characteristics of a real chip. Results demonstrate that the proposed approach can successfully detect Trojans even if it consists of a single gate. A comparison to the state-of-the-art shows the method superiority over others.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4153-4166"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144739911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCSI.2025.3559719
Hong Jiang;Guangren Duan;Mingzhe Hou
In this paper, a robust adaptive control scheme based on the unknown input observer is proposed for fully actuated systems with uncertainties. First, a nonlinear reduced-order unknown input observer with an integral term is introduced to decouple the uncertainties in the system and suppresses the output noises via the action of integral term. Then the linear matrix inequality for solving the observer gains is given by using the linear parameter varying method to treat the nonlinearity. Second, a robust adaptive controller based on the proposed observer, with the adaptive law to estimate the bound of uncertainties, is designed to make the states uniformly ultimately bounded. Due to the design of robust part, the ultimate bounds of states of the closed-loop system can be adjusted via the designed parameters. A simulation of the electromechanical system is given to demonstrate the effectiveness of the proposed method.
{"title":"Robust Adaptive Control Based on Reduced-Order Unknown Input Observer for Fully Actuated Systems With Uncertainties","authors":"Hong Jiang;Guangren Duan;Mingzhe Hou","doi":"10.1109/TCSI.2025.3559719","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559719","url":null,"abstract":"In this paper, a robust adaptive control scheme based on the unknown input observer is proposed for fully actuated systems with uncertainties. First, a nonlinear reduced-order unknown input observer with an integral term is introduced to decouple the uncertainties in the system and suppresses the output noises via the action of integral term. Then the linear matrix inequality for solving the observer gains is given by using the linear parameter varying method to treat the nonlinearity. Second, a robust adaptive controller based on the proposed observer, with the adaptive law to estimate the bound of uncertainties, is designed to make the states uniformly ultimately bounded. Due to the design of robust part, the ultimate bounds of states of the closed-loop system can be adjusted via the designed parameters. A simulation of the electromechanical system is given to demonstrate the effectiveness of the proposed method.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 9","pages":"4946-4956"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145057454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TCSI.2025.3560295
Kai Yu;Ruixin Wu;Sizhen Li;Junfeng Gao;Mo Huang
This paper presents an enhanced three-level buck converter (E3LBC) with configurable power stage (CPS) and configurable control stage (CCS) for fast load transient response. Compared with the conventional 3LBC and existing solutions, the proposed CPS can raise the inductor current slope significantly by changing the switching node voltage to 3/2 times or −1/2 times the input voltage ($V_{mathrm {IN}}$ ) during the load-increasing or load-decreasing transient, which will improve the load transient response. Moreover, the CPS can realize the series or parallel operations of flying capacitors ($C_{mathrm {F1,}}~C_{mathrm {F2}}$ ) and make their voltages ($V_{mathrm {CF1}}$ , $V_{mathrm {CF2}}$ ) eventually converge to $V_{mathrm {IN}}$ /2. On the other hand, the proposed CCS can eliminate the minimum off or on time by using hysteresis control and keep the inductor charging or discharging all the time during the load-increasing or load-decreasing transient for further improving load transient response. Besides, the CCS can provide an adaptive-on-time control in the steady state to acquire a pseudo-constant frequency for small output voltage ripple. The prototype design has been fabricated with the 0.18-$mu $ m CMOS process. According to the measurement results, the E3LBC exhibits undershoot/overshoot voltages and settling time of −19/+30 mV and 1.2/$1.1~mu $ s, when the load current is changed between 100 mA and 500 mA. The other measurements and comparisons also verify the effectiveness of CPS and CCS for the E3LBC.
{"title":"Design of Enhanced Three-Level Buck Converter With Configurable Power and Control Stages for Fast Load Transient Response","authors":"Kai Yu;Ruixin Wu;Sizhen Li;Junfeng Gao;Mo Huang","doi":"10.1109/TCSI.2025.3560295","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560295","url":null,"abstract":"This paper presents an enhanced three-level buck converter (E3LBC) with configurable power stage (CPS) and configurable control stage (CCS) for fast load transient response. Compared with the conventional 3LBC and existing solutions, the proposed CPS can raise the inductor current slope significantly by changing the switching node voltage to 3/2 times or −1/2 times the input voltage (<inline-formula> <tex-math>$V_{mathrm {IN}}$ </tex-math></inline-formula>) during the load-increasing or load-decreasing transient, which will improve the load transient response. Moreover, the CPS can realize the series or parallel operations of flying capacitors (<inline-formula> <tex-math>$C_{mathrm {F1,}}~C_{mathrm {F2}}$ </tex-math></inline-formula>) and make their voltages (<inline-formula> <tex-math>$V_{mathrm {CF1}}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$V_{mathrm {CF2}}$ </tex-math></inline-formula>) eventually converge to <inline-formula> <tex-math>$V_{mathrm {IN}}$ </tex-math></inline-formula>/2. On the other hand, the proposed CCS can eliminate the minimum off or on time by using hysteresis control and keep the inductor charging or discharging all the time during the load-increasing or load-decreasing transient for further improving load transient response. Besides, the CCS can provide an adaptive-on-time control in the steady state to acquire a pseudo-constant frequency for small output voltage ripple. The prototype design has been fabricated with the 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process. According to the measurement results, the E3LBC exhibits undershoot/overshoot voltages and settling time of −19/+30 mV and 1.2/<inline-formula> <tex-math>$1.1~mu $ </tex-math></inline-formula>s, when the load current is changed between 100 mA and 500 mA. The other measurements and comparisons also verify the effectiveness of CPS and CCS for the E3LBC.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 11","pages":"7401-7410"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A tradeoff between bandwidth and back-off range is commonly found in the Doherty power amplifier (DPA). This paper proposes an input phase control mechanism together with a cooperative asymmetric out-phased current load modulation technique. The cooperative asymmetric out-phased current load modulation can extend the output back-off range (OBO). The input phase control mechanism together with modified impedance transforming load modulation networks (LMNs) is used to widen the DPA bandwidth. An input coupled-line coupler is implemented to realize this phase requirement. For demonstration purposes, a DPA with an operating frequency from 1.7 GHz to 2.9 GHz and with a 9-dB OBO range is designed and fabricated using GaN HEMT devices. Continuous-wave measurements show that the implemented DPA exhibits a drain efficiency ranging from 54.5% to 75.6% at saturation and from 41% to 50.6% at 9-dB OBO across the operating bandwidth. When excited by a 20-MHz long-term evolution (LTE) signal with a 9-dB peak-to-average power ratio (PAPR), the implemented DPA achieves average drain efficiencies of 41%- 53.8% with an adjacent channel leakage ratio (ACLR) better than −48.1 dBc after digital predistortion (DPD).
{"title":"Input Phase Controlled Doherty Power Amplifier With Out-Phased Current Load Modulation for Arbitrary Output Back-Off","authors":"Bai Hua Zeng;Yu Fei Pan;Fu Cheng Yuan;Wing Shing Chan;Shao Yong Zheng","doi":"10.1109/TCSI.2025.3557496","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3557496","url":null,"abstract":"A tradeoff between bandwidth and back-off range is commonly found in the Doherty power amplifier (DPA). This paper proposes an input phase control mechanism together with a cooperative asymmetric out-phased current load modulation technique. The cooperative asymmetric out-phased current load modulation can extend the output back-off range (OBO). The input phase control mechanism together with modified impedance transforming load modulation networks (LMNs) is used to widen the DPA bandwidth. An input coupled-line coupler is implemented to realize this phase requirement. For demonstration purposes, a DPA with an operating frequency from 1.7 GHz to 2.9 GHz and with a 9-dB OBO range is designed and fabricated using GaN HEMT devices. Continuous-wave measurements show that the implemented DPA exhibits a drain efficiency ranging from 54.5% to 75.6% at saturation and from 41% to 50.6% at 9-dB OBO across the operating bandwidth. When excited by a 20-MHz long-term evolution (LTE) signal with a 9-dB peak-to-average power ratio (PAPR), the implemented DPA achieves average drain efficiencies of 41%- 53.8% with an adjacent channel leakage ratio (ACLR) better than −48.1 dBc after digital predistortion (DPD).","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2626-2638"},"PeriodicalIF":5.2,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-21DOI: 10.1109/TCSI.2025.3559987
Jun-Lan Wang;Xiao-Jian Li
This paper investigates the data-based attack detection and identification for cyber-physical systems (CPSs) under sparse sensor attacks. In order to improve the identification performance, a novel scheme based on an iterative reweighted $l_{2}/l_{1}$ minimization algorithm is presented. Firstly, a threshold that characterizes the maximum number of identifiable attacks is determined. By introducing the reweighting technique, smaller weights are assigned to the relatively easy-to-identify attacks, namely, blocks with larger $l_{2}$ -norms, thus forcing the minimization to focus on the ones with smaller $l_{2}$ -norms. Then, the number of identifiable attacks is enhanced and a higher identification accuracy is guaranteed compared with the existing results. Finally, three examples are given to verify the effectiveness and advantages of the proposed scheme in both noisy and noiseless cases.
{"title":"Data-Driven Attack Detection and Identification for Cyber-Physical Systems Under Sparse Sensor Attacks: Iterative Reweighted l2/l1 Recovery Approach","authors":"Jun-Lan Wang;Xiao-Jian Li","doi":"10.1109/TCSI.2025.3559987","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559987","url":null,"abstract":"This paper investigates the data-based attack detection and identification for cyber-physical systems (CPSs) under sparse sensor attacks. In order to improve the identification performance, a novel scheme based on an iterative reweighted <inline-formula> <tex-math>$l_{2}/l_{1}$ </tex-math></inline-formula> minimization algorithm is presented. Firstly, a threshold that characterizes the maximum number of identifiable attacks is determined. By introducing the reweighting technique, smaller weights are assigned to the relatively easy-to-identify attacks, namely, blocks with larger <inline-formula> <tex-math>$l_{2}$ </tex-math></inline-formula>-norms, thus forcing the minimization to focus on the ones with smaller <inline-formula> <tex-math>$l_{2}$ </tex-math></inline-formula>-norms. Then, the number of identifiable attacks is enhanced and a higher identification accuracy is guaranteed compared with the existing results. Finally, three examples are given to verify the effectiveness and advantages of the proposed scheme in both noisy and noiseless cases.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2890-2902"},"PeriodicalIF":5.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the DC microgrid cluster system, due to the large number of converters, there are many operation modes and switching frequencies. The traditional modeling methods are difficult to balance the accuracy of the model and the simplicity of calculation and are not suitable for different switching frequency systems. In view of the above problems, this paper uses simplified discrete time mapping model to model the system. It combines the state space average model with the discrete time mapping model, which greatly improves the simplicity and accuracy of modeling. Taking the photovoltaic-energy storage system as an example, this paper analyzes the nonlinear behavior of the system and predicts the critical control parameters when the Hopf bifurcation occurs in the system. The eigenvalue sensitivity analysis is used to determine the eigenvalue change rate and change trend when the control parameters change, which provides guidance for the selection of parameters in practical applications. Finally, the high precision of the model is verified by simulation, and the applicability and effectiveness of the method in different switching frequency systems are verified by experiments.
{"title":"Modeling and Nonlinear Dynamic Behavior Analysis of Photovoltaic-Energy Storage DC Microgrid","authors":"Ronglong Wang;Fan Xie;Bo Zhang;Dongyuan Qiu;Wenxun Xiao;Yanfeng Chen","doi":"10.1109/TCSI.2025.3558905","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3558905","url":null,"abstract":"In the DC microgrid cluster system, due to the large number of converters, there are many operation modes and switching frequencies. The traditional modeling methods are difficult to balance the accuracy of the model and the simplicity of calculation and are not suitable for different switching frequency systems. In view of the above problems, this paper uses simplified discrete time mapping model to model the system. It combines the state space average model with the discrete time mapping model, which greatly improves the simplicity and accuracy of modeling. Taking the photovoltaic-energy storage system as an example, this paper analyzes the nonlinear behavior of the system and predicts the critical control parameters when the Hopf bifurcation occurs in the system. The eigenvalue sensitivity analysis is used to determine the eigenvalue change rate and change trend when the control parameters change, which provides guidance for the selection of parameters in practical applications. Finally, the high precision of the model is verified by simulation, and the applicability and effectiveness of the method in different switching frequency systems are verified by experiments.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2778-2791"},"PeriodicalIF":5.2,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-18DOI: 10.1109/TCSI.2025.3559727
Dong Liang;Hui Zhang;Yetong Wang;Linhao Ma;Shiyue Ma;Zhijun Zhou;Fanyi Meng;Kaixue Ma;Keping Wang
An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.
{"title":"Design of Oscillator-Based Reconfigurable Modulator With High-Q FBAR Resonators Supporting Fast OOK/BFSK/ BPSK Modulation","authors":"Dong Liang;Hui Zhang;Yetong Wang;Linhao Ma;Shiyue Ma;Zhijun Zhou;Fanyi Meng;Kaixue Ma;Keping Wang","doi":"10.1109/TCSI.2025.3559727","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3559727","url":null,"abstract":"An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 6","pages":"2543-2555"},"PeriodicalIF":5.2,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144171056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the dual spacecraft pursuit-evasion game problem under incomplete information is investigated, and a strategy-solving method for the incomplete information pursuit-evasion game based on particle swarm optimization and unscented particle filter (PSO-UPF) estimation is proposed. The completeness of the information available about the target’s cost function, which is determined by the weighting information, has a significant impact on the success of the pursuing strategy. For the cost function is unknown in incomplete information scenarios, a research framework of the pursuit-evasion game based on following observation and one-sided pursuit two stages is established. Besides, to describe the more accurate motion of the spacecraft, a Schweighart-Sedwick (SS) dynamic model is introduced that considers the effect of $J_{2}$ perturbation. Firstly, an equilibrium strategy for the SS model-based pursuit-evasion problem is derived under complete information. Next, for the incomplete information scenarios, an estimation method based on PSO-UPF of weight matrix information is established, which allows the cost function to be determined by the estimation method in the observation stage. Then, the pursuit strategy is re-designed in the one-sided pursuit stage based on the estimated cost function. Finally, the performance of the proposed method is validated by simulation. The results demonstrate that the approach can achieve good performance by efficiently estimating the weight information in the opponent’s cost function.
{"title":"Pursuit-Evasion Game for Spacecraft With Incomplete Information Under J₂ Perturbation","authors":"Zhenxin Mu;Mingjiang Ji;Pengyu Guo;Qufei Zhang;Bing Xiao;Lu Cao;Junzhi Yu","doi":"10.1109/TCSI.2025.3560303","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3560303","url":null,"abstract":"In this paper, the dual spacecraft pursuit-evasion game problem under incomplete information is investigated, and a strategy-solving method for the incomplete information pursuit-evasion game based on particle swarm optimization and unscented particle filter (PSO-UPF) estimation is proposed. The completeness of the information available about the target’s cost function, which is determined by the weighting information, has a significant impact on the success of the pursuing strategy. For the cost function is unknown in incomplete information scenarios, a research framework of the pursuit-evasion game based on following observation and one-sided pursuit two stages is established. Besides, to describe the more accurate motion of the spacecraft, a Schweighart-Sedwick (SS) dynamic model is introduced that considers the effect of <inline-formula> <tex-math>$J_{2}$ </tex-math></inline-formula> perturbation. Firstly, an equilibrium strategy for the SS model-based pursuit-evasion problem is derived under complete information. Next, for the incomplete information scenarios, an estimation method based on PSO-UPF of weight matrix information is established, which allows the cost function to be determined by the estimation method in the observation stage. Then, the pursuit strategy is re-designed in the one-sided pursuit stage based on the estimated cost function. Finally, the performance of the proposed method is validated by simulation. The results demonstrate that the approach can achieve good performance by efficiently estimating the weight information in the opponent’s cost function.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 8","pages":"4346-4358"},"PeriodicalIF":5.2,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144725238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TCSI.2025.3554635
Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu
FPGA accelerators for lightweight convolutional neural networks (LWCNNs) have recently attracted significant attention. Most existing LWCNN accelerators focus on single-Computing-Engine (CE) architecture with local optimization. However, these designs typically suffer from high on-chip/off-chip memory overhead and low computational efficiency due to their layer-by-layer dataflow and unified resource mapping mechanisms. To tackle these issues, a novel multi-CE-based accelerator with balanced dataflow is proposed to efficiently accelerate LWCNN through memory-oriented and computing-oriented optimizations. Firstly, a streaming architecture with hybrid CEs is designed to minimize off-chip memory access while maintaining a low cost of on-chip buffer size. Secondly, a balanced dataflow strategy is introduced for streaming architectures to enhance computational efficiency by improving efficient resource mapping and mitigating data congestion. Furthermore, a resource-aware memory and parallelism allocation methodology is proposed, based on a performance model, to achieve better performance and scalability. The proposed accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and ShuffleNetV2. Implementation results demonstrate that the proposed accelerator can save up to 68.3% of on-chip memory size with reduced off-chip memory access compared to the reference design. It achieves an impressive performance of up to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while maintaining a high DSP utilization of 95%, thus significantly outperforming current LWCNN accelerators.
{"title":"A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow","authors":"Zhiyuan Zhao;Yihao Chen;Pengcheng Feng;Jixing Li;Gang Chen;Rongxuan Shen;Huaxiang Lu","doi":"10.1109/TCSI.2025.3554635","DOIUrl":"https://doi.org/10.1109/TCSI.2025.3554635","url":null,"abstract":"FPGA accelerators for lightweight convolutional neural networks (LWCNNs) have recently attracted significant attention. Most existing LWCNN accelerators focus on single-Computing-Engine (CE) architecture with local optimization. However, these designs typically suffer from high on-chip/off-chip memory overhead and low computational efficiency due to their layer-by-layer dataflow and unified resource mapping mechanisms. To tackle these issues, a novel multi-CE-based accelerator with balanced dataflow is proposed to efficiently accelerate LWCNN through memory-oriented and computing-oriented optimizations. Firstly, a streaming architecture with hybrid CEs is designed to minimize off-chip memory access while maintaining a low cost of on-chip buffer size. Secondly, a balanced dataflow strategy is introduced for streaming architectures to enhance computational efficiency by improving efficient resource mapping and mitigating data congestion. Furthermore, a resource-aware memory and parallelism allocation methodology is proposed, based on a performance model, to achieve better performance and scalability. The proposed accelerator is evaluated on Xilinx ZC706 platform using MobileNetV2 and ShuffleNetV2. Implementation results demonstrate that the proposed accelerator can save up to 68.3% of on-chip memory size with reduced off-chip memory access compared to the reference design. It achieves an impressive performance of up to 2092.4 FPS and a state-of-the-art MAC efficiency of up to 94.58%, while maintaining a high DSP utilization of 95%, thus significantly outperforming current LWCNN accelerators.","PeriodicalId":13039,"journal":{"name":"IEEE Transactions on Circuits and Systems I: Regular Papers","volume":"72 7","pages":"3338-3351"},"PeriodicalIF":5.2,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144550650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TCSI.2025.3559711
Hapsah Aulia Azzahra;Muhammad Fakhri Mauludin;Xi Zhu;Jae-Won Nam;Jusung Kim
This paper presents a current-reused coupled oscillator with improved noise circulating technique for phase noise improvement. The proposed current-reused coupled oscillator with order of 2, where the noise circulation oscillator is stacked on top of PMOS cross-coupled oscillator solves the strict trade-off between power consumption and phase noise. The degeneration transistors for noise circulating operations are biased in triode-region instead of in saturation to provide an optimum delay in loop gain, such that the positive and negative phase change in the normalized impulse sensitivity function (ISF) become more symmetric. Thus, the $1/f^{3}$ phase noise is significantly improved. The voltage-controlled oscillator (VCO) was implemented using CMOS 65nm technology, and the measurement results demonstrated its operation within a frequency range of 15.4–17 GHz (9.8% tuning range). Despite its low power dissipation of 6.3 mW, the VCO design exhibits excellent performance, offering a phase noise of −111.2 dBc/Hz at 1 MHz offset frequency. Furthermore, the proposed VCO attains a figure of merit (FoM) of −187.4 dBc/Hz.
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