Pub Date : 2025-07-25DOI: 10.1109/TCPMT.2025.3592829
Aakash Mani;Jahar Sarkar
Thermal shock, leg design, and current profile may also affect the transient performance and reliability of a segmented thermoelectric cooler (STEC), but it has not yet been studied. Hence, this study conducts a detailed 3-D transient analysis of STEC with two distinct leg geometries: square and circular cross sections. Effects of various operational conditions, including pulse current profiles, segment leg ratios, and thermal shock scenarios, on the transient supercooling, coefficient of performance (COP), and thermal stress of STEC are investigated. The results indicate that the quadratic current pulse demonstrated the best cooling performance among the tested current pulse shapes, achieving temperature reductions of 5.3 K for square-leg configuration and 6.1 K for circular-leg configuration compared to the steady-state minimum temperatures at optimal current. Additionally, the analysis highlights the influence of segment leg ratios, with a hot-side to cold-side segment length ratio of 7:3, showing improved thermal performance by achieving reduced cold-side temperature. Under thermal shock conditions, higher power current pulses effectively minimized peak temperature rise while maintaining reasonable thermal stress levels. These findings provide valuable insights into optimizing the design and operation of STECs for hotspot cooling applications, paving the way for developing more efficient and reliable next-generation cooling systems.
{"title":"Transient Thermomechanical Characteristic of Segmented Thermoelectric Cooler for Hotspot Thermal Management","authors":"Aakash Mani;Jahar Sarkar","doi":"10.1109/TCPMT.2025.3592829","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3592829","url":null,"abstract":"Thermal shock, leg design, and current profile may also affect the transient performance and reliability of a segmented thermoelectric cooler (STEC), but it has not yet been studied. Hence, this study conducts a detailed 3-D transient analysis of STEC with two distinct leg geometries: square and circular cross sections. Effects of various operational conditions, including pulse current profiles, segment leg ratios, and thermal shock scenarios, on the transient supercooling, coefficient of performance (COP), and thermal stress of STEC are investigated. The results indicate that the quadratic current pulse demonstrated the best cooling performance among the tested current pulse shapes, achieving temperature reductions of 5.3 K for square-leg configuration and 6.1 K for circular-leg configuration compared to the steady-state minimum temperatures at optimal current. Additionally, the analysis highlights the influence of segment leg ratios, with a hot-side to cold-side segment length ratio of 7:3, showing improved thermal performance by achieving reduced cold-side temperature. Under thermal shock conditions, higher power current pulses effectively minimized peak temperature rise while maintaining reasonable thermal stress levels. These findings provide valuable insights into optimizing the design and operation of STECs for hotspot cooling applications, paving the way for developing more efficient and reliable next-generation cooling systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 12","pages":"2614-2625"},"PeriodicalIF":3.0,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Microwave device design increasingly relies on surrogate modeling to accelerate optimization and reduce costly electromagnetic (EM) simulations. This article presents a spectral Bayesian optimization (SBO) framework leveraging a physics-informed Gaussian process (GP) with a rational complex-valued Szegö kernel and input warping to enhance surrogate accuracy and data efficiency. Unlike conventional methods that model scalar objectives, our approach directly learns the complex-valued frequency response, enforcing causality and Hermitian symmetry. Effectiveness is demonstrated in two cases: a zig-zag microstrip bandpass filter optimized for magnitude response and a passive differential equalizer optimized for both transmission magnitude and group delay. By embedding prior physics and modeling directly in the frequency domain, the method enables accurate, sample-efficient optimization of frequency-dependent behavior. This work shows how physics-informed Bayesian optimization (BO) can significantly improve microwave device design efficiency.
{"title":"Spectral Bayesian Optimization Using a Physics-Informed Rational Szegö Kernel for Microwave Design","authors":"Yens Lindemans;Thijs Ullrick;Ivo Couckuyt;Tim Pattyn;Dirk Deschrijver;Dries Vande Ginste;Tom Dhaene","doi":"10.1109/TCPMT.2025.3592441","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3592441","url":null,"abstract":"Microwave device design increasingly relies on surrogate modeling to accelerate optimization and reduce costly electromagnetic (EM) simulations. This article presents a spectral Bayesian optimization (SBO) framework leveraging a physics-informed Gaussian process (GP) with a rational complex-valued Szegö kernel and input warping to enhance surrogate accuracy and data efficiency. Unlike conventional methods that model scalar objectives, our approach directly learns the complex-valued frequency response, enforcing causality and Hermitian symmetry. Effectiveness is demonstrated in two cases: a zig-zag microstrip bandpass filter optimized for magnitude response and a passive differential equalizer optimized for both transmission magnitude and group delay. By embedding prior physics and modeling directly in the frequency domain, the method enables accurate, sample-efficient optimization of frequency-dependent behavior. This work shows how physics-informed Bayesian optimization (BO) can significantly improve microwave device design efficiency.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1836-1846"},"PeriodicalIF":3.0,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-22DOI: 10.1109/TCPMT.2025.3591501
Yunhui Li;Lihao Liu;Hongwei Xu;Han Diao;Li Shang;Cheng Yang;Zhicheng Ding;Fan Yang
Chiplet-based designs using 2.5-D advanced packaging offer advantages in cost and flexibility over monolithic system-on-chip (SoC), enabling heterogeneous integration. However, the high interconnect density and stringent signaling requirements, particularly under standards like the Universal Chiplet Interconnect Express (UCIe), present significant routing challenges. Traditional routing methods often struggle with the unique constraints and high escape densities of 2.5-D interposers. This article proposes a signal-integrity (SI)-aware integer linear programming (ILP)-based routing method, specifically tailored for 2.5-D heterogeneous chiplet interconnects adhering to the UCIe standard. Our approach features an ILP formulation for simultaneous escape routing (SER) that integrates layer and track assignment while explicitly optimizing for minimal detours and bends to reduce insertion loss, and incorporating a coupling length constraint to directly mitigate crosstalk. A subsequent area routing stage connects the escape points, ensuring design rule compliance. The experimental results on UCIe-compliant benchmarks demonstrate the effectiveness of our method compared to both an open-source router and a commercial router. Our method not only achieves significant improvements in geometric quality, but also exhibits superior SI, validated through voltage transfer function (VTF) analysis. The proposed method provides an efficient, high-quality solution for routing practical 2.5-D chiplet systems.
{"title":"Signal-Integrity-Aware ILP Routing for Practical 2.5-D Chiplet Interconnects","authors":"Yunhui Li;Lihao Liu;Hongwei Xu;Han Diao;Li Shang;Cheng Yang;Zhicheng Ding;Fan Yang","doi":"10.1109/TCPMT.2025.3591501","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3591501","url":null,"abstract":"Chiplet-based designs using 2.5-D advanced packaging offer advantages in cost and flexibility over monolithic system-on-chip (SoC), enabling heterogeneous integration. However, the high interconnect density and stringent signaling requirements, particularly under standards like the Universal Chiplet Interconnect Express (UCIe), present significant routing challenges. Traditional routing methods often struggle with the unique constraints and high escape densities of 2.5-D interposers. This article proposes a signal-integrity (SI)-aware integer linear programming (ILP)-based routing method, specifically tailored for 2.5-D heterogeneous chiplet interconnects adhering to the UCIe standard. Our approach features an ILP formulation for simultaneous escape routing (SER) that integrates layer and track assignment while explicitly optimizing for minimal detours and bends to reduce insertion loss, and incorporating a coupling length constraint to directly mitigate crosstalk. A subsequent area routing stage connects the escape points, ensuring design rule compliance. The experimental results on UCIe-compliant benchmarks demonstrate the effectiveness of our method compared to both an open-source router and a commercial router. Our method not only achieves significant improvements in geometric quality, but also exhibits superior SI, validated through voltage transfer function (VTF) analysis. The proposed method provides an efficient, high-quality solution for routing practical 2.5-D chiplet systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1890-1901"},"PeriodicalIF":3.0,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-21DOI: 10.1109/TCPMT.2025.3590724
Jin Luo;Qianyin Xiang;Quanyuan Feng
The tradeoff between the unloaded quality factor ($Q_{text {u}}$ ) and resonant frequency tunable range of a novel planar integrated switchable and tunable resonator is studied. The novel switchable and tunable resonators are designed based on a quarter-wavelength resonator with a floating strip loaded by a varactor diode and p-i-n diode, and the continuously switchable tuning characteristics of the resonant frequency are modeled and investigated. A reconfigurable bandpass filter (BPF) with continuously tunable frequency and stable bandwidth based on the switchable and tunable resonator with improved $Q_{text {u}}$ is designed, fabricated, and measured. The developed component demonstrates a tuning range of 1.05–2 GHz with a typical bandwidth of 124 MHz and a minimum insertion loss (IL) of 1.8 dB.
{"title":"A Reconfigurable Bandpass Filter Based on Novel Planar Integrated Switchable and Tunable Resonator With Improved Insertion Loss and Frequency Range","authors":"Jin Luo;Qianyin Xiang;Quanyuan Feng","doi":"10.1109/TCPMT.2025.3590724","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3590724","url":null,"abstract":"The tradeoff between the unloaded quality factor (<inline-formula> <tex-math>$Q_{text {u}}$ </tex-math></inline-formula>) and resonant frequency tunable range of a novel planar integrated switchable and tunable resonator is studied. The novel switchable and tunable resonators are designed based on a quarter-wavelength resonator with a floating strip loaded by a varactor diode and p-i-n diode, and the continuously switchable tuning characteristics of the resonant frequency are modeled and investigated. A reconfigurable bandpass filter (BPF) with continuously tunable frequency and stable bandwidth based on the switchable and tunable resonator with improved <inline-formula> <tex-math>$Q_{text {u}}$ </tex-math></inline-formula> is designed, fabricated, and measured. The developed component demonstrates a tuning range of 1.05–2 GHz with a typical bandwidth of 124 MHz and a minimum insertion loss (IL) of 1.8 dB.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"2049-2052"},"PeriodicalIF":3.0,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145073373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-21DOI: 10.1109/TCPMT.2025.3591150
Lei Sang;Hui Tian;Wenlong Bi;Shengjie Zhao;Ping Li;Qiang Chen;Hao Tu
To realize “FPGA-like” microwave components and enhance the reconfiguration ability of microwave links, this article proposes a redefinable microwave component that breaks the limitations of conventional microwave components with single functionality. The redefinable microwave components adopt a “combining tangram” design approach to identify the “greatest common divisor” among several microwave functional structures. The patch + gap structure is used as the multiplex unit, and the RF switches are used to control the current flow direction, forming different electromagnetic distributions, thus achieving dynamic reconfiguration of microwave functions. The resonant performance is adjusted using variable capacitors, enabling the reconfiguration of the performance. The test results of the sample indicate that the microwave passive component can achieve software-defined antenna, filtering, and coupling functions, with adjustable center frequencies for all three functions. Compared with commonly used antenna, filter, or coupler, the performance metrics of the redefinable microwave components have not decreased. Furthermore, the component has also been applied for practical validation in radar systems. The demonstration results show that the redefinable microwave component significantly improves the reconfiguration performance of the microwave link, enabling the microwave system to meet the requirements of multiple application scenarios such as imaging, communication, and distance measurement.
{"title":"A Flexible RF Link Enabled by the Redefinable Microwave Passive Components","authors":"Lei Sang;Hui Tian;Wenlong Bi;Shengjie Zhao;Ping Li;Qiang Chen;Hao Tu","doi":"10.1109/TCPMT.2025.3591150","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3591150","url":null,"abstract":"To realize “FPGA-like” microwave components and enhance the reconfiguration ability of microwave links, this article proposes a redefinable microwave component that breaks the limitations of conventional microwave components with single functionality. The redefinable microwave components adopt a “combining tangram” design approach to identify the “greatest common divisor” among several microwave functional structures. The patch + gap structure is used as the multiplex unit, and the RF switches are used to control the current flow direction, forming different electromagnetic distributions, thus achieving dynamic reconfiguration of microwave functions. The resonant performance is adjusted using variable capacitors, enabling the reconfiguration of the performance. The test results of the sample indicate that the microwave passive component can achieve software-defined antenna, filtering, and coupling functions, with adjustable center frequencies for all three functions. Compared with commonly used antenna, filter, or coupler, the performance metrics of the redefinable microwave components have not decreased. Furthermore, the component has also been applied for practical validation in radar systems. The demonstration results show that the redefinable microwave component significantly improves the reconfiguration performance of the microwave link, enabling the microwave system to meet the requirements of multiple application scenarios such as imaging, communication, and distance measurement.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1973-1985"},"PeriodicalIF":3.0,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-15DOI: 10.1109/TCPMT.2025.3589429
Rahman Sajadi;C. N. Muhammed Ajmal;Bilal Akin
This article presents a comprehensive reliability analysis of TO-263 silicon carbide MOSFETs (SiC MOSFETs) from four different vendors, focusing on gate oxide and package degradation. A range of accelerated aging tests (AATs), including positive high-temperature gate bias (PHTGB), negative high-temperature gate bias (NHTGB), high-temperature reverse bias (HTRB), and dc power cycling (DCPC), are conducted to investigate both gate oxide and package reliability. The findings from HTGB and HTRB tests emphasize that even a 10 nm reduction in gate oxide thickness can significantly impact gate oxide reliability compared to similar designs. Furthermore, the results from NHTGB show that the devices are more prone to failure compared to PHTGB, disproving the idea that the device lifetime is longer in the off-state compared to the on-state. The conclusions are drawn from measurements using focused ion beam (FIB) and transmission electron microscopy (TEM), which provide detailed cross-sectional images of the devices. Additionally, the reliability of the TO-263 package is assessed, highlighting solder fatigue failure between the device and the printed circuit board (PCB) as a significant issue. This failure mechanism can lead to the detachment of the device from the PCB, resulting in a loss of connection. The study underscores the importance of optimizing gate oxide thickness and addressing thermal–mechanical stresses to enhance the overall reliability of SiC MOSFETs with TO-263 packages in high-power applications.
{"title":"Gate Oxide and Package Reliability of TO-263 SiC MOSFETs","authors":"Rahman Sajadi;C. N. Muhammed Ajmal;Bilal Akin","doi":"10.1109/TCPMT.2025.3589429","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3589429","url":null,"abstract":"This article presents a comprehensive reliability analysis of TO-263 silicon carbide MOSFETs (SiC MOSFETs) from four different vendors, focusing on gate oxide and package degradation. A range of accelerated aging tests (AATs), including positive high-temperature gate bias (PHTGB), negative high-temperature gate bias (NHTGB), high-temperature reverse bias (HTRB), and dc power cycling (DCPC), are conducted to investigate both gate oxide and package reliability. The findings from HTGB and HTRB tests emphasize that even a 10 nm reduction in gate oxide thickness can significantly impact gate oxide reliability compared to similar designs. Furthermore, the results from NHTGB show that the devices are more prone to failure compared to PHTGB, disproving the idea that the device lifetime is longer in the off-state compared to the on-state. The conclusions are drawn from measurements using focused ion beam (FIB) and transmission electron microscopy (TEM), which provide detailed cross-sectional images of the devices. Additionally, the reliability of the TO-263 package is assessed, highlighting solder fatigue failure between the device and the printed circuit board (PCB) as a significant issue. This failure mechanism can lead to the detachment of the device from the PCB, resulting in a loss of connection. The study underscores the importance of optimizing gate oxide thickness and addressing thermal–mechanical stresses to enhance the overall reliability of SiC MOSFETs with TO-263 packages in high-power applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1732-1740"},"PeriodicalIF":3.0,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-15DOI: 10.1109/TCPMT.2025.3589029
Yiyang Xu;Kangcheng Wang;Yun-Bo Zhao;Yu Kang;Peng Bai
Functional testing is essential for ensuring the quality of electronic products. As system complexity increases, the cost of functional testing—particularly during the motherboard testing stage—has risen significantly. Designing an efficient testing strategy is therefore key to reducing overall testing costs. Although data imputation methods can enhance the effectiveness of strategies by addressing missing data, current approaches do not adequately account for the impact of correlation information between system modules on the input information of the data imputation model. This oversight results in suboptimal imputation performance, making it challenging to further reduce testing costs. To overcome this limitation, we propose a data imputation method that integrates fault tree analysis (FTA) with eXtreme gradient boosting (XGBoost), effectively combining system fault mode analysis with data-driven modeling. First, faults in nonbus data transmission are additionally considered, and an enhanced fault tree for motherboard testing is constructed. Next, correlations among system modules are quantitatively represented as system event associations within the fault tree, based on which the attributes requiring imputation are determined. Then, a top–down quantitative analysis method driven by both mechanisms and data is introduced to infer the states of basic events from intermediate event states. This mapping from intermediate events to basic events reduces the proportion of missing data. Based on this, missing values are imputed using the tree-based XGBoost model. Experiments conducted on transformed real-world manufacturing data demonstrate that effective testing strategies can be dynamically developed under varying conditions using the proposed method. Testing costs are reduced by up to 5.64% in high-yield scenarios, 6.66% in low-yield scenarios, and 7.07% during long-term yield fluctuations. Furthermore, the defect level is reduced by as much as 51.02%.
{"title":"Low-Cost Functional Testing Based on Data Imputation Integrating Fault Tree Analysis and XGBoost","authors":"Yiyang Xu;Kangcheng Wang;Yun-Bo Zhao;Yu Kang;Peng Bai","doi":"10.1109/TCPMT.2025.3589029","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3589029","url":null,"abstract":"Functional testing is essential for ensuring the quality of electronic products. As system complexity increases, the cost of functional testing—particularly during the motherboard testing stage—has risen significantly. Designing an efficient testing strategy is therefore key to reducing overall testing costs. Although data imputation methods can enhance the effectiveness of strategies by addressing missing data, current approaches do not adequately account for the impact of correlation information between system modules on the input information of the data imputation model. This oversight results in suboptimal imputation performance, making it challenging to further reduce testing costs. To overcome this limitation, we propose a data imputation method that integrates fault tree analysis (FTA) with eXtreme gradient boosting (XGBoost), effectively combining system fault mode analysis with data-driven modeling. First, faults in nonbus data transmission are additionally considered, and an enhanced fault tree for motherboard testing is constructed. Next, correlations among system modules are quantitatively represented as system event associations within the fault tree, based on which the attributes requiring imputation are determined. Then, a top–down quantitative analysis method driven by both mechanisms and data is introduced to infer the states of basic events from intermediate event states. This mapping from intermediate events to basic events reduces the proportion of missing data. Based on this, missing values are imputed using the tree-based XGBoost model. Experiments conducted on transformed real-world manufacturing data demonstrate that effective testing strategies can be dynamically developed under varying conditions using the proposed method. Testing costs are reduced by up to 5.64% in high-yield scenarios, 6.66% in low-yield scenarios, and 7.07% during long-term yield fluctuations. Furthermore, the defect level is reduced by as much as 51.02%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1764-1777"},"PeriodicalIF":3.0,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144892378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Composite right/left-handed transmission line (CRLH TL) concept with metasurface (MS) unit cells is resurfaced to propose planar tunable and miniaturized power divider and phase shifter devices. Fabrication deals with monolayer metal patterning and varactor diodes. Electronic behavior can be modified by varying the dc bias voltages. A planar X-band power splitter with both equal and unequal power dividing properties is presented. Experimental outcomes confirm that it has 140-MHz center frequency tuning capability. It achieved a highest difference in power transfer of 4.5 dB between the two output ports without any notable change in the performance. Another design having resonant frequencies of 8.95 and 10.25 GHz along with varactor diodes is proposed to produce tunable phase shift characteristics. It generates a wide linear phase tuning range of 45° over almost a 2-GHz bandwidth. Both the prototypes allow an easy integration of active devices to attain tunable functionalities.
{"title":"Miniaturized Metasurface-Inspired Tunable Power Divider and Phase Shifter","authors":"Nophadon Wiwatcharagoses;Sambit Kumar Ghosh;Premjeet Chahal","doi":"10.1109/TCPMT.2025.3588044","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3588044","url":null,"abstract":"Composite right/left-handed transmission line (CRLH TL) concept with metasurface (MS) unit cells is resurfaced to propose planar tunable and miniaturized power divider and phase shifter devices. Fabrication deals with monolayer metal patterning and varactor diodes. Electronic behavior can be modified by varying the dc bias voltages. A planar X-band power splitter with both equal and unequal power dividing properties is presented. Experimental outcomes confirm that it has 140-MHz center frequency tuning capability. It achieved a highest difference in power transfer of 4.5 dB between the two output ports without any notable change in the performance. Another design having resonant frequencies of 8.95 and 10.25 GHz along with varactor diodes is proposed to produce tunable phase shift characteristics. It generates a wide linear phase tuning range of 45° over almost a 2-GHz bandwidth. Both the prototypes allow an easy integration of active devices to attain tunable functionalities.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1759-1763"},"PeriodicalIF":3.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-10DOI: 10.1109/TCPMT.2025.3582563
Nick Baker;Francesco Iannuzzo;Szymon Bęczkowski
State-of-the-art power semiconductors use solid metal interconnects such as wire-bonding, soldering, and sintering. Thermo-mechanical stress degrades these solid metal interconnects and is the main cause of failure in power semiconductors. This letter demonstrates the use of liquid-metals (LMs), which are inherently resistant to thermo-mechanical stress, to package a silicon power diode. The manufacturing process is performed below $80~^{circ }$ C. The thermo-mechanical lifetime is assessed through power cycling and is shown to increase by factor of 3.3x in comparison to SAC305 solder and aluminum wirebonded diodes. In addition, the thermal resistance of LM packaged diodes shows a 9% improvement. Corrosion and pump out of the LM is thought to be the failure mode.
{"title":"Liquid Paste Interconnects on a Silicon Power Diode","authors":"Nick Baker;Francesco Iannuzzo;Szymon Bęczkowski","doi":"10.1109/TCPMT.2025.3582563","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3582563","url":null,"abstract":"State-of-the-art power semiconductors use solid metal interconnects such as wire-bonding, soldering, and sintering. Thermo-mechanical stress degrades these solid metal interconnects and is the main cause of failure in power semiconductors. This letter demonstrates the use of liquid-metals (LMs), which are inherently resistant to thermo-mechanical stress, to package a silicon power diode. The manufacturing process is performed below <inline-formula> <tex-math>$80~^{circ }$ </tex-math></inline-formula>C. The thermo-mechanical lifetime is assessed through power cycling and is shown to increase by factor of 3.3x in comparison to SAC305 solder and aluminum wirebonded diodes. In addition, the thermal resistance of LM packaged diodes shows a 9% improvement. Corrosion and pump out of the LM is thought to be the failure mode.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1661-1665"},"PeriodicalIF":3.0,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144896806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-10DOI: 10.1109/TCPMT.2025.3587609
Zhonghao Zhang;Paul K. Jo;Shane Oh;Muhannad S. Bakir
This work presents a novel direct die-to-die (D2D) interconnect approach utilizing fused-silica stitch-chip technology to integrate heterogeneous commercial off-the-shelf (COTS) chiplets without the need for die embedding. This study evaluates RF performance through simulations and experimental measurements, comparing the stitch-chip interconnect against both wire-bond and other interconnect technologies. In addition, this study analyzes the impact of die embedding within a cavity on its performance. A heterogeneous integration of a low-noise amplifier (LNA) die (GaAs) and a switch die (AlGaAs), both designed for K-/Ka-band applications, is demonstrated using stitch-chip technology. RF characterization results verify that the bare LNA die maintains strong performance, achieving greater than 12-dB return loss (RL). The integrated LNA-switch module achieves a 20-dB linear gain up to 38 GHz, with the D2D stitch-chip interconnect showing a 4-dB improvement in gain compared to the die-to-package-to-die (D2P2D) approach and an 8.5-dB increase in gain compared to wire-bond connections. The results demonstrate that the proposed stitch-chip technology effectively minimizes insertion loss (IL), improves impedance matching, and enhances RF signal integrity, positioning it as an up-and-coming solution for future heterogeneous RF/mm-wave multichip integration applications.
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