Pub Date : 2024-08-22DOI: 10.1109/TCPMT.2024.3447650
Xinyu Zhang;Jun Li;Chenglin Yang;Tiancheng Liang;Wenwen Zhang;Yang Yang
This article presents a broadband dual-polarization antenna-in-package (AiP) design for 5G millimeter-wave user equipment. The magnetoelectric (ME) antenna is adopted to achieve dual polarization and broadband. We introduce a tapered feeding probe to enhance the antenna’s dual-polarization isolation and optimize the impedance matching between the feeding network and the radiating patch to achieve high gain throughout the entire operating bandwidth. Based on the antenna element, we design a $1times 4$ antenna array with the dimensions of $20times 5times 1.1$ mm3. The impedance bandwidth of both polarizations of the array falls within 26.8–42.7 GHz, covering the majority of the 5G new radio (NR) bands. The gain range for horizontal polarization within this band is 9.87–12.5 dBi, while that for vertical polarization is 10.67–12.51 dBi. The antenna array can achieve the beam-scanning angles of 50° and 30° in the FR2 n257 and n260 frequency bands, respectively. The AiP is manufactured and tested using the flip-chip ball grid array (FCBGA) process on an organic substrate, with the test results closely aligning with simulation outcomes. The proposed AiP covers 5G millimeter-wave n257, n259, n260, and n261 bands and a significant portion of n258 (24.25–27.5 GHz) while guaranteeing high dual-polarization isolation and considerable gain, thus making it suitable for application in 5G millimeter-wave user equipment.
{"title":"A Wideband Dual-Polarized Antenna-in-Package for 5G Millimeter-Wave User Equipment","authors":"Xinyu Zhang;Jun Li;Chenglin Yang;Tiancheng Liang;Wenwen Zhang;Yang Yang","doi":"10.1109/TCPMT.2024.3447650","DOIUrl":"10.1109/TCPMT.2024.3447650","url":null,"abstract":"This article presents a broadband dual-polarization antenna-in-package (AiP) design for 5G millimeter-wave user equipment. The magnetoelectric (ME) antenna is adopted to achieve dual polarization and broadband. We introduce a tapered feeding probe to enhance the antenna’s dual-polarization isolation and optimize the impedance matching between the feeding network and the radiating patch to achieve high gain throughout the entire operating bandwidth. Based on the antenna element, we design a \u0000<inline-formula> <tex-math>$1times 4$ </tex-math></inline-formula>\u0000 antenna array with the dimensions of \u0000<inline-formula> <tex-math>$20times 5times 1.1$ </tex-math></inline-formula>\u0000 mm3. The impedance bandwidth of both polarizations of the array falls within 26.8–42.7 GHz, covering the majority of the 5G new radio (NR) bands. The gain range for horizontal polarization within this band is 9.87–12.5 dBi, while that for vertical polarization is 10.67–12.51 dBi. The antenna array can achieve the beam-scanning angles of 50° and 30° in the FR2 n257 and n260 frequency bands, respectively. The AiP is manufactured and tested using the flip-chip ball grid array (FCBGA) process on an organic substrate, with the test results closely aligning with simulation outcomes. The proposed AiP covers 5G millimeter-wave n257, n259, n260, and n261 bands and a significant portion of n258 (24.25–27.5 GHz) while guaranteeing high dual-polarization isolation and considerable gain, thus making it suitable for application in 5G millimeter-wave user equipment.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1845-1853"},"PeriodicalIF":2.3,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/TCPMT.2024.3447040
Fei Liu;Heng Wang;Pingfa Feng;Long Zeng
Defects can be regarded as targets when using a target detection algorithm. Compared with conventional targets, chip defects have distinct characteristics. Their sizes are variable, and most defects are small in size. Defects lack texture features and can be viewed as anomalies relative to the background. Some defects exhibit elongated and strip-like characteristics, making the direct application of existing target detection algorithms less than ideal. In this article, we incorporate these characteristics as prior knowledge in the design and improvement of the target detection network structure. We propose a deep learning detection network, you only look once—with defect attention (YOLO-WDA), specifically tailored for chip defect data, using three targeted improvement methods. An anomaly attention mechanism (AAM) highlights defect features by contrasting information with normal chips. An improved module for small target defects uses the focus operation to retain more fine-grained information, combined with ghost convolution to adjust the channel redundancy and reduce network parameters. An Ameba convolution detection (AMBC-Detect) head can better capture continuous features such as curves. In experiments conducted on two chip datasets, YOLO-WDA achieved mean of average precision (mAP) scores of 65.5 and 43.2, outperforming the benchmark model, YOLOv8, by 2.7 and 4.8, respectively. Our model also outperforms other classical algorithms. Datasets are available at: https://pan.baidu.com/s/1vU3hkPUYSrzVHDKgGgt1MA?pwd=1 yja
{"title":"Integrated Circuit Packaging Defect Analysis and Deep Learning Detection Method","authors":"Fei Liu;Heng Wang;Pingfa Feng;Long Zeng","doi":"10.1109/TCPMT.2024.3447040","DOIUrl":"10.1109/TCPMT.2024.3447040","url":null,"abstract":"Defects can be regarded as targets when using a target detection algorithm. Compared with conventional targets, chip defects have distinct characteristics. Their sizes are variable, and most defects are small in size. Defects lack texture features and can be viewed as anomalies relative to the background. Some defects exhibit elongated and strip-like characteristics, making the direct application of existing target detection algorithms less than ideal. In this article, we incorporate these characteristics as prior knowledge in the design and improvement of the target detection network structure. We propose a deep learning detection network, you only look once—with defect attention (YOLO-WDA), specifically tailored for chip defect data, using three targeted improvement methods. An anomaly attention mechanism (AAM) highlights defect features by contrasting information with normal chips. An improved module for small target defects uses the focus operation to retain more fine-grained information, combined with ghost convolution to adjust the channel redundancy and reduce network parameters. An Ameba convolution detection (AMBC-Detect) head can better capture continuous features such as curves. In experiments conducted on two chip datasets, YOLO-WDA achieved mean of average precision (mAP) scores of 65.5 and 43.2, outperforming the benchmark model, YOLOv8, by 2.7 and 4.8, respectively. Our model also outperforms other classical algorithms. Datasets are available at: \u0000<uri>https://pan.baidu.com/s/1vU3hkPUYSrzVHDKgGgt1MA?pwd=1</uri>\u0000 yja","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1707-1719"},"PeriodicalIF":2.3,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/TCPMT.2024.3447079
Meiyu Wang;Peng Gao;Fangmin Shi;Weibo Hu;Xudong Wang;Haidong Yan;Yunhui Mei
The gallium-nitride (GaN) high-electron-mobility transistors (HEMT) devices have great potential for high-power, high-temperature, and high-frequency applications. However, it is challenging to package GaN HEMT power module with both low parasitic inductance and thermal resistance because the lateral GaN HEMT devices have fast switching speed, high heat flux density, and small die size. This article made a comprehensive review on the state-of-the-art packaging technologies of GaN HEMT power modules based on different substrate integration structures, including printed circuit board (PCB) surface mounting, wire-bonded flip chip, PCB-embedded, ceramic-substrate integrated, insulated metal substrate (IMS) integrated, and hybrid PCB-on-direct bond copper (DBC) packaging. Each technology has a tradeoff among parasitic inductance, thermal performance, and manufacturability. Innovations are still necessary for packaging GaN HEMT modules for their applications in high-frequency and high-power-density converters.
氮化镓（GaN）高电子迁移率晶体管（HEMT）器件在大功率、高温和高频应用方面具有巨大潜力。然而，由于侧向 GaN HEMT 器件具有开关速度快、热通量密度高和芯片尺寸小等特点，因此封装具有低寄生电感和热阻的 GaN HEMT 功率模块是一项挑战。本文全面综述了基于不同基板集成结构的 GaN HEMT 功率模块的最新封装技术，包括印刷电路板（PCB）表面贴装、线键合倒装芯片、PCB 嵌入、陶瓷基板集成、绝缘金属基板（IMS）集成以及 PCB 直接键合铜（DBC）混合封装。每种技术都需要在寄生电感、热性能和可制造性之间进行权衡。为了将 GaN HEMT 模块应用于高频和高功率密度转换器，封装技术仍需创新。
{"title":"Advanced Packaging Technology of GaN HEMT Module for High-Power and High-Frequency Applications: A Review","authors":"Meiyu Wang;Peng Gao;Fangmin Shi;Weibo Hu;Xudong Wang;Haidong Yan;Yunhui Mei","doi":"10.1109/TCPMT.2024.3447079","DOIUrl":"10.1109/TCPMT.2024.3447079","url":null,"abstract":"The gallium-nitride (GaN) high-electron-mobility transistors (HEMT) devices have great potential for high-power, high-temperature, and high-frequency applications. However, it is challenging to package GaN HEMT power module with both low parasitic inductance and thermal resistance because the lateral GaN HEMT devices have fast switching speed, high heat flux density, and small die size. This article made a comprehensive review on the state-of-the-art packaging technologies of GaN HEMT power modules based on different substrate integration structures, including printed circuit board (PCB) surface mounting, wire-bonded flip chip, PCB-embedded, ceramic-substrate integrated, insulated metal substrate (IMS) integrated, and hybrid PCB-on-direct bond copper (DBC) packaging. Each technology has a tradeoff among parasitic inductance, thermal performance, and manufacturability. Innovations are still necessary for packaging GaN HEMT modules for their applications in high-frequency and high-power-density converters.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1537-1550"},"PeriodicalIF":2.3,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/TCPMT.2024.3446590
Ahmed Issa Alnahhal;Balázs Plesz
This article demonstrates the effect of spectrum splitting of the solar spectrum on the output performance of the combined system for low concentration levels. The full spectrum has been split into two parts, the postbandgap spectrum (PBS) with a range of 1100–4000 nm is transferred to the thermoelectric device, and the within-bandgap spectrum with a range of 350–1100 nm is further split into two smaller partitions and divided between the solar cell and thermoelectric generator (TEG). The calculations were performed for 15 configurations, where the splitting wavelength was increased in steps of 50 nm. The results showed that splitting the spectrum decreases the thermal load of the solar cell reducing its temperature, while the TEG device can compensate for the decrease of the solar cell power caused by the reduction of the spectral range transferred to the solar cell. At higher solar concentration levels, the optimal splitting wavelength increases, meaning that the optimal spectral distribution between TEG and photovoltaic (PV) is shifted toward the TEG device as light concentration levels and power densities increase. It was also verified that with increasing light concentration the spectrum-splitting combined system shows a growing efficiency advantage compared with standalone PV cells. This is explained on one hand by the temperature reduction of the PV cells, and on the other by the higher power contribution of the TEG device.
{"title":"Spectrum Splitting-Based Performance of Combined Photovoltaic Thermoelectric Generator System","authors":"Ahmed Issa Alnahhal;Balázs Plesz","doi":"10.1109/TCPMT.2024.3446590","DOIUrl":"10.1109/TCPMT.2024.3446590","url":null,"abstract":"This article demonstrates the effect of spectrum splitting of the solar spectrum on the output performance of the combined system for low concentration levels. The full spectrum has been split into two parts, the postbandgap spectrum (PBS) with a range of 1100–4000 nm is transferred to the thermoelectric device, and the within-bandgap spectrum with a range of 350–1100 nm is further split into two smaller partitions and divided between the solar cell and thermoelectric generator (TEG). The calculations were performed for 15 configurations, where the splitting wavelength was increased in steps of 50 nm. The results showed that splitting the spectrum decreases the thermal load of the solar cell reducing its temperature, while the TEG device can compensate for the decrease of the solar cell power caused by the reduction of the spectral range transferred to the solar cell. At higher solar concentration levels, the optimal splitting wavelength increases, meaning that the optimal spectral distribution between TEG and photovoltaic (PV) is shifted toward the TEG device as light concentration levels and power densities increase. It was also verified that with increasing light concentration the spectrum-splitting combined system shows a growing efficiency advantage compared with standalone PV cells. This is explained on one hand by the temperature reduction of the PV cells, and on the other by the higher power contribution of the TEG device.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1560-1567"},"PeriodicalIF":2.3,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the semiconductor industry, especially in the manufacturing of through-glass vias (TGVs), there is an increasing need to improve the quality and efficiency of manufacturing processes. To address the challenges such as lack of efficiency, requiring substantial manual labor, and falling short in precision of traditional methods in meeting high standards for TGV manufacturing, the approach that combines deep learning and optimization techniques was introduced to achieve automatic quality assessment and refine laser drilling parameters for TGVs manufacturing. We have developed a residual U-Net model with an accuracy of up to 87.9% by training high-resolution scanning electron microscope (SEM) images of TGVs for automatic assessment of TGVs quality, closely matching the assessments made by human experts. We used Bayesian optimization to iteratively adjust the laser drilling parameters that are crucial for TGVs manufacturing, and the quality scores obtained by the residual U-Net model enhanced by 13.2% after 50 iterations, which confirms the effectiveness of the integration of U-Net architecture with Bayesian optimization in achieving optimal manufacturing results.
在半导体行业，尤其是在玻璃通孔（TGV）的制造过程中，对提高制造过程的质量和效率的需求与日俱增。针对 TGV 制造过程中存在的效率低下、需要大量人工、传统方法精度不高等问题，我们引入了深度学习和优化技术相结合的方法，以实现自动质量评估，并完善 TGV 制造过程中的激光钻孔参数。我们通过训练 TGV 的高分辨率扫描电子显微镜（SEM）图像，开发了一个残差 U-Net 模型，用于自动评估 TGV 的质量，准确率高达 87.9%，与人类专家的评估结果非常接近。我们使用贝叶斯优化方法迭代调整对 TGV 制造至关重要的激光钻孔参数，经过 50 次迭代后，残余 U-Net 模型获得的质量分数提高了 13.2%，这证实了 U-Net 架构与贝叶斯优化方法的整合在实现最佳制造结果方面的有效性。
{"title":"Parameter Optimization of Laser Drilling for Through-Glass Vias Based on Deep Learning and Bayesian Algorithm","authors":"Yuhang Ouyang;Dongyang Hou;Ting Lv;Fang Dong;Sheng Liu;Jianhui Zhao","doi":"10.1109/TCPMT.2024.3446510","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3446510","url":null,"abstract":"In the semiconductor industry, especially in the manufacturing of through-glass vias (TGVs), there is an increasing need to improve the quality and efficiency of manufacturing processes. To address the challenges such as lack of efficiency, requiring substantial manual labor, and falling short in precision of traditional methods in meeting high standards for TGV manufacturing, the approach that combines deep learning and optimization techniques was introduced to achieve automatic quality assessment and refine laser drilling parameters for TGVs manufacturing. We have developed a residual U-Net model with an accuracy of up to 87.9% by training high-resolution scanning electron microscope (SEM) images of TGVs for automatic assessment of TGVs quality, closely matching the assessments made by human experts. We used Bayesian optimization to iteratively adjust the laser drilling parameters that are crucial for TGVs manufacturing, and the quality scores obtained by the residual U-Net model enhanced by 13.2% after 50 iterations, which confirms the effectiveness of the integration of U-Net architecture with Bayesian optimization in achieving optimal manufacturing results.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1680-1691"},"PeriodicalIF":2.3,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142551994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current research on the transmission characteristics of through silicon via-redistribution layer (TSV-RDL) interconnects is basically limited to the single-pair interconnect (a device with two TSVs connected by an RDL line is referred to as one-pair), which is obviously insufficient for highly integrated 3-D packaging. Thus, this article aims to simulate the actual long-chain interconnects by establishing an equivalent circuit model of multipair TSV-RDL interconnects in order to explore their transmission characteristics. First, the equivalent circuit model of long-chain ground-signal-ground type (GSG-type) TSV-RDL interconnects is established based on the correlation between single-pair and multipair interconnects. Second, the transmission performance of long-chain interconnects is investigated by analyzing the reasons for the differences in insertion loss of various length test vehicles in the frequency band from 0.01 to 40 GHz. Compared to RDL lines, TSVs have a greater impact on the overall loss. The resistance of interconnects and the capacitance of the insulating layer at low frequency, the capacitance and conductance associated with the conductive substrate in the mid-frequency range, as well as the inductance in the high-frequency region all play pivotal roles in impedance changes in their respective domains. Finally, the above analysis points out the optimization of the long-chain interconnect by increasing its length while avoiding excessive inductance due to RDL lines in order to reduce the use of TSVs and thus improve the overall transmission performance.
{"title":"Transmission Characteristics of Long-Chain Through Silicon Via-Redistribution Layer Interconnects","authors":"Xiaoting Chen;Xiaodong Jian;Hongyue Wang;Xiangjun Lu;Yiming Zhang;Xiangxiang Zhong;Bin Zhou","doi":"10.1109/TCPMT.2024.3445345","DOIUrl":"10.1109/TCPMT.2024.3445345","url":null,"abstract":"Current research on the transmission characteristics of through silicon via-redistribution layer (TSV-RDL) interconnects is basically limited to the single-pair interconnect (a device with two TSVs connected by an RDL line is referred to as one-pair), which is obviously insufficient for highly integrated 3-D packaging. Thus, this article aims to simulate the actual long-chain interconnects by establishing an equivalent circuit model of multipair TSV-RDL interconnects in order to explore their transmission characteristics. First, the equivalent circuit model of long-chain ground-signal-ground type (GSG-type) TSV-RDL interconnects is established based on the correlation between single-pair and multipair interconnects. Second, the transmission performance of long-chain interconnects is investigated by analyzing the reasons for the differences in insertion loss of various length test vehicles in the frequency band from 0.01 to 40 GHz. Compared to RDL lines, TSVs have a greater impact on the overall loss. The resistance of interconnects and the capacitance of the insulating layer at low frequency, the capacitance and conductance associated with the conductive substrate in the mid-frequency range, as well as the inductance in the high-frequency region all play pivotal roles in impedance changes in their respective domains. Finally, the above analysis points out the optimization of the long-chain interconnect by increasing its length while avoiding excessive inductance due to RDL lines in order to reduce the use of TSVs and thus improve the overall transmission performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1620-1629"},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rapid advancement of electronic information, electronic components are increasingly trending toward miniaturization and high-density. Reflow soldering has emerged as the predominant method for soldering, but its quality is susceptible to various influencing factors. This study focuses on investigating the reflow soldering process of ceramic ball grid array (CBGA) devices by integrating the Anand constitutive model of solder joints, with the solder joint material being Sn63Pb37. A transient thermodynamic coupling model for the reflow soldering process is established, and the thermal simulation parameters are calibrated through temperature testing. The results indicate that the deviation between simulation and experimental outcomes is below 5%. Furthermore, a comparison of the Anand model and elastic model’s impact on solder joint warping and residual stress reveals that the Anand model yields more precise simulation results. Subsequently, the soldering quality of reflow soldering is analyzed based on Anand model, and the key parameters influencing soldering quality are identified through orthogonal analysis, providing a basis for optimal design. The findings suggest that the temperature of the ninth temperature zone and air supply rate exert the most significant influence on soldering quality. In comparison to the initial temperature curve and the airflow rate, there is a $21~^{circ }$ C increase in peak temperature, a 20-s prolongation of liquid phase time, a reduction of residual stress by 0.15 MPa, and an increase in printed circuit board (PCB) warping by 0.04 mm.
{"title":"The Transient Thermal Coupling of CBGA Solder Joints in Reflow Soldering: Experimental and Numerical Optimization","authors":"Hang-Bo Shi;Wei-Xuan Guo;Min Liu;Kui Li;Yi-Long Chen;Zhi-Xiang Zhang;Tian-Tian Shao","doi":"10.1109/TCPMT.2024.3445963","DOIUrl":"10.1109/TCPMT.2024.3445963","url":null,"abstract":"With the rapid advancement of electronic information, electronic components are increasingly trending toward miniaturization and high-density. Reflow soldering has emerged as the predominant method for soldering, but its quality is susceptible to various influencing factors. This study focuses on investigating the reflow soldering process of ceramic ball grid array (CBGA) devices by integrating the Anand constitutive model of solder joints, with the solder joint material being Sn63Pb37. A transient thermodynamic coupling model for the reflow soldering process is established, and the thermal simulation parameters are calibrated through temperature testing. The results indicate that the deviation between simulation and experimental outcomes is below 5%. Furthermore, a comparison of the Anand model and elastic model’s impact on solder joint warping and residual stress reveals that the Anand model yields more precise simulation results. Subsequently, the soldering quality of reflow soldering is analyzed based on Anand model, and the key parameters influencing soldering quality are identified through orthogonal analysis, providing a basis for optimal design. The findings suggest that the temperature of the ninth temperature zone and air supply rate exert the most significant influence on soldering quality. In comparison to the initial temperature curve and the airflow rate, there is a \u0000<inline-formula> <tex-math>$21~^{circ }$ </tex-math></inline-formula>\u0000C increase in peak temperature, a 20-s prolongation of liquid phase time, a reduction of residual stress by 0.15 MPa, and an increase in printed circuit board (PCB) warping by 0.04 mm.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1670-1679"},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-16DOI: 10.1109/TCPMT.2024.3443858
Chengyi Liao;Huimin He;Fengman Liu;Xugang Wang;Rui Cao;Lijun Chen;Cheng Peng;Liqiang Cao;Qingdong Wang
The development of semiconductors, driven by artificial intelligence (AI) and fifth-generation technology (5G) technologies, has posed challenges in advanced packaging. To address these challenges, a 3-D packaging architecture based on active interposers has emerged. This article presents a novel fabrication method of the active interposer with high-aspect-ratio through-silicon vias (TSVs) and a reliable assembly process of 3-D chiplets. The proposed fabrication method of active interposer adopts frontside via-last TSV technology. First, a two-step protection method etching is implemented to address low-dielectric constant (DK) (low-k) material overetching risks. Then, baking at 350 °C after TSV etching is suggested to prevent short circuits. Last, a blade saw followed by laser scribing is proposed to mitigate die chipping during the dicing saw of low-k material. In addition, the 3-D chiplet assembly process is optimized for low thickness, large-area active interposer-to-substrate and high-density-I/O die-to-die bonding. Optimized recipe of thermal compression bonding (TCB), along with solder on pad (SoP), modified under-bump metallization (UBM), and novel flux transfer method, ensures high-quality solder joints without voids or bridging. The validity of the optimized assembly process is confirmed by reliability tests. The successfully integrated 3-D chiplets demonstrate that the fabrication process of the active interposer and the optimized assembly flow can enhance the performance and reliability of 3-D chiplet packaging in various applications.
{"title":"Enhanced Fabrication and Assembly of 3-D Chiplets Based on Active Interposer With Frontside Via-Last TSVs","authors":"Chengyi Liao;Huimin He;Fengman Liu;Xugang Wang;Rui Cao;Lijun Chen;Cheng Peng;Liqiang Cao;Qingdong Wang","doi":"10.1109/TCPMT.2024.3443858","DOIUrl":"10.1109/TCPMT.2024.3443858","url":null,"abstract":"The development of semiconductors, driven by artificial intelligence (AI) and fifth-generation technology (5G) technologies, has posed challenges in advanced packaging. To address these challenges, a 3-D packaging architecture based on active interposers has emerged. This article presents a novel fabrication method of the active interposer with high-aspect-ratio through-silicon vias (TSVs) and a reliable assembly process of 3-D chiplets. The proposed fabrication method of active interposer adopts frontside via-last TSV technology. First, a two-step protection method etching is implemented to address low-dielectric constant (DK) (low-k) material overetching risks. Then, baking at 350 °C after TSV etching is suggested to prevent short circuits. Last, a blade saw followed by laser scribing is proposed to mitigate die chipping during the dicing saw of low-k material. In addition, the 3-D chiplet assembly process is optimized for low thickness, large-area active interposer-to-substrate and high-density-I/O die-to-die bonding. Optimized recipe of thermal compression bonding (TCB), along with solder on pad (SoP), modified under-bump metallization (UBM), and novel flux transfer method, ensures high-quality solder joints without voids or bridging. The validity of the optimized assembly process is confirmed by reliability tests. The successfully integrated 3-D chiplets demonstrate that the fabrication process of the active interposer and the optimized assembly flow can enhance the performance and reliability of 3-D chiplet packaging in various applications.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1692-1700"},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1109/tcpmt.2024.3443530
Henry A. Martin, Dong Hu, Xu Liu, René H. Poelma, Edsger C. P. Smits, Willem D. Van Driel, GuoQi Zhang
{"title":"Prognostic Monitoring of Power QFN Packages with Silver Sintered Die-Attach Materials","authors":"Henry A. Martin, Dong Hu, Xu Liu, René H. Poelma, Edsger C. P. Smits, Willem D. Van Driel, GuoQi Zhang","doi":"10.1109/tcpmt.2024.3443530","DOIUrl":"https://doi.org/10.1109/tcpmt.2024.3443530","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"285 1","pages":""},"PeriodicalIF":2.2,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1109/TCPMT.2024.3443599
Zhibo Cao;Jens Lehmann;Bruno Heusdens;Emre Can Durmaz;Patrick Krüger;Matthias Wietstruck;Norbert Herfurth;Awwal Adeniyi Adesunkanmi;Corrado Carta;Mehmet Kaynak
This article conducts a comprehensive investigation of the assembly technologies of a Cu pillar-based multichip flip-chip package with low-cost PCB substrates. Such a package is considered as a cost-effective solution for mm-wave broadband applications below 60 GHz. Three main trend flip-chip assembly methods are compared: mass reflow soldering, Cu pillar thermocompression soldering, and Au-Cu thermocompression bonding (TCB). Within these three assembly approaches, both the samples used for assembly and the assembly conditions are systematically compared. Specifically, Cu pillars with and without solder caps, PCB substrates with different solder mask thicknesses, PCB substrates with different glass transition temperatures, and different bonding compression forces are carried out in different assembly approaches. After the assembly, the assembly yield and contact resistance per bump are examined by meander daisy chain resistance measurement and the bonding qualities of both the whole chip and individual bumps are inspected using shear testing and cross sectioning. Findings reveal that reflow soldering offers advantages for high-volume, cost-effective assemblies despite a slightly lower yield, and the Au-Cu TCB exhibits a very high yield with diminished throughput. Whereas, Cu pillar thermocompression soldering does not manifest advantages over the other two approaches. This meticulous investigation enhances the accessibility of the discussed packaging approach, contributing to the groundwork for future technological advancements in this domain.
{"title":"The Assembly Investigation of a Multichip to PCB Flip-Chip Package Using Cu Pillar Bumps","authors":"Zhibo Cao;Jens Lehmann;Bruno Heusdens;Emre Can Durmaz;Patrick Krüger;Matthias Wietstruck;Norbert Herfurth;Awwal Adeniyi Adesunkanmi;Corrado Carta;Mehmet Kaynak","doi":"10.1109/TCPMT.2024.3443599","DOIUrl":"10.1109/TCPMT.2024.3443599","url":null,"abstract":"This article conducts a comprehensive investigation of the assembly technologies of a Cu pillar-based multichip flip-chip package with low-cost PCB substrates. Such a package is considered as a cost-effective solution for mm-wave broadband applications below 60 GHz. Three main trend flip-chip assembly methods are compared: mass reflow soldering, Cu pillar thermocompression soldering, and Au-Cu thermocompression bonding (TCB). Within these three assembly approaches, both the samples used for assembly and the assembly conditions are systematically compared. Specifically, Cu pillars with and without solder caps, PCB substrates with different solder mask thicknesses, PCB substrates with different glass transition temperatures, and different bonding compression forces are carried out in different assembly approaches. After the assembly, the assembly yield and contact resistance per bump are examined by meander daisy chain resistance measurement and the bonding qualities of both the whole chip and individual bumps are inspected using shear testing and cross sectioning. Findings reveal that reflow soldering offers advantages for high-volume, cost-effective assemblies despite a slightly lower yield, and the Au-Cu TCB exhibits a very high yield with diminished throughput. Whereas, Cu pillar thermocompression soldering does not manifest advantages over the other two approaches. This meticulous investigation enhances the accessibility of the discussed packaging approach, contributing to the groundwork for future technological advancements in this domain.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1661-1669"},"PeriodicalIF":2.3,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：