{"title":"Modeling and Analysis of Parasitic Parameters of Through-Glass Vias with Various Tapers and Sidewall Roughness","authors":"Zhen Fang, Jihua Zhang, Shuqi Li, Jinxu Liu, Libin Gao, Hongwei Chen, Xingzhou Cai, Wanli Zhang","doi":"10.1109/tcpmt.2024.3452103","DOIUrl":"https://doi.org/10.1109/tcpmt.2024.3452103","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"5 1","pages":""},"PeriodicalIF":2.2,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-30DOI: 10.1109/TCPMT.2024.3452637
Euichul Chung;Geyu Yan;Shane Oh;Bharath Ramakrishnan;Husam Alissa;Vaidehi Oruganti;Christian Belady;Muhannad S. Bakir
The electrical-thermal characteristics of microfluidic cooled 3-D-integrated circuits (3D-ICs) accounting for thermal metrics, including thermal resistance and pressure drop, and electrical metrics, including signal delay and bandwidth density, are investigated in this article. The parametric design exploration of various through-silicon via (TSV)-integrated microfluidic pin-fin heat sinks is modeled using computational fluid dynamics (CFD) and SPICE simulation. The co-integration of micropin-fin and TSVs forms a design interdependence, leading to a tradeoff between electrical and thermal performance. Owing to the complex relationship between electrical and thermal metrics, we explore optimal 3D-IC design solutions using the Technique for Order Preference by Similarity to Ideal Solution (TOPSIS), a multicriteria decision method to determine the optimized TSV-integrated microfluidic heat sink design with different degrees of weights assigned to thermal and electrical considerations.
{"title":"Electrical–Thermal Co-Analysis of Through-Silicon Vias (TSVs) Integrated Within Micropin-Fin Heatsink for 3-D Heterogeneous Integration (HI)","authors":"Euichul Chung;Geyu Yan;Shane Oh;Bharath Ramakrishnan;Husam Alissa;Vaidehi Oruganti;Christian Belady;Muhannad S. Bakir","doi":"10.1109/TCPMT.2024.3452637","DOIUrl":"10.1109/TCPMT.2024.3452637","url":null,"abstract":"The electrical-thermal characteristics of microfluidic cooled 3-D-integrated circuits (3D-ICs) accounting for thermal metrics, including thermal resistance and pressure drop, and electrical metrics, including signal delay and bandwidth density, are investigated in this article. The parametric design exploration of various through-silicon via (TSV)-integrated microfluidic pin-fin heat sinks is modeled using computational fluid dynamics (CFD) and SPICE simulation. The co-integration of micropin-fin and TSVs forms a design interdependence, leading to a tradeoff between electrical and thermal performance. Owing to the complex relationship between electrical and thermal metrics, we explore optimal 3D-IC design solutions using the Technique for Order Preference by Similarity to Ideal Solution (TOPSIS), a multicriteria decision method to determine the optimized TSV-integrated microfluidic heat sink design with different degrees of weights assigned to thermal and electrical considerations.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1792-1802"},"PeriodicalIF":2.3,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-30DOI: 10.1109/TCPMT.2024.3452484
Priyanka Borkar;Vijay S. Duryodhan
The performance of a phase change material (PCM)-based hybrid heat sink is evaluated using a transient, 3-D numerical study. PCM is used in a passive cooling method to dissipate the heat, whereas liquid flowthrough microchannels is employed as active cooling to resolidify the PCM. Passive and active cooling modes operate periodically, governed by various operating temperatures. Simulations are performed by varying aspect ratio (AR) of the microchannel (AR = 1 and 3) and fin spacing/PCM volume ( $S = 1$ , 2, 4) for the range of Reynolds number (Re = 497, 995, 1492) and supplied heat flux ( $q'' = 50$ , 100, 150 kW/m2). Transient variations of junction temperature, PCM liquid fraction, and energy consumption are recorded and analyzed in detail for all the cases studied. The objective is to identify the parameters leading to less active cooling time than passive cooling. The numerical results show that the frequency and amplitude of periodic temperature variation owing to passive-active–passive cooling are a function of Reynolds number, heat flux, PCM volume, and AR of microchannels. The time of active cooling and the quantity of resolidified PCM vary inversely with the Reynolds number. Furthermore, an increase in AR was observed to have a favorable effect on improving the performance of PCM-based hybrid heat sink. For the range of parameters studied in this work, it is observed that around 22%–89% less energy is consumed by a hybrid heat sink if a microchannel of AR 3 is used compared to that of 1. The quantity of PCM plays a vital role in the performance of hybrid heat sinks; therefore, a fin spacing of 1 mm works better than that of 2 and 4 mm. The proposed concept of a hybrid heat sink will help reduce the dependency on an active cooling system for miniaturized electronic devices.
{"title":"Study of Phase Change Material-Based Hybrid Heat Sink for Electronics Cooling Application","authors":"Priyanka Borkar;Vijay S. Duryodhan","doi":"10.1109/TCPMT.2024.3452484","DOIUrl":"10.1109/TCPMT.2024.3452484","url":null,"abstract":"The performance of a phase change material (PCM)-based hybrid heat sink is evaluated using a transient, 3-D numerical study. PCM is used in a passive cooling method to dissipate the heat, whereas liquid flowthrough microchannels is employed as active cooling to resolidify the PCM. Passive and active cooling modes operate periodically, governed by various operating temperatures. Simulations are performed by varying aspect ratio (AR) of the microchannel (AR = 1 and 3) and fin spacing/PCM volume (\u0000<inline-formula> <tex-math>$S = 1$ </tex-math></inline-formula>\u0000, 2, 4) for the range of Reynolds number (Re = 497, 995, 1492) and supplied heat flux (\u0000<inline-formula> <tex-math>$q'' = 50$ </tex-math></inline-formula>\u0000, 100, 150 kW/m2). Transient variations of junction temperature, PCM liquid fraction, and energy consumption are recorded and analyzed in detail for all the cases studied. The objective is to identify the parameters leading to less active cooling time than passive cooling. The numerical results show that the frequency and amplitude of periodic temperature variation owing to passive-active–passive cooling are a function of Reynolds number, heat flux, PCM volume, and AR of microchannels. The time of active cooling and the quantity of resolidified PCM vary inversely with the Reynolds number. Furthermore, an increase in AR was observed to have a favorable effect on improving the performance of PCM-based hybrid heat sink. For the range of parameters studied in this work, it is observed that around 22%–89% less energy is consumed by a hybrid heat sink if a microchannel of AR 3 is used compared to that of 1. The quantity of PCM plays a vital role in the performance of hybrid heat sinks; therefore, a fin spacing of 1 mm works better than that of 2 and 4 mm. The proposed concept of a hybrid heat sink will help reduce the dependency on an active cooling system for miniaturized electronic devices.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1771-1782"},"PeriodicalIF":2.3,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/TCPMT.2024.3451621
Yuying Li;Mu-Shui Zhang;Zi-Xin Wang
In this article, a lossy coplanar electromagnetic bandgap (EBG) structure embedded with periodic resistors is proposed for anti-resonance suppression and stopband extension. With the aid of the resistors, anti-resonance formed by the capacitance of the unit cell and the parasitic interconnect inductance of the decoupling capacitor is mitigated, the lower cutoff frequency is shifted below 1 MHz, three orders of magnitude reduction compared to the conventional coplanar EBG structures, and two orders of magnitude reduction compared to the current stopband-enhanced coplanar EBG structures. An equivalent circuit model is developed and the effect of parameters of capacitance, inductance, and resistance of the lossy components is analyzed. To verify the effectiveness of the structure, test boards are fabricated and measured both in the high- and low-frequency ranges. Measurements and full-wave simulation results are in good agreement, showing that the proposed structure creates a stopband from 0.63 MHz to 9.91 GHz under the suppression level of −30 dB. The lower cutoff frequency falls in the effective frequency range of the lossy RC components and becomes insensitive to the bridge inductance, so the bridges between neighboring EBG cells can be shortened and widened, which will mitigate the degradation of signal integrity (SI). Eye diagram results show that the maximum eye open (MEO) has a 25% improvement by the lossy components.
{"title":"A Lossy Coplanar EBG Structure for Anti-Resonance Suppression and Stopband Extension","authors":"Yuying Li;Mu-Shui Zhang;Zi-Xin Wang","doi":"10.1109/TCPMT.2024.3451621","DOIUrl":"10.1109/TCPMT.2024.3451621","url":null,"abstract":"In this article, a lossy coplanar electromagnetic bandgap (EBG) structure embedded with periodic resistors is proposed for anti-resonance suppression and stopband extension. With the aid of the resistors, anti-resonance formed by the capacitance of the unit cell and the parasitic interconnect inductance of the decoupling capacitor is mitigated, the lower cutoff frequency is shifted below 1 MHz, three orders of magnitude reduction compared to the conventional coplanar EBG structures, and two orders of magnitude reduction compared to the current stopband-enhanced coplanar EBG structures. An equivalent circuit model is developed and the effect of parameters of capacitance, inductance, and resistance of the lossy components is analyzed. To verify the effectiveness of the structure, test boards are fabricated and measured both in the high- and low-frequency ranges. Measurements and full-wave simulation results are in good agreement, showing that the proposed structure creates a stopband from 0.63 MHz to 9.91 GHz under the suppression level of −30 dB. The lower cutoff frequency falls in the effective frequency range of the lossy RC components and becomes insensitive to the bridge inductance, so the bridges between neighboring EBG cells can be shortened and widened, which will mitigate the degradation of signal integrity (SI). Eye diagram results show that the maximum eye open (MEO) has a 25% improvement by the lossy components.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1835-1844"},"PeriodicalIF":2.3,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-29DOI: 10.1109/TCPMT.2024.3451730
Dingkun Tian;Fukang Deng;Yong Wang;Yadong Xu;Zhiqiang Lin;Mujiu Chen;Guoping Zhang;Yougen Hu;Rong Sun
With the progressive demands of electronics, advanced electromagnetic interference (EMI) shielding technology are desired to protect electronics against risk from EMI radiation under various conditions. In this work, a new kind of 3-D conformal EMI shielding technology based on a polymer composite film with high stretchability and electrical conductivity was proposed. The conductive composite film contains thermal plastic polymer matrix, metallic fillers, and additives, which exhibits excellent conductive, stretchable, and adhesive properties, and provides 3-D conformable capability on a printed circuit board assembly (PCBA). The conductive composite film shows a high EMI shielding effectiveness (SE) value of 72 dB in the 30–3000 MHz and 91 dB in the 8.2–12.4 GHz at thickness of $65~mu $ m, and relative near-field SE value of exceed 35 dB in 500–6000 MHz. Obviously, this novel conformal EMI shielding technology will be a promising candidate for application in board-level shielding (BLS).
随着对电子产品要求的不断提高，人们需要先进的电磁干扰（EMI）屏蔽技术来保护电子产品在各种条件下免受 EMI 辐射的危害。本研究提出了一种基于高拉伸性和导电性聚合物复合膜的新型三维保形 EMI 屏蔽技术。这种导电复合膜包含热塑料聚合物基体、金属填料和添加剂，具有优异的导电性、可拉伸性和粘合性，可在印刷电路板组件（PCBA）上实现三维保形。在厚度为 65~mu $ m 时，该导电复合膜在 30-3000 MHz 和 8.2-12.4 GHz 的电磁干扰屏蔽效能（SE）值分别为 72 dB 和 91 dB，在 500-6000 MHz 的相对近场 SE 值超过 35 dB。显然，这种新型保形 EMI 屏蔽技术将有望应用于板级屏蔽（BLS）。
{"title":"3-D-Conformable Conductive Composite Film for Printed Circuit Board Level Electromagnetic Interference Shielding","authors":"Dingkun Tian;Fukang Deng;Yong Wang;Yadong Xu;Zhiqiang Lin;Mujiu Chen;Guoping Zhang;Yougen Hu;Rong Sun","doi":"10.1109/TCPMT.2024.3451730","DOIUrl":"10.1109/TCPMT.2024.3451730","url":null,"abstract":"With the progressive demands of electronics, advanced electromagnetic interference (EMI) shielding technology are desired to protect electronics against risk from EMI radiation under various conditions. In this work, a new kind of 3-D conformal EMI shielding technology based on a polymer composite film with high stretchability and electrical conductivity was proposed. The conductive composite film contains thermal plastic polymer matrix, metallic fillers, and additives, which exhibits excellent conductive, stretchable, and adhesive properties, and provides 3-D conformable capability on a printed circuit board assembly (PCBA). The conductive composite film shows a high EMI shielding effectiveness (SE) value of 72 dB in the 30–3000 MHz and 91 dB in the 8.2–12.4 GHz at thickness of \u0000<inline-formula> <tex-math>$65~mu $ </tex-math></inline-formula>\u0000m, and relative near-field SE value of exceed 35 dB in 500–6000 MHz. Obviously, this novel conformal EMI shielding technology will be a promising candidate for application in board-level shielding (BLS).","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1825-1834"},"PeriodicalIF":2.3,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/TCPMT.2024.3451136
Haiyan Sun;Dongqing Cang;Zixuan Dong;Jicong Zhao;Zhikuang Cai
With the development of high-performance computing and artificial intelligence, the transistor density of systems on a chip is also increasing exponentially, and the packaging solution for future high-performance chips has shifted toward chip-on-wafer-on-substrate (CoWoS) packaging. However, with the complexity of the CoWoS packaging structure and the increase in the number of chips, it is extremely challenging to analyze the steady-state heat of the CoWoS packaging. This is a necessary measure to optimize the chip layout and evaluate the package’s reliability. Based on the heat transfer path from the chip to the environment, an analytical model has been proposed in this study to calculate the temperature of multiple chiplets CoWoS packaging. The thermal coupling between multiple chiplets and the thermal equivalence of the through-silicon via (TSV) interposer are fully taken into account in this model. Each thermal resistance in the packaging has an analytical solution, and each chiplet has a junction temperature calculation expression. To verify the accuracy of the model calculation data, this study uses finite element simulation to calculate the chiplet temperature for two cases under two sets of thermal conditions. The data show that this model has high accuracy and fast calculation speed for temperature calculation of CoWoS multiple chiplet packaging.
{"title":"Enhanced Junction Temperature Prediction Model for CoWoS Packaging With Multiple Chiplets","authors":"Haiyan Sun;Dongqing Cang;Zixuan Dong;Jicong Zhao;Zhikuang Cai","doi":"10.1109/TCPMT.2024.3451136","DOIUrl":"10.1109/TCPMT.2024.3451136","url":null,"abstract":"With the development of high-performance computing and artificial intelligence, the transistor density of systems on a chip is also increasing exponentially, and the packaging solution for future high-performance chips has shifted toward chip-on-wafer-on-substrate (CoWoS) packaging. However, with the complexity of the CoWoS packaging structure and the increase in the number of chips, it is extremely challenging to analyze the steady-state heat of the CoWoS packaging. This is a necessary measure to optimize the chip layout and evaluate the package’s reliability. Based on the heat transfer path from the chip to the environment, an analytical model has been proposed in this study to calculate the temperature of multiple chiplets CoWoS packaging. The thermal coupling between multiple chiplets and the thermal equivalence of the through-silicon via (TSV) interposer are fully taken into account in this model. Each thermal resistance in the packaging has an analytical solution, and each chiplet has a junction temperature calculation expression. To verify the accuracy of the model calculation data, this study uses finite element simulation to calculate the chiplet temperature for two cases under two sets of thermal conditions. The data show that this model has high accuracy and fast calculation speed for temperature calculation of CoWoS multiple chiplet packaging.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1783-1791"},"PeriodicalIF":2.3,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-26DOI: 10.1109/TCPMT.2024.3449330
Lihao Liu;Yunhui Li;Beisi Lu;Li Shang;Fan Yang
A chiplet-based heterogeneous integrated system design has emerged as a new trend in advanced packaging. However, the high density and complexity of high-speed interconnects between chiplets introduce significant signal integrity (SI) challenges. Rapid and accurate assessment of SI during the design stage is critical to ensure the functionality and performance of chiplet-based systems. Traditional numerical methods for evaluating SI, such as the method of moments (MoM), face challenges due to their substantial demands on computing time and hardware resources. This work presents GNN-SP, a novel graph neural network (GNN)-based method for rapid S-parameter estimation of chiplet interconnects, as well as an open dataset for chiplet interconnect SI based on the Universal Chiplet Interconnect Express (UCIe) standard. GNN is capable of capturing different combinations of local interconnect patterns through message passing, and in GNN-SP, global information is encoded into graph nodes to be incorporated into the node aggregation process. Therefore, the GNN model is able to learn both global and intricate local information of complex interconnects. Compared with convolutional neural networks (CNNs) and multilayer perceptron (MLP)-based methods for predicting the magnitude and phase of S-parameters, GNN-SP reduces the average relative error from 70% to 90% and achieves a speedup of $1.3{times }$ – $9.97{times }$ . Compared with the commercial Agilent advanced design system (ADS) Momentum simulator based on the MoM, GNN-SP achieves a speedup of 22 $099{times }$ with an average relative error below 1.93% for insertion/return loss and an average relative error below 3.31% for crosstalk.
基于芯片的异构集成系统设计已成为先进封装的新趋势。然而，芯片间高速互连的高密度和复杂性带来了巨大的信号完整性（SI）挑战。在设计阶段快速、准确地评估 SI 对于确保芯片系统的功能和性能至关重要。用于评估 SI 的传统数值方法（如矩法 (MoM)）因其对计算时间和硬件资源的大量需求而面临挑战。本研究提出了一种基于图神经网络（GNN）的新方法 GNN-SP，用于快速估算芯片互连的 S 参数，以及基于通用芯片互连 Express（UCIe）标准的芯片互连 SI 开放数据集。GNN 能够通过消息传递捕捉本地互连模式的不同组合，而在 GNN-SP 中，全局信息被编码到图节点中，以纳入节点聚合过程。因此，GNN 模型能够学习复杂互连的全局信息和错综复杂的局部信息。与基于卷积神经网络（CNN）和多层感知器（MLP）的 S 参数幅值和相位预测方法相比，GNN-SP 将平均相对误差从 70% 降低到 90%，速度提高了 1.3{times }$ - 9.97{times }$。与基于 MoM 的商用安捷伦高级设计系统 (ADS) Momentum 仿真器相比，GNN-SP 的速度提高了 22 $099{/times }$，插入/回波损耗的平均相对误差低于 1.93%，串扰的平均相对误差低于 3.31%。
{"title":"GNN-SP: Fast S-Parameter Estimation of Chiplet Interconnect via Graph Neural Network","authors":"Lihao Liu;Yunhui Li;Beisi Lu;Li Shang;Fan Yang","doi":"10.1109/TCPMT.2024.3449330","DOIUrl":"10.1109/TCPMT.2024.3449330","url":null,"abstract":"A chiplet-based heterogeneous integrated system design has emerged as a new trend in advanced packaging. However, the high density and complexity of high-speed interconnects between chiplets introduce significant signal integrity (SI) challenges. Rapid and accurate assessment of SI during the design stage is critical to ensure the functionality and performance of chiplet-based systems. Traditional numerical methods for evaluating SI, such as the method of moments (MoM), face challenges due to their substantial demands on computing time and hardware resources. This work presents GNN-SP, a novel graph neural network (GNN)-based method for rapid S-parameter estimation of chiplet interconnects, as well as an open dataset for chiplet interconnect SI based on the Universal Chiplet Interconnect Express (UCIe) standard. GNN is capable of capturing different combinations of local interconnect patterns through message passing, and in GNN-SP, global information is encoded into graph nodes to be incorporated into the node aggregation process. Therefore, the GNN model is able to learn both global and intricate local information of complex interconnects. Compared with convolutional neural networks (CNNs) and multilayer perceptron (MLP)-based methods for predicting the magnitude and phase of S-parameters, GNN-SP reduces the average relative error from 70% to 90% and achieves a speedup of \u0000<inline-formula> <tex-math>$1.3{times }$ </tex-math></inline-formula>\u0000–\u0000<inline-formula> <tex-math>$9.97{times }$ </tex-math></inline-formula>\u0000. Compared with the commercial Agilent advanced design system (ADS) Momentum simulator based on the MoM, GNN-SP achieves a speedup of 22\u0000<inline-formula> <tex-math>$099{times }$ </tex-math></inline-formula>\u0000 with an average relative error below 1.93% for insertion/return loss and an average relative error below 3.31% for crosstalk.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1862-1871"},"PeriodicalIF":2.3,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/TCPMT.2024.3449047
Rahul Gupta;Nieqing Cao;Sang Won Yoon;Yu Jin;Daehan Won
This article presents a dynamic simulation model for the stencil-printing process (SPP) in surface mount technology (SMT) assembly lines, focusing on accurately replicating the real-time stencil printing while allowing adjustments to printer settings. The model offers a time and cost-effective alternative to the experiments and a reliable testing environment for researchers and technologists investigating advanced algorithms and strategic methodologies in SMT printing. SPP is influenced by various controllable factors, such as printer parameters. However, an additional challenge arises from uncontrollable environmental noise that affects the printing quality, leading to uneven solder paste application and machine precision that brings randomness to the results. Recognizing the need to mitigate the effects of this environmental noise and enhance the accuracy of the simulator, the proposed simulation model incorporates a dual-tree complex wavelet transform (DTCWT) algorithm. DTCWT used in this model addresses the challenge of environmental noise affecting the printing quality, showcasing an enhanced capability in noise reduction and signal clarity. The noise from the SPP data is modeled and extracted from the DTCWT model and introduced into the simulation model to improve the prediction accuracy. The simulation model demonstrated an improvement of 36% in Volume AVG and 62% in Volume STD accuracy on root-mean-squared error (RMSE), marking a significant advancement over the statistical simulator.
{"title":"A Dual-Tree Complex Wavelet Transform Simulation Model for Improved Noise Modeling and Prediction of Real-Time Stencil-Printing Process","authors":"Rahul Gupta;Nieqing Cao;Sang Won Yoon;Yu Jin;Daehan Won","doi":"10.1109/TCPMT.2024.3449047","DOIUrl":"10.1109/TCPMT.2024.3449047","url":null,"abstract":"This article presents a dynamic simulation model for the stencil-printing process (SPP) in surface mount technology (SMT) assembly lines, focusing on accurately replicating the real-time stencil printing while allowing adjustments to printer settings. The model offers a time and cost-effective alternative to the experiments and a reliable testing environment for researchers and technologists investigating advanced algorithms and strategic methodologies in SMT printing. SPP is influenced by various controllable factors, such as printer parameters. However, an additional challenge arises from uncontrollable environmental noise that affects the printing quality, leading to uneven solder paste application and machine precision that brings randomness to the results. Recognizing the need to mitigate the effects of this environmental noise and enhance the accuracy of the simulator, the proposed simulation model incorporates a dual-tree complex wavelet transform (DTCWT) algorithm. DTCWT used in this model addresses the challenge of environmental noise affecting the printing quality, showcasing an enhanced capability in noise reduction and signal clarity. The noise from the SPP data is modeled and extracted from the DTCWT model and introduced into the simulation model to improve the prediction accuracy. The simulation model demonstrated an improvement of 36% in Volume AVG and 62% in Volume STD accuracy on root-mean-squared error (RMSE), marking a significant advancement over the statistical simulator.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 10","pages":"1872-1880"},"PeriodicalIF":2.3,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Challenges and Technologies of Frontside Via-Last Active-Interposer Processes on Low-k Material for 3D Chiplet","authors":"Rui Cao, Huimin He, Lijun Chen, Chengyi Liao, Fengman Liu, Liqiang Cao, Qidong Wang","doi":"10.1109/tcpmt.2024.3443855","DOIUrl":"https://doi.org/10.1109/tcpmt.2024.3443855","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"16 1","pages":""},"PeriodicalIF":2.2,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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