Pub Date : 2024-12-26DOI: 10.1109/TCPMT.2024.3522315
Shaoyi Liu;Song Xue;Jianlun Huang;Hao Wang;Zhihai Wang;Congsi Wang
The through-silicon via (TSV) technology, due to its fine feature dimensions and high operating frequency, introduces complexity in performance analysis. Traditional analytical methods can become unrealistic when confronting the multiple considerations of thermomechanical and signal transmission characteristics. This article introduces a collaborative optimization framework incorporating the multioutput multifidelity surrogate model (MOMFSM) with a multiobjective optimizer. This framework aims to accelerate TSV structure design accounting for the multiphysics effect with low computational demand and uncompromised accuracy. The MOMFSM improves predictive accuracy by capturing the correlations between various physical outputs of TSV and fuses data of different fidelities, reducing reliance on high-fidelity (HF) data. Employing the rapid and precise MOMFSM, thermal stress and S-parameters distributions in TSV were simulated and used as analytical functions for design objectives. The multiobjective optimizer conducts an efficient multiphysics collaborative optimization, yielding a set of nondominated optimization solutions. The technique for order preference by similarity to an ideal solution (TOPSIS) was employed to derive the best compromise solution (BCS) from these options. The results indicate that the thermal stress in TSV interconnection was reduced from 690.3 to 635.4 MPa, the $S_{11}$ at 30 GHz decreased from −26.29 to −39.93 dB, and the $S_{21}$ at 30 GHz increased from −0.646 to −0.443 dB. This study, moreover, provides valuable insights for the comprehensive enhancement of TSV multiphysics performance and offers robust support for integrated circuit (IC) interconnection design.
{"title":"A Data-Driven Approach to Collaborative Optimization for Enhancing TSV Multiphysics Performance","authors":"Shaoyi Liu;Song Xue;Jianlun Huang;Hao Wang;Zhihai Wang;Congsi Wang","doi":"10.1109/TCPMT.2024.3522315","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3522315","url":null,"abstract":"The through-silicon via (TSV) technology, due to its fine feature dimensions and high operating frequency, introduces complexity in performance analysis. Traditional analytical methods can become unrealistic when confronting the multiple considerations of thermomechanical and signal transmission characteristics. This article introduces a collaborative optimization framework incorporating the multioutput multifidelity surrogate model (MOMFSM) with a multiobjective optimizer. This framework aims to accelerate TSV structure design accounting for the multiphysics effect with low computational demand and uncompromised accuracy. The MOMFSM improves predictive accuracy by capturing the correlations between various physical outputs of TSV and fuses data of different fidelities, reducing reliance on high-fidelity (HF) data. Employing the rapid and precise MOMFSM, thermal stress and S-parameters distributions in TSV were simulated and used as analytical functions for design objectives. The multiobjective optimizer conducts an efficient multiphysics collaborative optimization, yielding a set of nondominated optimization solutions. The technique for order preference by similarity to an ideal solution (TOPSIS) was employed to derive the best compromise solution (BCS) from these options. The results indicate that the thermal stress in TSV interconnection was reduced from 690.3 to 635.4 MPa, the <inline-formula> <tex-math>$S_{11}$ </tex-math></inline-formula> at 30 GHz decreased from −26.29 to −39.93 dB, and the <inline-formula> <tex-math>$S_{21}$ </tex-math></inline-formula> at 30 GHz increased from −0.646 to −0.443 dB. This study, moreover, provides valuable insights for the comprehensive enhancement of TSV multiphysics performance and offers robust support for integrated circuit (IC) interconnection design.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"253-262"},"PeriodicalIF":2.3,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-26DOI: 10.1109/TCPMT.2024.3522319
Qianzhen Su;Zepeng Wang;Bo Zhang;Haoyuan Zhao;Dandan Liu;Jingliang Li;Xiaolong Wen;Jianhua Li
The amorphous wire demonstrates good soft magnetic properties and the giant magnetoimpedance (GMI) effect. However, the amorphous wire with a diameter ranging from several micrometers to several tens of micrometers is soft and thin; thus, it is difficult to handle and fabricate to achieve a magnetic sensor. In addition, the electrical contact resistance of the amorphous wire with pads shows wide distribution due to the contact area being hard to control when welding. To solve these problems, this article proposed a microelectronic fabrication method for an amorphous wire-based magnetic sensor. Glass wafer was used as the supporting substrate of the amorphous wire, and nonphotosensitive polyimide resin was employed as the electroplating mask. Electroplating was performed to achieve the electrical interconnection between the amorphous wire and pads on the substrate. The structure fabricated above was composed of amorphous wire and a supporting glass substrate. Then, the enameled wire was uniformly wound around the fabricated structure as a signal pickup coil. The test results showed excellent linearity within the range of −0.6 to +0.6 Oe and a sensitivity of 6.38 V/Oe.
{"title":"A Fabrication Method for Amorphous Wire GMI Magnetic Sensor With Microelectronic Manufacturing Technology","authors":"Qianzhen Su;Zepeng Wang;Bo Zhang;Haoyuan Zhao;Dandan Liu;Jingliang Li;Xiaolong Wen;Jianhua Li","doi":"10.1109/TCPMT.2024.3522319","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3522319","url":null,"abstract":"The amorphous wire demonstrates good soft magnetic properties and the giant magnetoimpedance (GMI) effect. However, the amorphous wire with a diameter ranging from several micrometers to several tens of micrometers is soft and thin; thus, it is difficult to handle and fabricate to achieve a magnetic sensor. In addition, the electrical contact resistance of the amorphous wire with pads shows wide distribution due to the contact area being hard to control when welding. To solve these problems, this article proposed a microelectronic fabrication method for an amorphous wire-based magnetic sensor. Glass wafer was used as the supporting substrate of the amorphous wire, and nonphotosensitive polyimide resin was employed as the electroplating mask. Electroplating was performed to achieve the electrical interconnection between the amorphous wire and pads on the substrate. The structure fabricated above was composed of amorphous wire and a supporting glass substrate. Then, the enameled wire was uniformly wound around the fabricated structure as a signal pickup coil. The test results showed excellent linearity within the range of −0.6 to +0.6 Oe and a sensitivity of 6.38 V/Oe.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"236-243"},"PeriodicalIF":2.3,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Indium (In) is the widely adopted solder thermal interface materials (TIM1) for high-power central processing unit (CPU) chips, primarily because it offers improved heat dissipation performance. However, organic flux residues trapped within In solder can outgas and create a lot of voids (void rate ~35%) in In TIM1 during solder ball reflow, which limits its application in advanced ball grid array (BGA) package. In this article, to realize fluxless In reflow and obtain a low void rate In TIM1, a thin silver (Ag) layer is electroplating on a thick In TIM1 surface to form in situ generated AgIn2 coating, which can protect In from oxidation. Thus, flux is not required to remove the oxide layer of solder during reflow. After an In reflow and solder ball reflow for three times, a low void rate (4.2%) joint is produced confirmed by a scanning acoustic microscope (SAM). Better heat transfer capability and mechanical property (+11.4%) are also obtained. A novel AgIn2 coating decomposition mechanism during reflow is also found. During In reflow, AgIn2 would decompose into In and Ag atoms, and the Ag atoms could increase the wettability of solder and shear strength of the joint.
{"title":"Investigation on Indium Thermal Interface Materials Fluxless Bonding Technology via In Situ Formed AgIn₂ Coating","authors":"Jing Wen;Yi Fan;Guoliao Sun;Jinyang Su;Linzheng Fu;Zhuo Chen;Wenhui Zhu","doi":"10.1109/TCPMT.2024.3522254","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3522254","url":null,"abstract":"Indium (In) is the widely adopted solder thermal interface materials (TIM1) for high-power central processing unit (CPU) chips, primarily because it offers improved heat dissipation performance. However, organic flux residues trapped within In solder can outgas and create a lot of voids (void rate ~35%) in In TIM1 during solder ball reflow, which limits its application in advanced ball grid array (BGA) package. In this article, to realize fluxless In reflow and obtain a low void rate In TIM1, a thin silver (Ag) layer is electroplating on a thick In TIM1 surface to form in situ generated AgIn2 coating, which can protect In from oxidation. Thus, flux is not required to remove the oxide layer of solder during reflow. After an In reflow and solder ball reflow for three times, a low void rate (4.2%) joint is produced confirmed by a scanning acoustic microscope (SAM). Better heat transfer capability and mechanical property (+11.4%) are also obtained. A novel AgIn2 coating decomposition mechanism during reflow is also found. During In reflow, AgIn2 would decompose into In and Ag atoms, and the Ag atoms could increase the wettability of solder and shear strength of the joint.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"421-427"},"PeriodicalIF":2.3,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TCPMT.2024.3521292
Sambit Kumar Ghosh;Ethan Kepros;Premjeet Chahal
This article introduces a new method to fabricate low-loss terahertz (THz) frequency-selective surfaces (FSSs) on flexible substrates. The process involves the printing of periodic metallic patterns on glass substrate using aerosol-jet printing (AJP) technology and silver-based nanoparticle ink followed by a novel lift-off process using thin parylene-C. The printed structures on glass can be sintered at high temperatures to achieve high conductivity silver structures. These printed structures are lifted of using a thin ($10~mu $ m) parylene-C. Use of thin parylene-C reduces the effective dielectric losses. Several designs are demonstrated including parallel wire-grid and a tilted I-shaped polarizer, and a few THz FSS bandpass and band-stop filters. All the prototypes are designed, fabricated, and experimentally validated. The proposed FSSs can find applications in the next generation of low-loss THz flexible electronics.
{"title":"Aerosol-Jet Printed High-Q Quasi-Optical FSSs on Flex Substrates Using a Novel Parylene Lift-Off Process","authors":"Sambit Kumar Ghosh;Ethan Kepros;Premjeet Chahal","doi":"10.1109/TCPMT.2024.3521292","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3521292","url":null,"abstract":"This article introduces a new method to fabricate low-loss terahertz (THz) frequency-selective surfaces (FSSs) on flexible substrates. The process involves the printing of periodic metallic patterns on glass substrate using aerosol-jet printing (AJP) technology and silver-based nanoparticle ink followed by a novel lift-off process using thin parylene-C. The printed structures on glass can be sintered at high temperatures to achieve high conductivity silver structures. These printed structures are lifted of using a thin (<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m) parylene-C. Use of thin parylene-C reduces the effective dielectric losses. Several designs are demonstrated including parallel wire-grid and a tilted I-shaped polarizer, and a few THz FSS bandpass and band-stop filters. All the prototypes are designed, fabricated, and experimentally validated. The proposed FSSs can find applications in the next generation of low-loss THz flexible electronics.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"244-252"},"PeriodicalIF":2.3,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-17DOI: 10.1109/TCPMT.2024.3519434
Jia-Xing Guo;Jian-Kang Xiao;Tan Song
In this article, a new butterfly-shaped filtering antenna array with Chebyshev filtering response, and a new wideband circularly polarized antenna array have been proposed, both using self-packaged multilayer suspended substrate technique. The filtering antenna array integrates the functions of a bandpass filter, a power divider, and a $2times 2$ antenna array by using multiple coupling resonators, while the circularly polarized antenna array is constructed by the wide slot structure using sequential rotation technique with 90° phase difference on neighboring antenna unit. Measured by vector network analyzer and spherical multiprobe test system, the filtering antenna array has been demonstrated with an impedance bandwidth of 11.8%, a favorable gain of 10.5 dBi, and a pair of gain zeros; meanwhile, the circularly polarized antenna array has a measured fractional impedance bandwidth of 60.9%, a maximum gain of 10.2 dBi, and a wide 3 dB axial ratio bandwidth covering 3.18–5.8 GHz. The measured results agree with the simulations. The proposed works integrate the advantages of suspended coplanar waveguide (SCPW), multiple resonators including microstrip patches and wide slots, which not only improve the design flexibility but also achieve wideband and favorable gain. While the feeding network and the radiation elements can be protected by the self-packaged construction.
{"title":"Wideband Filtering and Circularly Polarized Antenna Arrays With Self-Packaged Multilayer Suspended Substrate Technique","authors":"Jia-Xing Guo;Jian-Kang Xiao;Tan Song","doi":"10.1109/TCPMT.2024.3519434","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3519434","url":null,"abstract":"In this article, a new butterfly-shaped filtering antenna array with Chebyshev filtering response, and a new wideband circularly polarized antenna array have been proposed, both using self-packaged multilayer suspended substrate technique. The filtering antenna array integrates the functions of a bandpass filter, a power divider, and a <inline-formula> <tex-math>$2times 2$ </tex-math></inline-formula> antenna array by using multiple coupling resonators, while the circularly polarized antenna array is constructed by the wide slot structure using sequential rotation technique with 90° phase difference on neighboring antenna unit. Measured by vector network analyzer and spherical multiprobe test system, the filtering antenna array has been demonstrated with an impedance bandwidth of 11.8%, a favorable gain of 10.5 dBi, and a pair of gain zeros; meanwhile, the circularly polarized antenna array has a measured fractional impedance bandwidth of 60.9%, a maximum gain of 10.2 dBi, and a wide 3 dB axial ratio bandwidth covering 3.18–5.8 GHz. The measured results agree with the simulations. The proposed works integrate the advantages of suspended coplanar waveguide (SCPW), multiple resonators including microstrip patches and wide slots, which not only improve the design flexibility but also achieve wideband and favorable gain. While the feeding network and the radiation elements can be protected by the self-packaged construction.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"309-318"},"PeriodicalIF":2.3,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cooling presents a significant challenge for high-performance 3-D integrated circuits (3D ICs). To this end, this research explores through-silicon via (TSV)-compatible micropin-fin heat sink (MPFHS) for high-power 3-D chip stacks. Copper TSVs with a diameter of $5.2~mu $ m and a high aspect ratio (HAR) of 29:1 are developed. An extensive experimental and computational investigation of the MPFHS under varying flow rates and power conditions was conducted, showing that the MPFHS maintains an average chip temperature below $72~^{circ }$ C, even with a total power dissipation of 500 W and a power density of 312 W/cm2 at a flow rate of 117 mL/min. The minimum total thermal resistance achieved was $0.286~^{circ }$ C$cdot $ cm2/W.
{"title":"Toward TSV-Compatible Microfluidic Cooling for 3D ICs","authors":"Geyu Yan;Euichul Chung;Erik Masselink;Shane Oh;Muneeb Zia;Bharath Ramakrishnan;Vaidehi Oruganti;Husam Alissa;Christian Belady;Yunhyeok Im;Yogendra Joshi;Muhannad S. Bakir","doi":"10.1109/TCPMT.2024.3516653","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3516653","url":null,"abstract":"Cooling presents a significant challenge for high-performance 3-D integrated circuits (3D ICs). To this end, this research explores through-silicon via (TSV)-compatible micropin-fin heat sink (MPFHS) for high-power 3-D chip stacks. Copper TSVs with a diameter of <inline-formula> <tex-math>$5.2~mu $ </tex-math></inline-formula>m and a high aspect ratio (HAR) of 29:1 are developed. An extensive experimental and computational investigation of the MPFHS under varying flow rates and power conditions was conducted, showing that the MPFHS maintains an average chip temperature below <inline-formula> <tex-math>$72~^{circ }$ </tex-math></inline-formula>C, even with a total power dissipation of 500 W and a power density of 312 W/cm2 at a flow rate of 117 mL/min. The minimum total thermal resistance achieved was <inline-formula> <tex-math>$0.286~^{circ }$ </tex-math></inline-formula>C<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/W.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"104-112"},"PeriodicalIF":2.3,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/TCPMT.2024.3513323
Mingyao Ma;Qian Zhang;Weisheng Guo;Qiwei Song
The cause of failures in insulated gate bipolar transistor (IGBT) modules is primarily attributed to temperature-related factors. Accurately estimating the junction temperature of IGBT modules is crucial for enhancing their reliability. Currently, thermal network models stand as commonly used tools for estimating the junction temperature of IGBT modules. However, prevailing thermal models exhibit certain limitations in accurately predicting the junction temperature, particularly when considering the degradation of chip solder within IGBT modules. This article presents a practical degradation model of the chip solder layer, establishing a functional correlation between the chip solder degradation rate and the number of power cycles. A dynamic compact thermal network model over long time scales is established, and the method for thermal parameter extraction is discussed. The finite-element simulation and experimental results show that the dynamic compact thermal network model can accurately estimate the junction temperature.
{"title":"Dynamic IGBT Compact Thermal Network Model Over Long Time Scales","authors":"Mingyao Ma;Qian Zhang;Weisheng Guo;Qiwei Song","doi":"10.1109/TCPMT.2024.3513323","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3513323","url":null,"abstract":"The cause of failures in insulated gate bipolar transistor (IGBT) modules is primarily attributed to temperature-related factors. Accurately estimating the junction temperature of IGBT modules is crucial for enhancing their reliability. Currently, thermal network models stand as commonly used tools for estimating the junction temperature of IGBT modules. However, prevailing thermal models exhibit certain limitations in accurately predicting the junction temperature, particularly when considering the degradation of chip solder within IGBT modules. This article presents a practical degradation model of the chip solder layer, establishing a functional correlation between the chip solder degradation rate and the number of power cycles. A dynamic compact thermal network model over long time scales is established, and the method for thermal parameter extraction is discussed. The finite-element simulation and experimental results show that the dynamic compact thermal network model can accurately estimate the junction temperature.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"123-130"},"PeriodicalIF":2.3,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TCPMT.2024.3500721
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2024.3500721","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500721","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C4-C4"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TCPMT.2024.3511042
Tongchuan Ma;Liyiming Yang;Yanlu Li;Yuan Du
This letter presents an innovative noncontact packaging technique for photonic integrated circuits (PICs) and electronic integrated circuits (EICs) through inductively coupled interconnects. The primary aim of this approach is to enhance thermal isolation between the heat-generating electrical logic die and the thermally sensitive optical interferometer die. The feasibility of this contactless transceiver, which fulfills information transmission from the laser Doppler vibrometry (LDV) to the EIC, is substantiated via electromagnetic simulations. Furthermore, thermal simulations conducted by COMSOL prove that this packaging configuration could potentially reduce the temperature of PICs by up to $4.6~^{circ }$ C when compared to the conventional 3-D stack packaging, underlining its potential for improved thermal performance.
{"title":"Noncontact Integration of Photonic IC and Electronic IC via Inductively Coupled Interconnects","authors":"Tongchuan Ma;Liyiming Yang;Yanlu Li;Yuan Du","doi":"10.1109/TCPMT.2024.3511042","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3511042","url":null,"abstract":"This letter presents an innovative noncontact packaging technique for photonic integrated circuits (PICs) and electronic integrated circuits (EICs) through inductively coupled interconnects. The primary aim of this approach is to enhance thermal isolation between the heat-generating electrical logic die and the thermally sensitive optical interferometer die. The feasibility of this contactless transceiver, which fulfills information transmission from the laser Doppler vibrometry (LDV) to the EIC, is substantiated via electromagnetic simulations. Furthermore, thermal simulations conducted by COMSOL prove that this packaging configuration could potentially reduce the temperature of PICs by up to <inline-formula> <tex-math>$4.6~^{circ }$ </tex-math></inline-formula>C when compared to the conventional 3-D stack packaging, underlining its potential for improved thermal performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"232-234"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142992901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TCPMT.2024.3500719
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2024.3500719","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3500719","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778114","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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