Pub Date : 2025-08-18DOI: 10.1109/TCPMT.2025.3599484
Wonchul Do;Sanghyun Jin;Insoo Choi;Jinho Jeong
This article presents a novel redistribution layer (RDL) technology with embedded trace structures, targeting high-density interconnects for organic interposers and bridge chips in 2.5-D integration. The proposed embedded trace RDL (ETR) adopts grayscale lithography, enabling the simultaneous formation of vias and traces in a single lithography step. This single-mask process reduces manufacturing complexity and cost compared to conventional dual-mask ETR approaches and is compatible with I-line steppers commonly used in advanced packaging. The proposed ETR successfully demonstrates four-stacked vias with a minimum diameter of $1.5~mu $ m and traces with 2/$1~mu $ m line/space, validating its capability for fine-pitch, multilayer interconnects. Trace width and dielectric thickness variations were within 7.5% and 2.9% of the median, respectively, and critical dimension uniformity was within 5%. Dense traces between two vias were fabricated and compared with conventional semi-additive process (SAP)-based RDL, confirming that the pad-less vias in the proposed ETR enhance interconnection density. Furthermore, the rounded-edge traces, a distinctive feature of the ETR, reduce conductor loss by mitigating current crowding, leading to improved signal transmission bandwidth. Together, these effects increase bandwidth density, making the proposed ETR highly suitable for advanced high-speed, high-density interconnect applications. Finally, to the best of our knowledge, electromigration (EM) testing was conducted on the ETR structure for the first time, demonstrating a $34.2times $ improvement in mean time-to-failure (MTTF) over SAP-based RDL.
{"title":"Single-Mask Embedded Trace Redistribution Layer Technology Using Grayscale Lithography","authors":"Wonchul Do;Sanghyun Jin;Insoo Choi;Jinho Jeong","doi":"10.1109/TCPMT.2025.3599484","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3599484","url":null,"abstract":"This article presents a novel redistribution layer (RDL) technology with embedded trace structures, targeting high-density interconnects for organic interposers and bridge chips in 2.5-D integration. The proposed embedded trace RDL (ETR) adopts grayscale lithography, enabling the simultaneous formation of vias and traces in a single lithography step. This single-mask process reduces manufacturing complexity and cost compared to conventional dual-mask ETR approaches and is compatible with I-line steppers commonly used in advanced packaging. The proposed ETR successfully demonstrates four-stacked vias with a minimum diameter of <inline-formula> <tex-math>$1.5~mu $ </tex-math></inline-formula>m and traces with 2/<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>m line/space, validating its capability for fine-pitch, multilayer interconnects. Trace width and dielectric thickness variations were within 7.5% and 2.9% of the median, respectively, and critical dimension uniformity was within 5%. Dense traces between two vias were fabricated and compared with conventional semi-additive process (SAP)-based RDL, confirming that the pad-less vias in the proposed ETR enhance interconnection density. Furthermore, the rounded-edge traces, a distinctive feature of the ETR, reduce conductor loss by mitigating current crowding, leading to improved signal transmission bandwidth. Together, these effects increase bandwidth density, making the proposed ETR highly suitable for advanced high-speed, high-density interconnect applications. Finally, to the best of our knowledge, electromigration (EM) testing was conducted on the ETR structure for the first time, demonstrating a <inline-formula> <tex-math>$34.2times $ </tex-math></inline-formula> improvement in mean time-to-failure (MTTF) over SAP-based RDL.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 10","pages":"2269-2278"},"PeriodicalIF":3.0,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145374744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/TCPMT.2025.3597811
Bijan Shahriari;Roni Khazaka
Behavioral modeling of analog circuits is an important step of the integrated circuit design flow. Indeed, closed-box behavior modeling allows users to replicate the behavior of circuit elements and devices without explicitly knowing the inner workings of the device. Prior works have automated the generation of behavioral models using machine learning (ML) at both the device and circuit level. More specifically, a recent work has used high-order polynomial projection operators (HIPPOs) to augment gated recurrent unit (GRU)-based macro-models. This new HIPPO-based model has been shown to outperform state-of-the-art GRU-based circuit macro-models. In this article, we introduce a new type of modified recurrent neural network (RNN) circuit macro-model that uses the HIPPO framework, called HIPPO-RNN. Additionally, we present a modified HIPPO-RNN (stable-HIPPO-RNN) model that is more suitable for enforcing input-to-state stability (ISS), and derive corresponding stability constraints. These constraints effectively guarantee ISS stability of the macro-model during transient simulation. We show the validity and superior performance of our macro-models on two circuit modeling examples.
{"title":"Stable HIPPO-Based Circuit Macro-Modeling","authors":"Bijan Shahriari;Roni Khazaka","doi":"10.1109/TCPMT.2025.3597811","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3597811","url":null,"abstract":"Behavioral modeling of analog circuits is an important step of the integrated circuit design flow. Indeed, closed-box behavior modeling allows users to replicate the behavior of circuit elements and devices without explicitly knowing the inner workings of the device. Prior works have automated the generation of behavioral models using machine learning (ML) at both the device and circuit level. More specifically, a recent work has used high-order polynomial projection operators (HIPPOs) to augment gated recurrent unit (GRU)-based macro-models. This new HIPPO-based model has been shown to outperform state-of-the-art GRU-based circuit macro-models. In this article, we introduce a new type of modified recurrent neural network (RNN) circuit macro-model that uses the HIPPO framework, called HIPPO-RNN. Additionally, we present a modified HIPPO-RNN (stable-HIPPO-RNN) model that is more suitable for enforcing input-to-state stability (ISS), and derive corresponding stability constraints. These constraints effectively guarantee ISS stability of the macro-model during transient simulation. We show the validity and superior performance of our macro-models on two circuit modeling examples.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1823-1835"},"PeriodicalIF":3.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/TCPMT.2025.3597771
Antonio Carlucci;Ion Victor Gosea;Stefano Grivet-Talocia
This article presents a complete framework for the generation of behavioral macromodels of a wide class of nonlinear components, devices, and systems. The model structure and related identification algorithms are based on the Volterra series formulated in the frequency domain through multivariate generalized transfer functions (GTFs). A multivariate rational model is first estimated in pole-residue form from sampled responses and then converted to a bilinear state-space form. The main novel contribution of this work is the SPICE-compatible circuit synthesis, which enables the usage of nonlinear macromodels within circuit simulation environments as part of more complex system-level simulations. Examples are provided for a low dropout voltage regulator and a system-level power distribution network embedding integrated regulators. For such examples, the proposed SPICE equivalents offer speedup factors ranging from $12times $ up to $650times $ with negligible loss in accuracy.
{"title":"On the Generation of SPICE-Compatible Nonlinear Behavioral Macromodels","authors":"Antonio Carlucci;Ion Victor Gosea;Stefano Grivet-Talocia","doi":"10.1109/TCPMT.2025.3597771","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3597771","url":null,"abstract":"This article presents a complete framework for the generation of behavioral macromodels of a wide class of nonlinear components, devices, and systems. The model structure and related identification algorithms are based on the Volterra series formulated in the frequency domain through multivariate generalized transfer functions (GTFs). A multivariate rational model is first estimated in pole-residue form from sampled responses and then converted to a bilinear state-space form. The main novel contribution of this work is the SPICE-compatible circuit synthesis, which enables the usage of nonlinear macromodels within circuit simulation environments as part of more complex system-level simulations. Examples are provided for a low dropout voltage regulator and a system-level power distribution network embedding integrated regulators. For such examples, the proposed SPICE equivalents offer speedup factors ranging from <inline-formula> <tex-math>$12times $ </tex-math></inline-formula> up to <inline-formula> <tex-math>$650times $ </tex-math></inline-formula> with negligible loss in accuracy.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1857-1867"},"PeriodicalIF":3.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/TCPMT.2025.3597840
Til Hillebrecht;Tommy Weber;Johannes Alfert;Christian Schuster
The introduction of machine learning (ML) methods into the design process of printed circuit boards (PCBs) drives the need for large quantities of readily available data. This article addresses the problems of engineers to find ML-ready data that can be easily reused and combined to enhance PCB design by storing the defining parameters in a normalized format within a relational database. It implements search and filter functions to obtain relevant data quickly. The database contains data that were used to address a variety of different signal integrity (SI)- and power integrity (PI)-related problems. Details of the database structure, necessary data conversion steps, currently stored datasets, and a statistical analysis thereof are described. This database is capable of being automated to a degree that ML agents can interact with it.
{"title":"Relational SI/PI-Database for a Data-Driven Approach to PCB Design Automation and Performance Prediction","authors":"Til Hillebrecht;Tommy Weber;Johannes Alfert;Christian Schuster","doi":"10.1109/TCPMT.2025.3597840","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3597840","url":null,"abstract":"The introduction of machine learning (ML) methods into the design process of printed circuit boards (PCBs) drives the need for large quantities of readily available data. This article addresses the problems of engineers to find ML-ready data that can be easily reused and combined to enhance PCB design by storing the defining parameters in a normalized format within a relational database. It implements search and filter functions to obtain relevant data quickly. The database contains data that were used to address a variety of different signal integrity (SI)- and power integrity (PI)-related problems. Details of the database structure, necessary data conversion steps, currently stored datasets, and a statistical analysis thereof are described. This database is capable of being automated to a degree that ML agents can interact with it.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1847-1856"},"PeriodicalIF":3.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a vertically stacked bi-color micro-light-emitting diode (Micro-LED) array structure employing Au–Sn hybrid bonding technology is presented. The design integrates blue flip-chip and green vertical Micro-LEDs into a common cathode circuit configuration, achieving an ultrafine pixel pitch of $5~mu $ m across $343times 387$ array on 1.6-cm2 substrate. Precise hybrid bonding was performed at $233~^{circ }$ C for 30 min, enabling effective Au–Sn alloy formation. The structure’s performance was verified through electrical character and cross-sectional SEM-EDX analysis, demonstrating minimal voltage increase postbonding and confirming the feasibility of independent control for both colors. This integration approach provides a scalable solution for high resolution, compact, and low-power consumption. The Micro-LEDs display applications, particularly suited for near-eye devices such as augmented and virtual reality systems.
{"title":"Using Hybrid Bonding for Stacked Bi-Color Micro-Light-Emitting Diodes","authors":"Wen-Ching Hung;Jui-Fu Chang;Sheng-Po Chang;Shoou-Jinn Chang;Jyh-Chen Chen","doi":"10.1109/TCPMT.2025.3595581","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3595581","url":null,"abstract":"In this work, a vertically stacked bi-color micro-light-emitting diode (Micro-LED) array structure employing Au–Sn hybrid bonding technology is presented. The design integrates blue flip-chip and green vertical Micro-LEDs into a common cathode circuit configuration, achieving an ultrafine pixel pitch of <inline-formula> <tex-math>$5~mu $ </tex-math></inline-formula>m across <inline-formula> <tex-math>$343times 387$ </tex-math></inline-formula> array on 1.6-cm<sup>2</sup> substrate. Precise hybrid bonding was performed at <inline-formula> <tex-math>$233~^{circ }$ </tex-math></inline-formula>C for 30 min, enabling effective Au–Sn alloy formation. The structure’s performance was verified through electrical character and cross-sectional SEM-EDX analysis, demonstrating minimal voltage increase postbonding and confirming the feasibility of independent control for both colors. This integration approach provides a scalable solution for high resolution, compact, and low-power consumption. The Micro-LEDs display applications, particularly suited for near-eye devices such as augmented and virtual reality systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1886-1889"},"PeriodicalIF":3.0,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-04DOI: 10.1109/TCPMT.2025.3595152
Satyapal Singh;Vijay Kumar;Navin Kumar
In this article, a novel symmetric-structure-based silicon microelectromechanical systems (MEMS) piezoresistive accelerometer is proposed. Compared to conventional structures based on multiple support beams and hanging-seismic-mass, the symmetric-structure not only reduces cross-axis output but also ensures lower stresses in the flexures when subjected to cross-axis acceleration inputs. It increases the ratio of the fracture acceleration limit in the cross-direction to that in the sense-direction, from approximately 5.8 to 24. Additionally, it improves the ratio of the second to the first mode resonance frequency from approximately 2.2 to 10.5, which can improve survivability of the structure over a much wider bandwidth against resonance of the second mode. The new structure was fabricated by bonding two silicon-on-insulator (SOI) wafers, each containing complementary halves of the structure. This article presents the configuration details of the structure, along with analytical and finite element analysis (FEA) results to estimate deflections, stresses, modal frequencies, and mode shapes. Additionally, the MEMS fabrication process details, packaging, and test results of X-ray imaging, scanning electron microscope (SEM) imaging, natural frequency measurement using laser doppler vibrometer (LDV), sensitivity test, and so on, at die and package level are discussed.
{"title":"Investigation of a Novel Symmetric-Structure-Based MEMS Piezoresistive Accelerometer","authors":"Satyapal Singh;Vijay Kumar;Navin Kumar","doi":"10.1109/TCPMT.2025.3595152","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3595152","url":null,"abstract":"In this article, a novel symmetric-structure-based silicon microelectromechanical systems (MEMS) piezoresistive accelerometer is proposed. Compared to conventional structures based on multiple support beams and hanging-seismic-mass, the symmetric-structure not only reduces cross-axis output but also ensures lower stresses in the flexures when subjected to cross-axis acceleration inputs. It increases the ratio of the fracture acceleration limit in the cross-direction to that in the sense-direction, from approximately 5.8 to 24. Additionally, it improves the ratio of the second to the first mode resonance frequency from approximately 2.2 to 10.5, which can improve survivability of the structure over a much wider bandwidth against resonance of the second mode. The new structure was fabricated by bonding two silicon-on-insulator (SOI) wafers, each containing complementary halves of the structure. This article presents the configuration details of the structure, along with analytical and finite element analysis (FEA) results to estimate deflections, stresses, modal frequencies, and mode shapes. Additionally, the MEMS fabrication process details, packaging, and test results of X-ray imaging, scanning electron microscope (SEM) imaging, natural frequency measurement using laser doppler vibrometer (LDV), sensitivity test, and so on, at die and package level are discussed.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1868-1876"},"PeriodicalIF":3.0,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TCPMT.2025.3594505
Sumin David Joseph;Edward A. Ball
This article investigates the impact of bondwire interconnections on signal integrity in low and high millimeter-wave (mmWave) applications, emphasizing transmission degradation caused by inductive and parasitic effects. Through detailed measurements and analysis, we demonstrate that transmission loss and impedance mismatches can be effectively reduced by minimizing bondwire length and using multiple wires in parallel. Based on empirical data, we developed an electrical model of bondwire incorporating distributed inductance, capacitance, resistance $(L/C/R)$ , and transmission line characteristics. To further enhance performance, we introduce compact compensation circuits using LC structures and radial stubs optimized for both single and double bondwire configurations. Experimental validation shows that the proposed double-wire LC compensation technique significantly reduces insertion loss—from 5 to 1.5 dB and provides a return loss bandwidth from 70 to 75 GHz. The key novelty of this work lies in integrating multiple bondwires with low complexity, compact LC compensation structures, providing an effective solution for reducing insertion loss and improving impedance matching in mmWave systems. This approach offers a practical and scalable solution for improving chip-to-board and board-to-board interconnect performance in mmWave systems.
{"title":"Analysis of Bondwires and RF Compensation Circuits in E-Band","authors":"Sumin David Joseph;Edward A. Ball","doi":"10.1109/TCPMT.2025.3594505","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3594505","url":null,"abstract":"This article investigates the impact of bondwire interconnections on signal integrity in low and high millimeter-wave (mmWave) applications, emphasizing transmission degradation caused by inductive and parasitic effects. Through detailed measurements and analysis, we demonstrate that transmission loss and impedance mismatches can be effectively reduced by minimizing bondwire length and using multiple wires in parallel. Based on empirical data, we developed an electrical model of bondwire incorporating distributed inductance, capacitance, resistance <inline-formula> <tex-math>$(L/C/R)$ </tex-math></inline-formula>, and transmission line characteristics. To further enhance performance, we introduce compact compensation circuits using <italic>LC</i> structures and radial stubs optimized for both single and double bondwire configurations. Experimental validation shows that the proposed double-wire <italic>LC</i> compensation technique significantly reduces insertion loss—from 5 to 1.5 dB and provides a return loss bandwidth from 70 to 75 GHz. The key novelty of this work lies in integrating multiple bondwires with low complexity, compact <italic>LC</i> compensation structures, providing an effective solution for reducing insertion loss and improving impedance matching in mmWave systems. This approach offers a practical and scalable solution for improving chip-to-board and board-to-board interconnect performance in mmWave systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1986-1995"},"PeriodicalIF":3.0,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TCPMT.2025.3593891
Souhila Bouzerd;Laurent Dupont
This article presents and discusses a method for evaluating the initiation of a solder joint delamination in a 3-D power electronics assembly of SiC MOSFETs integrated into printed circuit board substrate to design a more efficient half bridge. This assembly requires soldering two metallic parts and addresses the integration of active chips with small dimensions compared to the larger heat-sink dimensions to operate only with a convective cooling system. This technological development is part of an effort to assess the robustness of technological choices for a new assembly model of wide bandgap components. However, the conventional methods do not effectively meet the need for detecting the initiation of solder delamination due to the optimized electrothermal assembly design. The method relies on potential difference measurements that exhibit greater sensitivity to detect the onset of solder delamination. Finite element simulations are carried out to assess the method’s sensitivity and discriminating factors, such as geometry and materials involved. Based on the numerical results, the dedicated prototypes of the assembly are developed with controlled delamination rates at the solder joint corners. The results demonstrate that this method is sensitive to detect low delamination rates compared to the traditional method. An improvement of the PCB copper design is made by adding a routing to improve the robustness and the reliability of the method sensitivity.
{"title":"A Method for Detecting the Initiation of Solder Joint Delamination in a 3-D PCB Assembly of WBG SiC MOSFET","authors":"Souhila Bouzerd;Laurent Dupont","doi":"10.1109/TCPMT.2025.3593891","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3593891","url":null,"abstract":"This article presents and discusses a method for evaluating the initiation of a solder joint delamination in a 3-D power electronics assembly of SiC MOSFETs integrated into printed circuit board substrate to design a more efficient half bridge. This assembly requires soldering two metallic parts and addresses the integration of active chips with small dimensions compared to the larger heat-sink dimensions to operate only with a convective cooling system. This technological development is part of an effort to assess the robustness of technological choices for a new assembly model of wide bandgap components. However, the conventional methods do not effectively meet the need for detecting the initiation of solder delamination due to the optimized electrothermal assembly design. The method relies on potential difference measurements that exhibit greater sensitivity to detect the onset of solder delamination. Finite element simulations are carried out to assess the method’s sensitivity and discriminating factors, such as geometry and materials involved. Based on the numerical results, the dedicated prototypes of the assembly are developed with controlled delamination rates at the solder joint corners. The results demonstrate that this method is sensitive to detect low delamination rates compared to the traditional method. An improvement of the PCB copper design is made by adding a routing to improve the robustness and the reliability of the method sensitivity.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"2041-2048"},"PeriodicalIF":3.0,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145073372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-29DOI: 10.1109/TCPMT.2025.3593614
Yue Pan;Tian Xia;Yu Mao Wu
As the integrated chip packaging technology progresses from 2.5-D to 3-D, new issues arise regarding the reliability of interconnects. The analysis of interconnect reliability is inherently multiphysics, multiscale, and large in computational scale. This article addresses these challenges by developing an electrical–thermal–mechanical co-simulation based on the discontinuous Galerkin finite-element method (DG-FEM). The governing equations for the three fields are formulated in a unified manner, enabling their effective solutions through a single DG-FEM framework. Since DG-FEM naturally supports the handling of nonconformal meshes, the mesh generation process is significantly simplified when handling multiscale models. Furthermore, a GPU parallel acceleration technique is applied to improve computational efficiency for large computational problems. The capability of the method in performing multiphysics simulations is demonstrated by several numerical examples of interconnect structures, achieving GPU speedups of over 20 times. Through simulations, detailed temperature and local stress distributions are efficiently obtained, providing critical insights into interconnect reliability.
{"title":"An Efficient Modeling Method for Multiphysics Analysis of 3-D Interconnects","authors":"Yue Pan;Tian Xia;Yu Mao Wu","doi":"10.1109/TCPMT.2025.3593614","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3593614","url":null,"abstract":"As the integrated chip packaging technology progresses from 2.5-D to 3-D, new issues arise regarding the reliability of interconnects. The analysis of interconnect reliability is inherently multiphysics, multiscale, and large in computational scale. This article addresses these challenges by developing an electrical–thermal–mechanical co-simulation based on the discontinuous Galerkin finite-element method (DG-FEM). The governing equations for the three fields are formulated in a unified manner, enabling their effective solutions through a single DG-FEM framework. Since DG-FEM naturally supports the handling of nonconformal meshes, the mesh generation process is significantly simplified when handling multiscale models. Furthermore, a GPU parallel acceleration technique is applied to improve computational efficiency for large computational problems. The capability of the method in performing multiphysics simulations is demonstrated by several numerical examples of interconnect structures, achieving GPU speedups of over 20 times. Through simulations, detailed temperature and local stress distributions are efficiently obtained, providing critical insights into interconnect reliability.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1921-1931"},"PeriodicalIF":3.0,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-25DOI: 10.1109/TCPMT.2025.3592673
Tomoaki Kashiwao;Ryo Takeda;Tomomi Ito
In recent years, white light-emitting diodes (LEDs) have gained traction in general lighting and displays owing to their energy efficiency and high performance. Zirconium dioxide (ZrO${}_{{2}}$ ) nanoparticles, characterized by high refractive indices, can significantly improve the luminous efficiency of white LEDs. When integrated into the encapsulation resin of white LED packaging (PKG), a small quantity of these nanoparticles effectively scatters the light emitted by the LED chip, thereby enhancing light extraction from the PKG. A ray-tracing simulation was employed to study the optical behavior of ZrO${}_{{2}}$ nanoparticles within white LED PKG. Subsequently, the distribution of the ZrO${}_{{2}}$ nanoparticles was optimized, and the mechanism underlying the enhanced luminosity was analyzed. The simulation results reveal that ZrO${}_{{2}}$ nanoparticles, particularly in the 50–100-nm range, significantly enhance luminosity while reducing phosphor usage in white LED manufacturing.
{"title":"Encapsulation of ZrO2 Nanoparticles for Improving Total Luminous Flux of White Light-Emitting Diodes","authors":"Tomoaki Kashiwao;Ryo Takeda;Tomomi Ito","doi":"10.1109/TCPMT.2025.3592673","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3592673","url":null,"abstract":"In recent years, white light-emitting diodes (LEDs) have gained traction in general lighting and displays owing to their energy efficiency and high performance. Zirconium dioxide (ZrO<inline-formula> <tex-math>${}_{{2}}$ </tex-math></inline-formula>) nanoparticles, characterized by high refractive indices, can significantly improve the luminous efficiency of white LEDs. When integrated into the encapsulation resin of white LED packaging (PKG), a small quantity of these nanoparticles effectively scatters the light emitted by the LED chip, thereby enhancing light extraction from the PKG. A ray-tracing simulation was employed to study the optical behavior of ZrO<inline-formula> <tex-math>${}_{{2}}$ </tex-math></inline-formula> nanoparticles within white LED PKG. Subsequently, the distribution of the ZrO<inline-formula> <tex-math>${}_{{2}}$ </tex-math></inline-formula> nanoparticles was optimized, and the mechanism underlying the enhanced luminosity was analyzed. The simulation results reveal that ZrO<inline-formula> <tex-math>${}_{{2}}$ </tex-math></inline-formula> nanoparticles, particularly in the 50–100-nm range, significantly enhance luminosity while reducing phosphor usage in white LED manufacturing.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1877-1885"},"PeriodicalIF":3.0,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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