Pub Date : 2025-01-14DOI: 10.1109/TCPMT.2024.3525141
Fang-Qian Wang;Xiao-Peng Wu;Guang-Bao Shan;Yin-Tang Yang
In recent years, due to the increase in power density and thermal accumulation, electrical and thermal reliability have become the main challenges in microsystem design, which requires rapid prediction of the electrical and thermal characteristics of a microsystem. To address these challenges, this study proposes a fast dual-cell method (FDCM) for the electrothermal coupling of 3-D microsystems. By decomposing the constitutive matrix and extracting the temperature variation parameters, the proposed method reduces the number of unknowns of temperature variation iteration, thus ensuring the calculation accuracy while significantly improving the calculation efficiency at a lower memory consumption. Compared with the finite element method (FEM) method, the calculation error of the FDCM is decreased by 1%, the calculation time is reduced by 63.70%, and the calculation memory is only 12.86% of that of the FEM. Finally, this study optimizes the layout of 3-D microsystems using the FDCM, addressing the electrothermal coupling problem.
{"title":"Electrothermal Coupling Optimization Method of a 3-D Microsystem Based on the Fast Dual-Cell Method","authors":"Fang-Qian Wang;Xiao-Peng Wu;Guang-Bao Shan;Yin-Tang Yang","doi":"10.1109/TCPMT.2024.3525141","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3525141","url":null,"abstract":"In recent years, due to the increase in power density and thermal accumulation, electrical and thermal reliability have become the main challenges in microsystem design, which requires rapid prediction of the electrical and thermal characteristics of a microsystem. To address these challenges, this study proposes a fast dual-cell method (FDCM) for the electrothermal coupling of 3-D microsystems. By decomposing the constitutive matrix and extracting the temperature variation parameters, the proposed method reduces the number of unknowns of temperature variation iteration, thus ensuring the calculation accuracy while significantly improving the calculation efficiency at a lower memory consumption. Compared with the finite element method (FEM) method, the calculation error of the FDCM is decreased by 1%, the calculation time is reduced by 63.70%, and the calculation memory is only 12.86% of that of the FEM. Finally, this study optimizes the layout of 3-D microsystems using the FDCM, addressing the electrothermal coupling problem.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"263-271"},"PeriodicalIF":2.3,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-dimensional heterogeneous integration is becoming increasingly important in advanced packaging as device functionalities expand within smaller spaces. Three-dimensional interconnects such as through silicon via (TSV)-solid–liquid interdiffusion (SLID) interconnects offer a promising approach for achieving miniaturization, high integration, and reduced power consumption. However, well-known Cu–Sn SLID-TSVs require high bonding temperatures, leading to residual stress and cracks. This research focuses on developing 3-D interconnects by using Cu–Sn–In/Co SLID-TSVs, which decrease bonding temperatures and reduce these issues. Finite element (FE) simulations qualitatively compared stress states in both SLID-TSV systems, showing lower residual stress in the Cu–Sn–In/Co SLID system than in Cu–Sn SLID. The Cu–Sn–In/Co SLID-TSV underwent microstructural analysis and reliability tests, including high-temperature storage (HTS), thermal shock (TS), and tensile strength testing. Most samples were free of voids and cracks, with a few showing minor defects along the bond line after TS. No cracks were observed inside the Si and TSVs. This indicates that adopting the Cu–Sn–In/Co system and reducing the bonding temperature to 200 °C can effectively prevent crack formations across bond lines, Si, and TSVs. Furthermore, all the samples meet the tensile strength requirements according to MIL-STD-883 method 2027.2, with the highest value observed for HTS-tested samples. Hence, low-temperature 3-D SLID-TSV interconnects were successfully demonstrated, showing strong potential for 3-D MEMS-ICs.
{"title":"Low-Temperature SLID-TSV Interconnects for 3-D (MEMS) Packaging","authors":"Fahimeh Emadi;Shenyi Liu;Vesa Vuorinen;Mervi Paulasto-Kröckel","doi":"10.1109/TCPMT.2025.3528519","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3528519","url":null,"abstract":"Three-dimensional heterogeneous integration is becoming increasingly important in advanced packaging as device functionalities expand within smaller spaces. Three-dimensional interconnects such as through silicon via (TSV)-solid–liquid interdiffusion (SLID) interconnects offer a promising approach for achieving miniaturization, high integration, and reduced power consumption. However, well-known Cu–Sn SLID-TSVs require high bonding temperatures, leading to residual stress and cracks. This research focuses on developing 3-D interconnects by using Cu–Sn–In/Co SLID-TSVs, which decrease bonding temperatures and reduce these issues. Finite element (FE) simulations qualitatively compared stress states in both SLID-TSV systems, showing lower residual stress in the Cu–Sn–In/Co SLID system than in Cu–Sn SLID. The Cu–Sn–In/Co SLID-TSV underwent microstructural analysis and reliability tests, including high-temperature storage (HTS), thermal shock (TS), and tensile strength testing. Most samples were free of voids and cracks, with a few showing minor defects along the bond line after TS. No cracks were observed inside the Si and TSVs. This indicates that adopting the Cu–Sn–In/Co system and reducing the bonding temperature to 200 °C can effectively prevent crack formations across bond lines, Si, and TSVs. Furthermore, all the samples meet the tensile strength requirements according to MIL-STD-883 method 2027.2, with the highest value observed for HTS-tested samples. Hence, low-temperature 3-D SLID-TSV interconnects were successfully demonstrated, showing strong potential for 3-D MEMS-ICs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"377-386"},"PeriodicalIF":2.3,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839082","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TCPMT.2025.3527313
Pouria Zaghari;Sourish S. Sinha;Douglas C. Hopkins;Jong Eun Ryu
Copper-filled via is a critical component of advanced electronic packaging technologies. Embedded in interposer substrate, vias provide enhanced electrical performance in 2.5-D and 3-D electronic packaging by allowing a smaller form factor. In addition to the electrical characteristics of an electronic package, its thermal and mechanical performance also depends on via geometry and the interposer material. This necessitates a co-design approach integrating thermal, mechanical, and electrical considerations. This article focuses on a numerical parametric study and multiobjective machine learning-based optimization of through-silicon via (TSV) and through-glass via (TGV). This study investigates the multidisciplinary effects of aspect ratio (AR) and pitch in the square and hexagonal array vias. Copper protrusion, thermal resistance, and electrical parasitics were used as the optimization performance indicators. An online artificial neural network (ANN) algorithm, as well as the conventional genetic algorithm (GA), was adopted to optimize the through-via designs. The parametric study demonstrated that glass substrates are more effective in reducing copper protrusion and mutual capacitance up to 47.5% and 67.6% compared to silicon. However, TSVs showed superior thermal performance. A higher AR helps minimize the copper protrusion for mechanical performance. Moreover, the thermal performance was enhanced by reducing the pitch and using hexagonal array vias. Regarding electrical performance, a high pitch and low AR are preferable to minimize electrical parasitics. Finally, a 61.3% decrease in the computation time was achieved by using an online ANN-based optimization scheme compared to GA, highlighting its potential in the optimization of high-fidelity complex electronic designs.
{"title":"Co-Design and ML-Based Optimization of Through-Via in Silicon and Glass Interposers for Electronic Packaging Applications","authors":"Pouria Zaghari;Sourish S. Sinha;Douglas C. Hopkins;Jong Eun Ryu","doi":"10.1109/TCPMT.2025.3527313","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3527313","url":null,"abstract":"Copper-filled via is a critical component of advanced electronic packaging technologies. Embedded in interposer substrate, vias provide enhanced electrical performance in 2.5-D and 3-D electronic packaging by allowing a smaller form factor. In addition to the electrical characteristics of an electronic package, its thermal and mechanical performance also depends on via geometry and the interposer material. This necessitates a co-design approach integrating thermal, mechanical, and electrical considerations. This article focuses on a numerical parametric study and multiobjective machine learning-based optimization of through-silicon via (TSV) and through-glass via (TGV). This study investigates the multidisciplinary effects of aspect ratio (AR) and pitch in the square and hexagonal array vias. Copper protrusion, thermal resistance, and electrical parasitics were used as the optimization performance indicators. An online artificial neural network (ANN) algorithm, as well as the conventional genetic algorithm (GA), was adopted to optimize the through-via designs. The parametric study demonstrated that glass substrates are more effective in reducing copper protrusion and mutual capacitance up to 47.5% and 67.6% compared to silicon. However, TSVs showed superior thermal performance. A higher AR helps minimize the copper protrusion for mechanical performance. Moreover, the thermal performance was enhanced by reducing the pitch and using hexagonal array vias. Regarding electrical performance, a high pitch and low AR are preferable to minimize electrical parasitics. Finally, a 61.3% decrease in the computation time was achieved by using an online ANN-based optimization scheme compared to GA, highlighting its potential in the optimization of high-fidelity complex electronic designs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"295-308"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TCPMT.2025.3527378
Hanqing Duan;Weijie Dong;Yongping Xie
In this article, a model for characterizing the S-parameters of periodic nonuniform microstrip lines with tabbed routing is proposed, which can calculate the corresponding scattering parameters quickly and accurately from the physical parameters. The model employs an equation-based analytical (EBA) solution, utilizing a piecewise cascade methodology and integrating numerical analysis from the finite difference time domain (FDTD) method within symmetrical repeated regions. This approach mitigates errors resulting from inadequate quasistatic conditions, thereby improving accuracy. Furthermore, the model integrates partial least squares (PLS) machine learning (ML) for correction. It leverages discrepancies between calculated and electromagnetic simulation results as learning inputs to predict model deviations under new structural parameters, thereby enhancing characterization precision. Validation against full-wave simulations confirms the model’s strong alignment and superior accuracy over the EBA solution, without compromising computational efficiency during numerical solution and model training. Moreover, the model’s accuracy is confirmed through comprehensive board fabrication and measurement experiments.
本文提出了一种用于表征具有片状布线的周期性非均匀微带线 S 参数的模型，该模型可以根据物理参数快速准确地计算出相应的散射参数。该模型采用基于方程的分析 (EBA) 解决方案，利用分段级联方法，并在对称重复区域内集成了有限差分时域 (FDTD) 方法的数值分析。这种方法可减少因准静态条件不足而产生的误差，从而提高精度。此外，该模型还集成了偏最小二乘法（PLS）机器学习（ML）来进行修正。它利用计算结果和电磁模拟结果之间的差异作为学习输入，预测新结构参数下的模型偏差，从而提高表征精度。根据全波仿真进行的验证证实，该模型与 EBA 解决方案相比，具有很强的一致性和更高的精确度，而且在数值求解和模型训练过程中不会降低计算效率。此外，该模型的准确性还通过全面的电路板制造和测量实验得到了证实。
{"title":"Characterization of S-Parameters for Nonuniform Microstrip Lines With Tabbed Routing Using Analytical-Numerical Method and Machine Learning","authors":"Hanqing Duan;Weijie Dong;Yongping Xie","doi":"10.1109/TCPMT.2025.3527378","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3527378","url":null,"abstract":"In this article, a model for characterizing the S-parameters of periodic nonuniform microstrip lines with tabbed routing is proposed, which can calculate the corresponding scattering parameters quickly and accurately from the physical parameters. The model employs an equation-based analytical (EBA) solution, utilizing a piecewise cascade methodology and integrating numerical analysis from the finite difference time domain (FDTD) method within symmetrical repeated regions. This approach mitigates errors resulting from inadequate quasistatic conditions, thereby improving accuracy. Furthermore, the model integrates partial least squares (PLS) machine learning (ML) for correction. It leverages discrepancies between calculated and electromagnetic simulation results as learning inputs to predict model deviations under new structural parameters, thereby enhancing characterization precision. Validation against full-wave simulations confirms the model’s strong alignment and superior accuracy over the EBA solution, without compromising computational efficiency during numerical solution and model training. Moreover, the model’s accuracy is confirmed through comprehensive board fabrication and measurement experiments.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"347-355"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TCPMT.2025.3527427
Ashita Victor;Muhannad S. Bakir
Wafer-scale packaging techniques pave the way for achieving high-density integration in advanced chiplet-based architectures. In this letter, a wafer-scale chiplet reconstitution technology is presented, where the key idea is to encapsulate a “sea of chiplets” in low-temperature silicon dioxide (SiO2) to form a reconstituted chiplet tier. For the demonstration of an ultrathin reconstituted-SiO2 chiplet tier, 10–20-$mu $ m-thick passive chiplets having a chiplet-to-chiplet gap of $50~mu $ m are fabricated. These passive chiplets are then encapsulated in 18–20-$mu $ m-thick silicon dioxide. However, to enable further postprocessing and fabrication of redistribution layers (RDLs) on the chiplet tiers, temporary bonding and debonding (TBDB) techniques are implemented. This letter explores different tier transfer (TBDB) techniques for the ultrathin SiO2 -chiplet tiers (<40-$mu $ m-thick). Two temporary adhesives were evaluated for this purpose: Crystalbond and double-side thermal release tape. The experimental results revealed that the Crystalbond adhesive posed several challenges, while the double-side thermal release tape allowed for a more successful transfer of the ultrathin chiplet tier.
{"title":"Tier Transfer of Ultrathin Reconstituted- SiO₂ Chiplet Tiers","authors":"Ashita Victor;Muhannad S. Bakir","doi":"10.1109/TCPMT.2025.3527427","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3527427","url":null,"abstract":"Wafer-scale packaging techniques pave the way for achieving high-density integration in advanced chiplet-based architectures. In this letter, a wafer-scale chiplet reconstitution technology is presented, where the key idea is to encapsulate a “sea of chiplets” in low-temperature silicon dioxide (SiO2) to form a reconstituted chiplet tier. For the demonstration of an ultrathin reconstituted-SiO2 chiplet tier, 10–20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick passive chiplets having a chiplet-to-chiplet gap of <inline-formula> <tex-math>$50~mu $ </tex-math></inline-formula>m are fabricated. These passive chiplets are then encapsulated in 18–20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick silicon dioxide. However, to enable further postprocessing and fabrication of redistribution layers (RDLs) on the chiplet tiers, temporary bonding and debonding (TBDB) techniques are implemented. This letter explores different tier transfer (TBDB) techniques for the ultrathin SiO2 -chiplet tiers (<40-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick). Two temporary adhesives were evaluated for this purpose: Crystalbond and double-side thermal release tape. The experimental results revealed that the Crystalbond adhesive posed several challenges, while the double-side thermal release tape allowed for a more successful transfer of the ultrathin chiplet tier.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"432-434"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-07DOI: 10.1109/TCPMT.2025.3526591
Zhonglin Jiang;Zequn Wang
Through silicon via (TSV) technology has been widely employed as a promising 3-D packaging technology to achieve significant reduction in device dimensions. Due to the existence of uncertainty in device dimension and material properties, significant thermal stress can be generated in TSV to detartrate the performance of TSV-based 3-D chips. This article presents an adaptive machine-learning-enabled evolutionary optimization approach for the reliability-based design of TSV structures under uncertainty. In detail, a finite element model is developed for TSV structures under thermal cycling loads to determine its thermomechanical performance. A Kriging model is then utilized to establish as a surrogate to predict the maximum thermal stress. With the surrogate model, an adaptive machine-learning-enabled efficient evolutionary optimization (aMLEO) approach is proposed to reduce the volume of TSV structures while enhancing their reliability.
{"title":"Adaptive Machine Learning-Enabled Evolutionary Optimization for Reliability-Based Design of Through Silicon Via (TSV) Structures Under Uncertainty","authors":"Zhonglin Jiang;Zequn Wang","doi":"10.1109/TCPMT.2025.3526591","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3526591","url":null,"abstract":"Through silicon via (TSV) technology has been widely employed as a promising 3-D packaging technology to achieve significant reduction in device dimensions. Due to the existence of uncertainty in device dimension and material properties, significant thermal stress can be generated in TSV to detartrate the performance of TSV-based 3-D chips. This article presents an adaptive machine-learning-enabled evolutionary optimization approach for the reliability-based design of TSV structures under uncertainty. In detail, a finite element model is developed for TSV structures under thermal cycling loads to determine its thermomechanical performance. A Kriging model is then utilized to establish as a surrogate to predict the maximum thermal stress. With the surrogate model, an adaptive machine-learning-enabled efficient evolutionary optimization (aMLEO) approach is proposed to reduce the volume of TSV structures while enhancing their reliability.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"387-398"},"PeriodicalIF":2.3,"publicationDate":"2025-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through-silicon via (TSV) has attracted much attention due to its numerous advantages, including high-density interconnection, low power consumption, and wide bandwidth. When signals are transmitted in TSV array, however, significant crosstalk issues may arise, negatively affecting timing and signal integrity. In this article, the distributions of signal and ground TSVs in an array are optimized by conducting co-simulation of ANSYS Q2D and MATLAB based on genetic algorithm (GA). The optimization aims at reducing the crosstalk in the array. Compared with the reference distribution scheme, the results indicate that the optimized distribution of TSV array can effectively reduce both near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The proposed method is of great significance in solving the crosstalk problem, offering feasible solutions for the design of TSV array.
{"title":"Distribution Optimization of Through-Silicon Via (TSV) Array Based on Genetic Algorithm","authors":"Jia-Yi Ju;Qi Qiang Liu;Peng Zhang;Jing Wang;Peng Zhao;Xuan Lin;Chen-Yang Yao;Wen-Sheng Zhao","doi":"10.1109/TCPMT.2025.3526829","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3526829","url":null,"abstract":"Through-silicon via (TSV) has attracted much attention due to its numerous advantages, including high-density interconnection, low power consumption, and wide bandwidth. When signals are transmitted in TSV array, however, significant crosstalk issues may arise, negatively affecting timing and signal integrity. In this article, the distributions of signal and ground TSVs in an array are optimized by conducting co-simulation of ANSYS Q2D and MATLAB based on genetic algorithm (GA). The optimization aims at reducing the crosstalk in the array. Compared with the reference distribution scheme, the results indicate that the optimized distribution of TSV array can effectively reduce both near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The proposed method is of great significance in solving the crosstalk problem, offering feasible solutions for the design of TSV array.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"399-409"},"PeriodicalIF":2.3,"publicationDate":"2025-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-07DOI: 10.1109/TCPMT.2025.3527171
{"title":"2024 Index IEEE Transactions on Components, Packaging and Manufacturing Technology Vol. 14","authors":"","doi":"10.1109/TCPMT.2025.3527171","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3527171","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2407-2463"},"PeriodicalIF":2.3,"publicationDate":"2025-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10832478","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-03DOI: 10.1109/TCPMT.2024.3511826
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2024.3511826","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3511826","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10823081","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-03DOI: 10.1109/TCPMT.2024.3511822
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2024.3511822","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3511822","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10821527","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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