Pub Date : 2025-04-07DOI: 10.1109/TCPMT.2025.3558701
Ioannis Mantis;Kapil Kumar Gupta;Rajan Ambat
In the presented work, the accumulative effect of different manufacturing steps of printed circuit board (PCB) on conformal coating performance is evaluated. An interdigitated comb pattern on an FR-4 board was used as a test PCB. Manufacturing processes included base test PCB produced by three different manufacturers (Man) incorporating copper-clad lamination (CCL) and hot air solder leveling (HASL) steps. In addition, test boards underwent typical wave solder and selective mini-wave steps. Commercial co-polymer polyurethane/polyacrylate and urethane acrylate conformal coatings were applied on test boards before as well as after soldering process. The study aims to evaluate induced contamination on the PCB surface after these manufacturing steps and the effect of PCB surface cleanliness on the protection performance of conformal coating under humidity. The results revealed chloride residues prior to soldering on the PCB surface with variations across Man-1 ($0.2~mu $ g/cm2), Man-2 ($0.4~mu $ g/cm2), and Man-3 ($0.8~mu $ g/cm2). In surface insulation resistance (SIR) measurements under humidity exposure, Man-3 exhibited 100% failure caused by dendrite formation, with resistance levels consistently over a decade lower than Man-1, highlighting the quality of the base PCB materials as a major factor for humidity-related issues. Equal importance was found regarding different wave soldering methods and coatings. However, the initial contamination present dominated over subsequent manufacturing steps with the highest chloride contamination resulting in up to one decade difference depending on the flux and coating chemistries.
{"title":"Effect of PCB Manufacturing Process Step-Related Cleanliness on Performance of Conformal Coating","authors":"Ioannis Mantis;Kapil Kumar Gupta;Rajan Ambat","doi":"10.1109/TCPMT.2025.3558701","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3558701","url":null,"abstract":"In the presented work, the accumulative effect of different manufacturing steps of printed circuit board (PCB) on conformal coating performance is evaluated. An interdigitated comb pattern on an FR-4 board was used as a test PCB. Manufacturing processes included base test PCB produced by three different manufacturers (Man) incorporating copper-clad lamination (CCL) and hot air solder leveling (HASL) steps. In addition, test boards underwent typical wave solder and selective mini-wave steps. Commercial co-polymer polyurethane/polyacrylate and urethane acrylate conformal coatings were applied on test boards before as well as after soldering process. The study aims to evaluate induced contamination on the PCB surface after these manufacturing steps and the effect of PCB surface cleanliness on the protection performance of conformal coating under humidity. The results revealed chloride residues prior to soldering on the PCB surface with variations across Man-1 (<inline-formula> <tex-math>$0.2~mu $ </tex-math></inline-formula>g/cm<sup>2</sup>), Man-2 (<inline-formula> <tex-math>$0.4~mu $ </tex-math></inline-formula>g/cm<sup>2</sup>), and Man-3 (<inline-formula> <tex-math>$0.8~mu $ </tex-math></inline-formula>g/cm<sup>2</sup>). In surface insulation resistance (SIR) measurements under humidity exposure, Man-3 exhibited 100% failure caused by dendrite formation, with resistance levels consistently over a decade lower than Man-1, highlighting the quality of the base PCB materials as a major factor for humidity-related issues. Equal importance was found regarding different wave soldering methods and coatings. However, the initial contamination present dominated over subsequent manufacturing steps with the highest chloride contamination resulting in up to one decade difference depending on the flux and coating chemistries.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1367-1375"},"PeriodicalIF":2.3,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/TCPMT.2025.3557270
Ming-Lang Tseng;Nima E. Gorji
X-ray diffraction (XRD) mapping is a nondestructive metrology technique that enables the reconstruction of warpage induced on a silicon wafer through thermomechanical stress. Here, we mapped the wafer’s warpage using a methodology based on a series of line scans in the x- and y-directions and at different 90° rotations of the same sample. These line scans collect rocking curves (RCs) from the wafer’s surface, recording the diffraction angle ($omega $ ) deviated from the Bragg angle due to surface misorientation. The surface warpage reflects in XRD measurements by inducing a difference between the measured diffraction angle and the reference Bragg angle ($omega - omega _{0}$ ) and RC broadening full-width at half-maximum (FWHM). By collecting and integrating the RCs and FWHM broadening from the whole surface and multiple rotations of the wafer, we could generate 3-D maps of the surface function $f(x)$ and the angular misorientation (warpage). The warpage exhibits a convex shape, aligning with optical profilometry measurements reported in the literature. The lab-based XRD imaging (XRDI) has the potential to be developed to map the wafer’s warpage in a shorter time and in situ, as can be perfectly performed in synchrotron radiation source.
{"title":"Metrology of Warpage in Silicon Wafers Using X-Ray Diffraction Mapping","authors":"Ming-Lang Tseng;Nima E. Gorji","doi":"10.1109/TCPMT.2025.3557270","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557270","url":null,"abstract":"X-ray diffraction (XRD) mapping is a nondestructive metrology technique that enables the reconstruction of warpage induced on a silicon wafer through thermomechanical stress. Here, we mapped the wafer’s warpage using a methodology based on a series of line scans in the <italic>x</i>- and <italic>y</i>-directions and at different 90° rotations of the same sample. These line scans collect rocking curves (<italic>RC</i>s) from the wafer’s surface, recording the diffraction angle (<inline-formula> <tex-math>$omega $ </tex-math></inline-formula>) deviated from the Bragg angle due to surface misorientation. The surface warpage reflects in XRD measurements by inducing a difference between the measured diffraction angle and the reference Bragg angle (<inline-formula> <tex-math>$omega - omega _{0}$ </tex-math></inline-formula>) and <italic>RC</i> broadening full-width at half-maximum (FWHM). By collecting and integrating the <italic>RC</i>s and FWHM broadening from the whole surface and multiple rotations of the wafer, we could generate 3-D maps of the surface function <inline-formula> <tex-math>$f(x)$ </tex-math></inline-formula> and the angular misorientation (warpage). The warpage exhibits a convex shape, aligning with optical profilometry measurements reported in the literature. The lab-based XRD imaging (XRDI) has the potential to be developed to map the wafer’s warpage in a shorter time and in situ, as can be perfectly performed in synchrotron radiation source.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1523-1528"},"PeriodicalIF":2.3,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/TCPMT.2025.3557461
Qi Zhang;Yazi Cao;Mingcong Zheng;Shichang Chen;Gaofeng Wang
On-chip bandpass filter (BPF) designs with high out-of-band rejection are proposed by virtue of 3-D glass-based advanced packaging technology. The proposed BPF design employs multiple coupling cells based on a combination of new mixed 2-D and 3-D coupling structures. It can generate multiple transmission zeros (TZs) and transmission poles (TPs). With these generated TZs, the out-of-band rejection of the proposed BPF designs can be greatly improved. The equivalent circuit model is developed and used for theoretical analysis. To prove the concept, two BPFs are designed and fabricated using 3-D glass-based advanced packaging technology. These two fabricated BPFs have center frequencies of 6.55 and 6.2 GHz and fractional bandwidths (FBWs) of 10.69% and 8%, respectively. These two BPFs can achieve insertion losses lower than 2.5 and 2.9 dB, return losses better than 10 and 13 dB, and more than 20-dB rejection up to 16.15 and 17.8 GHz. The sizes of the two BPFs are $2.1times 2.0times 0.35$ mm and $2.3times 4.3times 0.35$ mm. The simulation and measured results show good consistency.
{"title":"Design of On-Chip Bandpass Filters With Mixed 2-D and 3-D Coupling Structures Using 3-D Glass-Based Advanced Packaging Technology","authors":"Qi Zhang;Yazi Cao;Mingcong Zheng;Shichang Chen;Gaofeng Wang","doi":"10.1109/TCPMT.2025.3557461","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557461","url":null,"abstract":"On-chip bandpass filter (BPF) designs with high out-of-band rejection are proposed by virtue of 3-D glass-based advanced packaging technology. The proposed BPF design employs multiple coupling cells based on a combination of new mixed 2-D and 3-D coupling structures. It can generate multiple transmission zeros (TZs) and transmission poles (TPs). With these generated TZs, the out-of-band rejection of the proposed BPF designs can be greatly improved. The equivalent circuit model is developed and used for theoretical analysis. To prove the concept, two BPFs are designed and fabricated using 3-D glass-based advanced packaging technology. These two fabricated BPFs have center frequencies of 6.55 and 6.2 GHz and fractional bandwidths (FBWs) of 10.69% and 8%, respectively. These two BPFs can achieve insertion losses lower than 2.5 and 2.9 dB, return losses better than 10 and 13 dB, and more than 20-dB rejection up to 16.15 and 17.8 GHz. The sizes of the two BPFs are <inline-formula> <tex-math>$2.1times 2.0times 0.35$ </tex-math></inline-formula>mm and <inline-formula> <tex-math>$2.3times 4.3times 0.35$ </tex-math></inline-formula>mm. The simulation and measured results show good consistency.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1462-1467"},"PeriodicalIF":2.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Novel package-embedded inductors utilizing a dual-core spiral topology, designed for improved performance in integrated power delivery systems, are presented in this article. The proposed inductor features a simple fabrication process, gapped magnetic cores for stable performance across varying operating conditions, and overlapping spiral windings in adjacent layers, achieving high inductance density. The proposed topology consists of a spiral-shaped conductor winding layer sandwiched between two magnetic core layers. The conductor and insulating dielectric layers separate the cores and act as an air gap for the magnetic flux of the spiral inductor. The air gap causes an increase in the saturation current performance of the inductor. In addition to the single spiral winding, two advanced spiral inductor configurations, namely, two spiral windings in series and parallel, are explored. To enable design, a physical model and analytical monomial expressions are provided for inductance calculation. To evaluate the performance of these designs, three inductor samples are fabricated with two different magnetic core materials and air gaps. Overall, package-embedded dual-core spiral inductors with a performance of 115-nH inductance with 5-A saturation current and 330-nH inductance with 3.5A saturation current, occupying a 9-$text {mm}^{2}$ area and having efficiencies ranging from 75% to 80%, are demonstrated.
{"title":"Design and Demonstration of Dual-Core Spiral Package-Embedded Inductors for Integrated Voltage Regulators","authors":"Venkatesh Avula;Prahalad Murali;Madhavan Swaminathan","doi":"10.1109/TCPMT.2025.3557745","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557745","url":null,"abstract":"Novel package-embedded inductors utilizing a dual-core spiral topology, designed for improved performance in integrated power delivery systems, are presented in this article. The proposed inductor features a simple fabrication process, gapped magnetic cores for stable performance across varying operating conditions, and overlapping spiral windings in adjacent layers, achieving high inductance density. The proposed topology consists of a spiral-shaped conductor winding layer sandwiched between two magnetic core layers. The conductor and insulating dielectric layers separate the cores and act as an air gap for the magnetic flux of the spiral inductor. The air gap causes an increase in the saturation current performance of the inductor. In addition to the single spiral winding, two advanced spiral inductor configurations, namely, two spiral windings in series and parallel, are explored. To enable design, a physical model and analytical monomial expressions are provided for inductance calculation. To evaluate the performance of these designs, three inductor samples are fabricated with two different magnetic core materials and air gaps. Overall, package-embedded dual-core spiral inductors with a performance of 115-nH inductance with 5-A saturation current and 330-nH inductance with 3.5A saturation current, occupying a 9-<inline-formula> <tex-math>$text {mm}^{2}$ </tex-math></inline-formula> area and having efficiencies ranging from 75% to 80%, are demonstrated.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1275-1283"},"PeriodicalIF":2.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-03DOI: 10.1109/TCPMT.2025.3557411
Hang Qian;De-Wei Zhang;Qing Liu;Xi Wang;Xiao-Ming Li;Hong-Hui Xu
In this letter, the novel low-loss and reduced-size single- and dual-mode (S-DM) slow wave rectangular patch resonators (SWRPRs) are proposed based on a hybrid capacitive–inductive-load array (HCILA). The SWRPRs are analyzed in detail, and a highly selective DM two-pole quasi-elliptic bandpass filter (BPF) is proposed. The in-band insertion loss (IL) and size of the BPF are significantly reduced due to the use of HCILA. Three- and four-pole BPFs are realized by S-DM SWRPRs, and the introduced additional finite transmission zero (FTZ) can be efficiently controlled by phase coupling. A four-pole BPF is designed, fabricated, and measured for the demonstration. Results indicate that the proposed patch BPF offers the benefits of reduced size, high selectivity, and low loss, thereby expanding the potential applications of patch circuits.
{"title":"High-Selectivity Bandpass Filters With Low Loss and Reduced Size Based on HCILA Slow Wave Technology Encapsulated in Patch Cavities","authors":"Hang Qian;De-Wei Zhang;Qing Liu;Xi Wang;Xiao-Ming Li;Hong-Hui Xu","doi":"10.1109/TCPMT.2025.3557411","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557411","url":null,"abstract":"In this letter, the novel low-loss and reduced-size single- and dual-mode (S-DM) slow wave rectangular patch resonators (SWRPRs) are proposed based on a hybrid capacitive–inductive-load array (HCILA). The SWRPRs are analyzed in detail, and a highly selective DM two-pole quasi-elliptic bandpass filter (BPF) is proposed. The in-band insertion loss (IL) and size of the BPF are significantly reduced due to the use of HCILA. Three- and four-pole BPFs are realized by S-DM SWRPRs, and the introduced additional finite transmission zero (FTZ) can be efficiently controlled by phase coupling. A four-pole BPF is designed, fabricated, and measured for the demonstration. Results indicate that the proposed patch BPF offers the benefits of reduced size, high selectivity, and low loss, thereby expanding the potential applications of patch circuits.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 6","pages":"1376-1379"},"PeriodicalIF":2.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article details the design and manufacturing process of a compact module fed through a transition between a grounded coplanar waveguide (GCPW) input line and an air-filled (AF) waveguide integrated into the substrate. This waveguide feeds a micromachined horn antenna. The developed technology is based on the micromachining of an AF waveguide on a first substrate and a horn antenna on a second one. These two substrates are then assembled by a thermal diffusion process, which allows for creating an electrically conductive bonding interface. The novelty of this work relies in the use of this innovative technological process for the realization of millimeter-wave (mm-wave) subsystems. Furthermore, the developed technology enables the creation of high-performance components utilizing AF substrate integrated waveguides (AF-SIWs). This approach effectively addresses the challenges associated with transferring, integrating, and reducing costs often encountered in high-frequency systems development. The resulting device forms a highly integrated, low-cost, yet electrically performant mm-wave module entirely manufactured with a printed circuit board (PCB) process. The manufactured prototype operates at V-band, exhibiting a bandwidth of 3.1% and a maximum gain of 6.4 dBi.
{"title":"Printed Circuit Board (PCB)-Integrated Millimeter Module Composed of a Horn Antenna Fed Through a Grounded Coplanar Waveguide","authors":"Hassan Bouazzaoui;Benjamin Potelon;Cedric Quendo;Rozenn Allanic;Lucien Traon","doi":"10.1109/TCPMT.2025.3557708","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557708","url":null,"abstract":"This article details the design and manufacturing process of a compact module fed through a transition between a grounded coplanar waveguide (GCPW) input line and an air-filled (AF) waveguide integrated into the substrate. This waveguide feeds a micromachined horn antenna. The developed technology is based on the micromachining of an AF waveguide on a first substrate and a horn antenna on a second one. These two substrates are then assembled by a thermal diffusion process, which allows for creating an electrically conductive bonding interface. The novelty of this work relies in the use of this innovative technological process for the realization of millimeter-wave (mm-wave) subsystems. Furthermore, the developed technology enables the creation of high-performance components utilizing AF substrate integrated waveguides (AF-SIWs). This approach effectively addresses the challenges associated with transferring, integrating, and reducing costs often encountered in high-frequency systems development. The resulting device forms a highly integrated, low-cost, yet electrically performant mm-wave module entirely manufactured with a printed circuit board (PCB) process. The manufactured prototype operates at V-band, exhibiting a bandwidth of 3.1% and a maximum gain of 6.4 dBi.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1494-1501"},"PeriodicalIF":2.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1109/TCPMT.2025.3557232
Ye Yang;Kelly E. Lahaie;Tiwei Wei
Glass substrates offer significant advantages over current organic substrate, particularly in high-density, high-performance chip packaging for data-intensive applications such as artificial intelligence (AI). Glass with ultralow flatness enhances the depth of focus in lithography, which helps pattern precisely at advanced metal interconnects. In addition, their superior thermal stability minimizes pattern distortion, and their outstanding mechanical stability supports ultralarge package sizes. These exceptional dimensional stability properties facilitate precise layer-to-layer interconnect alignment, ultimately enabling glass substrates to achieve ten times higher interconnect density compared to organic substrates. However, fabricating high-density, small-diameter, high-aspect ratio (AR) through-glass vias (TGVs) remains a significant challenge. The current state-of-the-art technology for vertical TGVs achieves an AR of 12, with a via diameter of $30~mu $ m. In this work, we present the first demonstration of straight TGVs with 20-$mu $ m diameters on 300-$mu $ m thick borosilicate glass, achieving a record-high AR of 15. Thanks to the low large-area packaging cost, low thermal expansion coefficient, excellent thermal stability, and low electrical dissipation in high-frequency operation, borosilicate is chosen as the glass substrate in our research. For straight, high AR TGVs, this study explores a double-sided seed layer enhancement (SLE) approach using electroless deposition to reinforce the seed layer, combined with an electroplating strategy to produce void-free, fully filled straight TGVs metal interconnects. The parameter study of the SLE process provides valuable insights and guidelines for fabricating high AR TGVs for future high interconnect density 3-D integration systems.
{"title":"Double-Sided Copper Filling of Small Diameter, High-Aspect Ratio Through-Glass Vias in High-Density Glass Interposers","authors":"Ye Yang;Kelly E. Lahaie;Tiwei Wei","doi":"10.1109/TCPMT.2025.3557232","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557232","url":null,"abstract":"Glass substrates offer significant advantages over current organic substrate, particularly in high-density, high-performance chip packaging for data-intensive applications such as artificial intelligence (AI). Glass with ultralow flatness enhances the depth of focus in lithography, which helps pattern precisely at advanced metal interconnects. In addition, their superior thermal stability minimizes pattern distortion, and their outstanding mechanical stability supports ultralarge package sizes. These exceptional dimensional stability properties facilitate precise layer-to-layer interconnect alignment, ultimately enabling glass substrates to achieve ten times higher interconnect density compared to organic substrates. However, fabricating high-density, small-diameter, high-aspect ratio (AR) through-glass vias (TGVs) remains a significant challenge. The current state-of-the-art technology for vertical TGVs achieves an AR of 12, with a via diameter of <inline-formula> <tex-math>$30~mu $ </tex-math></inline-formula>m. In this work, we present the first demonstration of straight TGVs with 20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m diameters on 300-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m thick borosilicate glass, achieving a record-high AR of 15. Thanks to the low large-area packaging cost, low thermal expansion coefficient, excellent thermal stability, and low electrical dissipation in high-frequency operation, borosilicate is chosen as the glass substrate in our research. For straight, high AR TGVs, this study explores a double-sided seed layer enhancement (SLE) approach using electroless deposition to reinforce the seed layer, combined with an electroplating strategy to produce void-free, fully filled straight TGVs metal interconnects. The parameter study of the SLE process provides valuable insights and guidelines for fabricating high AR TGVs for future high interconnect density 3-D integration systems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1529-1537"},"PeriodicalIF":2.3,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1109/TCPMT.2025.3557118
Aleksandr A. Vlasov;Topi Uusitalo;Evgenii Lepukhov;Jukka Viheriälä;Mircea Guina
The modern processes for photonic integration impose stringent demands on the design and functionality of high precision bonding assembly setups. In this study, we present the development of a laser-assisted bonding (LAB) setup employing bottom irradiation/illumination architectures. The main goal is to demonstrate through-silicon imaging capability enabling alignment of photonic waveguides during the LAB process. The imaging is achieved with a novel optical set-up used also for the simultaneous irradiation laser beam delivery. A proof-of-concept LAB integration of a III/V chip to silicon photonic (SiPh) integrated circuit is demonstrated.
{"title":"Optical Setup for Laser-Assisted Bonding With Through-Silicon Microscopy Capabilities","authors":"Aleksandr A. Vlasov;Topi Uusitalo;Evgenii Lepukhov;Jukka Viheriälä;Mircea Guina","doi":"10.1109/TCPMT.2025.3557118","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3557118","url":null,"abstract":"The modern processes for photonic integration impose stringent demands on the design and functionality of high precision bonding assembly setups. In this study, we present the development of a laser-assisted bonding (LAB) setup employing bottom irradiation/illumination architectures. The main goal is to demonstrate through-silicon imaging capability enabling alignment of photonic waveguides during the LAB process. The imaging is achieved with a novel optical set-up used also for the simultaneous irradiation laser beam delivery. A proof-of-concept LAB integration of a III/V chip to silicon photonic (SiPh) integrated circuit is demonstrated.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"885-893"},"PeriodicalIF":2.3,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947525","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1109/TCPMT.2025.3556594
Jie Deng;Pascal Burasa;Ke Wu
In this work, a microwave (MW) and terahertz (THz) composite waveguide coupler for multiband wireless systems is proposed and demonstrated. Such a very large frequency ratio (more than $20times $ ) of the proposed coupler is made possible thanks to a composite waveguide technique where the center strip of a coplanar waveguide (CPW) is replaced by a substrate-integrated waveguide (SIW) block. In this way, the dual-mode operation, i.e., quasi-TEM mode and TE10 mode, can be enabled simultaneously at different frequencies. In addition, by adjusting the SIW width, the operating frequency of the quasi-TEM mode and the TE10 mode can be reassigned. All the advantages known for CPW couplers and SIW couplers are inherited in the proposed waveguide coupler. To validate this scheme, experimental prototypes are developed and fabricated on a thin-film miniature hybrid MW-integrated circuit (MHMIC) process. Measured results confirm the good THz performance as well as MW performance.
{"title":"Unified Microwave Terahertz Waveguide Coupler for Multiband Wireless Applications","authors":"Jie Deng;Pascal Burasa;Ke Wu","doi":"10.1109/TCPMT.2025.3556594","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3556594","url":null,"abstract":"In this work, a microwave (MW) and terahertz (THz) composite waveguide coupler for multiband wireless systems is proposed and demonstrated. Such a very large frequency ratio (more than <inline-formula> <tex-math>$20times $ </tex-math></inline-formula>) of the proposed coupler is made possible thanks to a composite waveguide technique where the center strip of a coplanar waveguide (CPW) is replaced by a substrate-integrated waveguide (SIW) block. In this way, the dual-mode operation, i.e., quasi-TEM mode and TE<sub>10</sub> mode, can be enabled simultaneously at different frequencies. In addition, by adjusting the SIW width, the operating frequency of the quasi-TEM mode and the TE<sub>10</sub> mode can be reassigned. All the advantages known for CPW couplers and SIW couplers are inherited in the proposed waveguide coupler. To validate this scheme, experimental prototypes are developed and fabricated on a thin-film miniature hybrid MW-integrated circuit (MHMIC) process. Measured results confirm the good THz performance as well as MW performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1032-1043"},"PeriodicalIF":2.3,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1109/TCPMT.2025.3556254
Hanyong Wang;Yongqiang Wang;Kaixue Ma
In this article, the transmission characteristics of metal integrated suspended line (MISL) technology are studied which is verified by the thru-reflect-line (TRL) de-embedding method. In addition, practical design guidelines for MISL circuits are provided. A 3-D T-junction power-dividing network is introduced. Furthermore, a 3-D Gysel power-dividing network is designed based on the proposed T-junction power-dividing network. Both networks exhibit low-loss performance. They also have a higher power handling capability (PHC) than traditional printed circuit board (PCB). In contrast to waveguide circuits, they utilize multilayer metal stacking, have the characteristics of quasi-planar circuits, and reduce the manufacturing cost. Moreover, compared with the substrate-integrated suspended line (SISL) circuits, the MISL technology reduces the number of circuit layers by combining computer numerical control (CNC) machining with laser and etching technologies, simplifying assembly processes.
{"title":"Three-Dimensional Low-Loss Power-Dividing Networks Based on Metal Integrated Suspended Line (MISL) for High Power Applications","authors":"Hanyong Wang;Yongqiang Wang;Kaixue Ma","doi":"10.1109/TCPMT.2025.3556254","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3556254","url":null,"abstract":"In this article, the transmission characteristics of metal integrated suspended line (MISL) technology are studied which is verified by the thru-reflect-line (TRL) de-embedding method. In addition, practical design guidelines for MISL circuits are provided. A 3-D T-junction power-dividing network is introduced. Furthermore, a 3-D Gysel power-dividing network is designed based on the proposed T-junction power-dividing network. Both networks exhibit low-loss performance. They also have a higher power handling capability (PHC) than traditional printed circuit board (PCB). In contrast to waveguide circuits, they utilize multilayer metal stacking, have the characteristics of quasi-planar circuits, and reduce the manufacturing cost. Moreover, compared with the substrate-integrated suspended line (SISL) circuits, the MISL technology reduces the number of circuit layers by combining computer numerical control (CNC) machining with laser and etching technologies, simplifying assembly processes.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 7","pages":"1479-1493"},"PeriodicalIF":2.3,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144581706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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