Pub Date : 2024-10-01DOI: 10.1109/TCPMT.2024.3471661
Bobi Shi;Yi Zhou;Haofeng Sun;Thong Nguyen;José E. Schutt-Ainé
Due to the rapid expansion of high-speed systems and the escalating complexity of circuits in recent decades, relying on linearity and applying the superposition concept in high-speed signaling systems results in an underestimation of the influence of nonlinear effects within circuits. Consequently, the traditional fast simulation method, which assumes linearity, is no longer adequate for accurately analyzing high-speed link nonlinear systems. Therefore, a fast and accurate statistical eye diagram analysis dedicated to nonlinear systems is proposed. The proposed method uses the Volterra-Wiener model identification to decompose the system into a linear time-invariant (LTI) system and a static nonlinear system represented by the polynomial function. The 2-D probability density function (pdf) or statistical eye diagram of the LTI system is estimated by the direct statistical analysis of the single-bit response (SBR). Subsequently, the nonlinear statistical eye is estimated by applying nonlinear density transformation with polynomial-based weights. The eye height (EH) and eye width (EW) are determined based on the voltage pdf and time pdf using statistical information. The accuracy and efficiency of the proposed method are verified using three examples: the ideal nonlinearity Wiener model, the differential fin field-effect transistor (FinFET) buffer, and the high-speed link with nonlinear equalization.
{"title":"Statistical Method for Eye Diagram Simulation in High-Speed Link Nonlinear System Applications","authors":"Bobi Shi;Yi Zhou;Haofeng Sun;Thong Nguyen;José E. Schutt-Ainé","doi":"10.1109/TCPMT.2024.3471661","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3471661","url":null,"abstract":"Due to the rapid expansion of high-speed systems and the escalating complexity of circuits in recent decades, relying on linearity and applying the superposition concept in high-speed signaling systems results in an underestimation of the influence of nonlinear effects within circuits. Consequently, the traditional fast simulation method, which assumes linearity, is no longer adequate for accurately analyzing high-speed link nonlinear systems. Therefore, a fast and accurate statistical eye diagram analysis dedicated to nonlinear systems is proposed. The proposed method uses the Volterra-Wiener model identification to decompose the system into a linear time-invariant (LTI) system and a static nonlinear system represented by the polynomial function. The 2-D probability density function (pdf) or statistical eye diagram of the LTI system is estimated by the direct statistical analysis of the single-bit response (SBR). Subsequently, the nonlinear statistical eye is estimated by applying nonlinear density transformation with polynomial-based weights. The eye height (EH) and eye width (EW) are determined based on the voltage pdf and time pdf using statistical information. The accuracy and efficiency of the proposed method are verified using three examples: the ideal nonlinearity Wiener model, the differential fin field-effect transistor (FinFET) buffer, and the high-speed link with nonlinear equalization.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"2050-2061"},"PeriodicalIF":2.3,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TCPMT.2024.3470796
Huajiao Shen;Fanyi Meng;Yongqiang Wang;Kaixue Ma
This article proposes a slow wave metal-integrated coplanar waveguide (MICPW) with low loss and self-packaging. Since almost no substrate is used for the MICPW, there is almost no dielectric loss. The signal trace of the MICPW is embedded inside the multilayer metal boards, the overall circuit is self-packaged and there is almost no radiation loss. The slow wave effect is generated by using the shunt stub. The proposed slow wave MICPW is utilized to design compact branch-line couplers. Two types of supporting structures for the suspended metal lines are presented. Two design cases operating at 3.5 and 1.8 GHz are implemented, and the core circuit areas are $0.13lambda $ g $times 0.26lambda $ g and $0.14lambda $ g $times 0.17lambda $ g, which shows a size reduction of 46% and 62% compared to the traditional counterparts. The measured loss percentages are only 3% and 1.14%, which are much smaller than that of the other reported works.
提出了一种低损耗、自封装的慢波金属集成共面波导（MICPW）。由于MICPW几乎不使用衬底，因此几乎没有介电损耗。MICPW的信号走线嵌入多层金属板内，整体电路自封装，几乎没有辐射损耗。慢波效应是通过使用分流管产生的。所提出的慢波MICPW用于设计紧凑的分支线耦合器。提出了两种悬吊金属线的支撑结构。实现了两种工作在3.5 GHz和1.8 GHz的设计案例，核心电路面积分别为$0.13lambda $ g $ × 0.26lambda $ g和$0.14lambda $ g $ × 0.17lambda $ g，与传统电路相比，尺寸分别减小了46%和62%。实测损失率仅为3%和1.14%，远低于其他已报道的作品。
{"title":"Self-Packaged Slow Wave Metal-Integrated Coplanar Waveguide (MICPW) for Compact Branch-Line Coupler Design","authors":"Huajiao Shen;Fanyi Meng;Yongqiang Wang;Kaixue Ma","doi":"10.1109/TCPMT.2024.3470796","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3470796","url":null,"abstract":"This article proposes a slow wave metal-integrated coplanar waveguide (MICPW) with low loss and self-packaging. Since almost no substrate is used for the MICPW, there is almost no dielectric loss. The signal trace of the MICPW is embedded inside the multilayer metal boards, the overall circuit is self-packaged and there is almost no radiation loss. The slow wave effect is generated by using the shunt stub. The proposed slow wave MICPW is utilized to design compact branch-line couplers. Two types of supporting structures for the suspended metal lines are presented. Two design cases operating at 3.5 and 1.8 GHz are implemented, and the core circuit areas are <inline-formula> <tex-math>$0.13lambda $ </tex-math></inline-formula>g <inline-formula> <tex-math>$times 0.26lambda $ </tex-math></inline-formula>g and <inline-formula> <tex-math>$0.14lambda $ </tex-math></inline-formula>g <inline-formula> <tex-math>$times 0.17lambda $ </tex-math></inline-formula>g, which shows a size reduction of 46% and 62% compared to the traditional counterparts. The measured loss percentages are only 3% and 1.14%, which are much smaller than that of the other reported works.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"196-205"},"PeriodicalIF":2.3,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1109/TCPMT.2024.3467274
Meng-Kai Shih;Tang-Yuan Chen;Bing-Yuan Huang;Cheng-Tang Pan;Chen-Chao Wang;C. P. Hung
The 2.5-D integrated circuit (2.5-D IC) packages, in which multiple dies or chips are integrated side-by-side on a single interposer, play a crucial role in meeting the high bandwidth and high-performance requirements of merging applications, such as high-performance computing (HPC) and artificial intelligence (AI). However, the high power density in such packages leads to hot spot issues, which raise serious concerns regarding thermal control and management. Therefore, this study uses a thermal impedance experimental testing method to analyze the thermal behavior and characteristics of the 2.5-D package in the module system. Additionally, 3-D computational fluid dynamics simulations were performed to examine the thermal behavior of a typical 2.5-D package under system-level conditions. The results of the simulation are consistent with physical phenomena and confirm the rationality of the numerical model. The Taguchi experimental design to determine the effects of the main design parameters of the 2.5-D package on its thermal resistance under system-level conditions. Finally, the results of the Taguchi analysis are used to establish general design guidelines for minimizing the thermal resistance of the 2.5-D package. Overall, the results indicate that maintaining a consistent die thickness enables the use of a uniform thermal interface material (TIM) layer between the heat sink and the package and hence improves the heat dissipation efficiency. Furthermore, the thermal resistance of the 2.5-D package can be lowered by reducing the TIM thickness and power density, using materials with a higher thermal conductivity for the fin heat sink and TIM, and increasing the fan speed and number of fins.
{"title":"Thermal Characteristics Analysis and Optimization of Heterogeneous 2.5-D Package Under System-Level Conditions","authors":"Meng-Kai Shih;Tang-Yuan Chen;Bing-Yuan Huang;Cheng-Tang Pan;Chen-Chao Wang;C. P. Hung","doi":"10.1109/TCPMT.2024.3467274","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3467274","url":null,"abstract":"The 2.5-D integrated circuit (2.5-D IC) packages, in which multiple dies or chips are integrated side-by-side on a single interposer, play a crucial role in meeting the high bandwidth and high-performance requirements of merging applications, such as high-performance computing (HPC) and artificial intelligence (AI). However, the high power density in such packages leads to hot spot issues, which raise serious concerns regarding thermal control and management. Therefore, this study uses a thermal impedance experimental testing method to analyze the thermal behavior and characteristics of the 2.5-D package in the module system. Additionally, 3-D computational fluid dynamics simulations were performed to examine the thermal behavior of a typical 2.5-D package under system-level conditions. The results of the simulation are consistent with physical phenomena and confirm the rationality of the numerical model. The Taguchi experimental design to determine the effects of the main design parameters of the 2.5-D package on its thermal resistance under system-level conditions. Finally, the results of the Taguchi analysis are used to establish general design guidelines for minimizing the thermal resistance of the 2.5-D package. Overall, the results indicate that maintaining a consistent die thickness enables the use of a uniform thermal interface material (TIM) layer between the heat sink and the package and hence improves the heat dissipation efficiency. Furthermore, the thermal resistance of the 2.5-D package can be lowered by reducing the TIM thickness and power density, using materials with a higher thermal conductivity for the fin heat sink and TIM, and increasing the fan speed and number of fins.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"157-164"},"PeriodicalIF":2.3,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work demonstrates the development of an additive manufacturing (AM)-based transition from a microstrip to an empty substrate-integrated waveguide (ESIW). An expanded ESIW section with a sharp dielectric taper allows for wideband impedance matching. The proposed transition is validated by simple, inexpensive, and reduced complexity using an AM technique. The top and bottom of ESIW are covered with a copper-coated polylactic acid (PLA) substrate of 0.5-mm thickness. The via holes in the ESIW are replaced by spraying copper on the internal walls. The proposed model’s veracity was further established by evaluating it against a subtractive manufacturing (SM) prototype. The measured results obtained using AM (SM) have an insertion loss of less than 2.24 dB (0.92 dB), a return loss better than 17.7 dB (18.08 dB), and 73.4% (60.8%) fractional bandwidth (FBW) over 10–21.6 (10–18.75) GHz.
这项工作展示了基于增材制造（AM）的从微带到空基板集成波导（ESIW）过渡的发展。扩展的ESIW部分具有尖锐的介电锥度，允许宽带阻抗匹配。所提出的转换通过使用AM技术简单，廉价和降低复杂性来验证。ESIW的顶部和底部覆盖一层0.5 mm厚的镀铜聚乳酸（PLA）衬底。ESIW的通孔被内壁喷铜取代。通过对减法制造（SM）原型进行评估，进一步验证了该模型的准确性。使用AM （SM）获得的测量结果显示，插入损耗小于2.24 dB (0.92 dB)，回波损耗优于17.7 dB (18.08 dB)，在10-21.6 (10-18.75)GHz范围内的分数带宽（FBW）为73.4%（60.8%）。
{"title":"Additively Manufactured Wideband Transition From Microstrip to Empty SIW at Ku-Band","authors":"Mettu Goutham Reddy;Karthikeyan Sholampettai Subramanian;Nrusingha Charan Pradhan","doi":"10.1109/TCPMT.2024.3469638","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3469638","url":null,"abstract":"This work demonstrates the development of an additive manufacturing (AM)-based transition from a microstrip to an empty substrate-integrated waveguide (ESIW). An expanded ESIW section with a sharp dielectric taper allows for wideband impedance matching. The proposed transition is validated by simple, inexpensive, and reduced complexity using an AM technique. The top and bottom of ESIW are covered with a copper-coated polylactic acid (PLA) substrate of 0.5-mm thickness. The via holes in the ESIW are replaced by spraying copper on the internal walls. The proposed model’s veracity was further established by evaluating it against a subtractive manufacturing (SM) prototype. The measured results obtained using AM (SM) have an insertion loss of less than 2.24 dB (0.92 dB), a return loss better than 17.7 dB (18.08 dB), and 73.4% (60.8%) fractional bandwidth (FBW) over 10–21.6 (10–18.75) GHz.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"2074-2078"},"PeriodicalIF":2.3,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1109/TCPMT.2024.3469868
Joe Steele;Dimitra Psychogiou
A new class of self-packaged RF co-designed bandpass filtering baluns (BPF-Bs) is proposed with alongside a novel integration scheme utilizing vertically integrated inkjet-printed multicoupled transmission lines (TLs). Furthermore, the manuscript outlines a comprehensive design methodology for their realization, exploiting the design freedom afforded by a two-material inkjet printing process, which enables the creation of tightly coupled vertically integrated TLs. The concept has been verified experimentally through the manufacturing and testing of wideband (WB) and ultrawideband (UWB) BPF-B prototypes, having ${f} _{0} = 5$ GHz, footprints of $0.019~lambda _{g}^{2}$ and $0.025~lambda _{g}^{2}$ , and 3 dB fractional bandwidths (FBWs) of 24% and 111%, respectively. For the WB and UWB designs, power loss, phase imbalance (PI), and amplitude imbalance (AI) were measured between 4.4 and 7.4 dB and 1.8–4.8 dB, $4^{circ }~pm ~4^{circ }$ and $2^{circ }~pm ~2^{circ }$ , and $0.45~pm ~0.45$ dB and $0.4~pm ~0.4$ dB, respectively.
{"title":"Self-Packaged Inkjet-Printed Vertically Integrated RF Co-Designed Bandpass Filtering Baluns","authors":"Joe Steele;Dimitra Psychogiou","doi":"10.1109/TCPMT.2024.3469868","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3469868","url":null,"abstract":"A new class of self-packaged RF co-designed bandpass filtering baluns (BPF-Bs) is proposed with alongside a novel integration scheme utilizing vertically integrated inkjet-printed multicoupled transmission lines (TLs). Furthermore, the manuscript outlines a comprehensive design methodology for their realization, exploiting the design freedom afforded by a two-material inkjet printing process, which enables the creation of tightly coupled vertically integrated TLs. The concept has been verified experimentally through the manufacturing and testing of wideband (WB) and ultrawideband (UWB) BPF-B prototypes, having \u0000<inline-formula> <tex-math>${f} _{0} = 5$ </tex-math></inline-formula>\u0000 GHz, footprints of \u0000<inline-formula> <tex-math>$0.019~lambda _{g}^{2}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$0.025~lambda _{g}^{2}$ </tex-math></inline-formula>\u0000, and 3 dB fractional bandwidths (FBWs) of 24% and 111%, respectively. For the WB and UWB designs, power loss, phase imbalance (PI), and amplitude imbalance (AI) were measured between 4.4 and 7.4 dB and 1.8–4.8 dB, \u0000<inline-formula> <tex-math>$4^{circ }~pm ~4^{circ }$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$2^{circ }~pm ~2^{circ }$ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$0.45~pm ~0.45$ </tex-math></inline-formula>\u0000 dB and \u0000<inline-formula> <tex-math>$0.4~pm ~0.4$ </tex-math></inline-formula>\u0000 dB, respectively.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"2124-2127"},"PeriodicalIF":2.3,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10697187","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142789005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1109/TCPMT.2024.3469160
Guoliao Sun;Cheng Peng;Jing Wen;Hongwei Liu;Wenhui Zhu;Liancheng Wang
As the power density of electric vehicles continues to increase, double-sided cooling technology has emerged as a focal point of research. However, the complexity of double-sided cooling structures leads to significant thermal mismatch issues, potentially resulting in the failure of interconnect among components. The hotspot in interposers further exacerbates the risk of thermal failure in attach layers. This article proposes using AlSiC interposers to enhance the heat dissipation and power density handling capability of the module. In addition, we designed and manufactured a 750-V/300-A 1-in-1 flip chip double-sided cooling (FCDSC) insulated gate bipolar transistor (IGBT) power module with AlSiC interposers. Thermal and thermomechanical stress simulation results showed that, at a total power loss of 180 W, the maximum junction temperature of the module with AlSiC interposers is reduced by 4.4% compared to the conventional Mo interposer module, and the maximum thermal stress in the attach layers is slightly decreased. The thermal resistance of the module with AlSiC interposers is 12.8% lower than that of the module with Mo interposers. Furthermore, it was proved by the power cycling tests (PCTs) that the lifetime of the FCDSC power module using AlSiC interposers is 25% longer than that with Mo interposers and at least two times longer than that with Cu interposers under the same ${T}_{{j}{max}}$ and ${boldsymbol {Delta }}{T}$ . Static electrical tests demonstrate that the power module with AlSiC interposers exhibits no degradation.
随着电动汽车功率密度的不断提高，双面冷却技术已成为研究的热点。然而，双面冷却结构的复杂性导致了严重的热失配问题，可能导致组件之间互连失败。中间介质中的热点进一步加剧了附着层热失效的风险。本文提出采用AlSiC中间层来提高模块的散热能力和功率密度处理能力。此外，我们设计并制造了一种带有AlSiC中间层的750 v /300 a 1合1倒装芯片双面冷却（FCDSC）绝缘栅双极晶体管（IGBT）功率模块。热应力和热机械应力模拟结果表明，在总功耗为180 W的情况下，AlSiC中间体模块的最高结温比传统Mo中间体模块降低了4.4%，并且贴合层的最大热应力略有降低。采用AlSiC中间体的模块的热阻比采用Mo中间体的模块低12.8%。在相同的${T}_{{j}{max}}$和${boldsymbol {Delta}}{T}$条件下，功率循环试验（PCTs）证明，使用AlSiC中间体的FCDSC功率模块的寿命比使用Mo中间体的寿命长25%，比使用Cu中间体的寿命长至少2倍。静电测试表明，采用AlSiC中间体的电源模块没有出现退化现象。
{"title":"Improvement Heat Dissipation of Flip Chip Double-Sided Cooling IGBT Module Using AlSiC-Interposer Technology","authors":"Guoliao Sun;Cheng Peng;Jing Wen;Hongwei Liu;Wenhui Zhu;Liancheng Wang","doi":"10.1109/TCPMT.2024.3469160","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3469160","url":null,"abstract":"As the power density of electric vehicles continues to increase, double-sided cooling technology has emerged as a focal point of research. However, the complexity of double-sided cooling structures leads to significant thermal mismatch issues, potentially resulting in the failure of interconnect among components. The hotspot in interposers further exacerbates the risk of thermal failure in attach layers. This article proposes using AlSiC interposers to enhance the heat dissipation and power density handling capability of the module. In addition, we designed and manufactured a 750-V/300-A 1-in-1 flip chip double-sided cooling (FCDSC) insulated gate bipolar transistor (IGBT) power module with AlSiC interposers. Thermal and thermomechanical stress simulation results showed that, at a total power loss of 180 W, the maximum junction temperature of the module with AlSiC interposers is reduced by 4.4% compared to the conventional Mo interposer module, and the maximum thermal stress in the attach layers is slightly decreased. The thermal resistance of the module with AlSiC interposers is 12.8% lower than that of the module with Mo interposers. Furthermore, it was proved by the power cycling tests (PCTs) that the lifetime of the FCDSC power module using AlSiC interposers is 25% longer than that with Mo interposers and at least two times longer than that with Cu interposers under the same \u0000<inline-formula> <tex-math>${T}_{{j}{max}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${boldsymbol {Delta }}{T}$ </tex-math></inline-formula>\u0000. Static electrical tests demonstrate that the power module with AlSiC interposers exhibits no degradation.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"1968-1977"},"PeriodicalIF":2.3,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-24DOI: 10.1109/TCPMT.2024.3467120
Ying-Han;Dongrui-Liu;Shujun-Li
The bouncing of the contactor upon closing can cause adhesion of contacts and wear of the contact tips, and these factors directly influence the reliability and electrical longevity of the contactor. In this study, a 3-D interpenetrating Cu-W contact with rhombic dodecahedron (RD) skeleton was fabricated using 3-D printing and infiltration technology; some commercial Cu-W contacts were prepared as comparison. Based on Hertz contact theory and extended theory, combined with the Kelvin-Voigt spring damping model, the principle of energy dissipation in contactor contact collision was analyzed. The Young modulus and damping coefficient of the two types of Cu-W contacts were obtained through stress-strain experiments and damping experiments using an INSTRON 5582 testing machine and a DpV55 shaker. The contact bounce characteristics of the two contact tips under different contactor parameters were obtained using a contact bounce test device and finally validated in practical contactors. The results show that the RD-structured Cu-W contact tip with a higher damping coefficient has more internal friction and better energy absorption when subjected to collision impacts, effectively suppressing contact bounce and exhibiting superior anti-bounce performance, especially at high-speed closings.
{"title":"Research on the Bounce Suppression of the 3-D Interpenetrating Cu-W","authors":"Ying-Han;Dongrui-Liu;Shujun-Li","doi":"10.1109/TCPMT.2024.3467120","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3467120","url":null,"abstract":"The bouncing of the contactor upon closing can cause adhesion of contacts and wear of the contact tips, and these factors directly influence the reliability and electrical longevity of the contactor. In this study, a 3-D interpenetrating Cu-W contact with rhombic dodecahedron (RD) skeleton was fabricated using 3-D printing and infiltration technology; some commercial Cu-W contacts were prepared as comparison. Based on Hertz contact theory and extended theory, combined with the Kelvin-Voigt spring damping model, the principle of energy dissipation in contactor contact collision was analyzed. The Young modulus and damping coefficient of the two types of Cu-W contacts were obtained through stress-strain experiments and damping experiments using an INSTRON 5582 testing machine and a DpV55 shaker. The contact bounce characteristics of the two contact tips under different contactor parameters were obtained using a contact bounce test device and finally validated in practical contactors. The results show that the RD-structured Cu-W contact tip with a higher damping coefficient has more internal friction and better energy absorption when subjected to collision impacts, effectively suppressing contact bounce and exhibiting superior anti-bounce performance, especially at high-speed closings.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"1995-2002"},"PeriodicalIF":2.3,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-23DOI: 10.1109/TCPMT.2024.3465655
Xianglong Wang;Jing Huang;Dongdong Chen;Di Li;Yintang Yang
The traditional design is achieved by the iterative simulation using finite element method (FEM) software and relies on the experts’ experience, so the design parameters cannot be effectively optimized to achieve the high-performance. In this research, based on the backpropagation neural network (BPNN) model and particle swarm optimization with linear decreasing inertia weight (PSO-LDIW) algorithm, an electro-thermal-stress multiphysical field coupling optimization design method for coaxial through silicon via (CTSV) array is provided. The irregular and complex relationship between the parameters (height of CTSV, radius, thickness of SiO2, BCB, and coaxial annular) and indexes is investigated by COMSOL Multiphysics and HFSS software. According to the simulation data of COMSOL and HFSS, the BPNN models are used to express the corresponding relationship between the parameters and indexes of CTSV. According to the desired indexes of CTSV, the multiobjective optimization function is formulated. Then, the PSO-LDIW algorithm is applied to optimize the parameters of CTSV. Finally, the simulation experiment is used to verify the effectiveness of the optimization design strategy. The simulated indexes (−40.28 dB, 366.31 K, 115.21, 74.14, and 23.16 MPa) well agree with the desired ones (−40 dB, 360 K, 110, 70, and 25 MPa), which indicates that the parameters of CTSV can effectively optimized by the developed design method to control the indexes. In addition, the optimized parameters are applied in the $4times 4$ CTSV array to verify the effectiveness of the developed strategy. Therefore, the developed electro-thermal-stress multiphysical field coupling optimization design method can effectively design a CTSV array for manufacturing high-performance chiplet-based microsystems.
{"title":"Electro-Thermal-Stress Multiphysical Field Coupling Optimization Design for Coaxial Through Silicon Via Array","authors":"Xianglong Wang;Jing Huang;Dongdong Chen;Di Li;Yintang Yang","doi":"10.1109/TCPMT.2024.3465655","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3465655","url":null,"abstract":"The traditional design is achieved by the iterative simulation using finite element method (FEM) software and relies on the experts’ experience, so the design parameters cannot be effectively optimized to achieve the high-performance. In this research, based on the backpropagation neural network (BPNN) model and particle swarm optimization with linear decreasing inertia weight (PSO-LDIW) algorithm, an electro-thermal-stress multiphysical field coupling optimization design method for coaxial through silicon via (CTSV) array is provided. The irregular and complex relationship between the parameters (height of CTSV, radius, thickness of SiO2, BCB, and coaxial annular) and indexes is investigated by COMSOL Multiphysics and HFSS software. According to the simulation data of COMSOL and HFSS, the BPNN models are used to express the corresponding relationship between the parameters and indexes of CTSV. According to the desired indexes of CTSV, the multiobjective optimization function is formulated. Then, the PSO-LDIW algorithm is applied to optimize the parameters of CTSV. Finally, the simulation experiment is used to verify the effectiveness of the optimization design strategy. The simulated indexes (−40.28 dB, 366.31 K, 115.21, 74.14, and 23.16 MPa) well agree with the desired ones (−40 dB, 360 K, 110, 70, and 25 MPa), which indicates that the parameters of CTSV can effectively optimized by the developed design method to control the indexes. In addition, the optimized parameters are applied in the \u0000<inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula>\u0000 CTSV array to verify the effectiveness of the developed strategy. Therefore, the developed electro-thermal-stress multiphysical field coupling optimization design method can effectively design a CTSV array for manufacturing high-performance chiplet-based microsystems.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 11","pages":"1978-1986"},"PeriodicalIF":2.3,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
DC relays are widely used in aerospace control, rail transportation, and other fields, with the reliability of their operation being a key factor in ensuring system safety. This article tests various models of dc relays and identifies a common phenomenon of secondary release, which can prolong the release time of the relay, increase contact arcing time, and shorten the relay’s lifespan. To investigate the generation mechanism and effects of this phenomenon, a specific model of dc relay is chosen as the research subject. Experimental and numerical simulation methods are employed to establish a circuit-magnetic field-mechanical coupling model of the dc relay, and its accuracy is validated through experimental comparison. Based on the simulation results, the secondary release mechanism is analyzed from the perspective of suction and reaction force matching and contact motion characteristics. The study proposes mitigating the secondary release phenomenon by increasing the air gap in the magnetic circuit, which improves the suction and reaction force characteristics during the release process. This method decreases the release time while increasing the suction time, with the impact on release time being more significant. The findings lay the groundwork for optimizing the design and extending the lifespan of electromagnetic relays.
{"title":"Study on Secondary Release Mechanism of DC Relay Based on Circuit-Magnetic Field-Mechanical Coupling Calculation","authors":"Wenhua Li;Yangyang Li;Jihui Gao;Ruzheng Pan;Zhengyuan Zhao","doi":"10.1109/TCPMT.2024.3466310","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3466310","url":null,"abstract":"DC relays are widely used in aerospace control, rail transportation, and other fields, with the reliability of their operation being a key factor in ensuring system safety. This article tests various models of dc relays and identifies a common phenomenon of secondary release, which can prolong the release time of the relay, increase contact arcing time, and shorten the relay’s lifespan. To investigate the generation mechanism and effects of this phenomenon, a specific model of dc relay is chosen as the research subject. Experimental and numerical simulation methods are employed to establish a circuit-magnetic field-mechanical coupling model of the dc relay, and its accuracy is validated through experimental comparison. Based on the simulation results, the secondary release mechanism is analyzed from the perspective of suction and reaction force matching and contact motion characteristics. The study proposes mitigating the secondary release phenomenon by increasing the air gap in the magnetic circuit, which improves the suction and reaction force characteristics during the release process. This method decreases the release time while increasing the suction time, with the impact on release time being more significant. The findings lay the groundwork for optimizing the design and extending the lifespan of electromagnetic relays.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2280-2289"},"PeriodicalIF":2.3,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rough contact creates a large electrical and thermal resistance between the contact surfaces of the electrical connector, which has a great impact on its usage. This work adopted finite element simulation to investigate the electrical and thermal properties in the contact region of electrical connectors. The Weierstrass-Mandelbrot (W-M) fractal function was used to model the contact of crown spring connectors with various roughness. The effects of different roughness and contact force on the electrical and thermal contact performance were analyzed. The increased roughness and decreased contact force cause a reduction in the contact area, resulting in the concentration of current and heat flow. The reduced contact area contributes to the increase of electrical contact resistance (ECR) and thermal contact resistance (TCR). The research indicates that smoothing the interfaces and increasing the contact force can effectively enhance contact performance.
{"title":"Investigation on Electrical and Thermal Performance of Electrical Connectors Under Rough Surface Contact","authors":"Xin Lei;Ziniu Yu;Yuhan Gao;Yuqi Zhou;Kezhong Xu;Yuxin Chen;Fulong Zhu","doi":"10.1109/TCPMT.2024.3465666","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3465666","url":null,"abstract":"Rough contact creates a large electrical and thermal resistance between the contact surfaces of the electrical connector, which has a great impact on its usage. This work adopted finite element simulation to investigate the electrical and thermal properties in the contact region of electrical connectors. The Weierstrass-Mandelbrot (W-M) fractal function was used to model the contact of crown spring connectors with various roughness. The effects of different roughness and contact force on the electrical and thermal contact performance were analyzed. The increased roughness and decreased contact force cause a reduction in the contact area, resulting in the concentration of current and heat flow. The reduced contact area contributes to the increase of electrical contact resistance (ECR) and thermal contact resistance (TCR). The research indicates that smoothing the interfaces and increasing the contact force can effectively enhance contact performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"281-287"},"PeriodicalIF":2.3,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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