Pub Date : 2025-09-16DOI: 10.1109/TCPMT.2025.3602199
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2025.3602199","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3602199","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"C3-C3"},"PeriodicalIF":3.0,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165615","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145073333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/TCPMT.2025.3602197
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors","authors":"","doi":"10.1109/TCPMT.2025.3602197","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3602197","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"2053-2053"},"PeriodicalIF":3.0,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165613","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145073374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15DOI: 10.1109/TCPMT.2025.3610036
Fuhan Liu;Rui Zhang;Kanno Kimiyuki;Joon Woo Kim;Madhavan Swaminathan;Rao R. Tummala
Downscaling of microvias to approach the critical dimension (CD) of routing half-line pitch is crucial for advanced packaging but presents significant challenges. The state of the art (SOTA), achieved with nanosecond (ns) pulsed UV laser, results in via diameters of 20 $mu $ m. By employing a 5-ps pulsed UV laser, microvias of 5 $mu $ m were achieved in a 5-$mu $ m-thick Ajinomoto build-up film (ABF) through conventional laser ablation and could be reduced to 3 $mu $ m by adding a thin copper layer on top of the ABF as a buffer. With thinner and filler-free materials, the minimum demonstrated microvia size was further down to 1.26 $mu $ m on a 2-$mu $ m-thick JSR dielectric film. A via matrix of $26times 33$ (858) was presented. The heat-affected zone (HAZ) and defects were around 0.5 $mu $ m. The landing accuracy within $16times 16$ (256) with a via pitch of 5-$mu $ m matrix was analyzed, which was ±0.34 $mu $ m. Considerations for the next-generation system designs for 1 $mu $ m and submicrometer microvias are discussed.
{"title":"Advances in Package Microvia Interconnects: Breakthroughs With Picosecond UV Laser Ablation","authors":"Fuhan Liu;Rui Zhang;Kanno Kimiyuki;Joon Woo Kim;Madhavan Swaminathan;Rao R. Tummala","doi":"10.1109/TCPMT.2025.3610036","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3610036","url":null,"abstract":"Downscaling of microvias to approach the critical dimension (CD) of routing half-line pitch is crucial for advanced packaging but presents significant challenges. The state of the art (SOTA), achieved with nanosecond (ns) pulsed UV laser, results in via diameters of 20 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m. By employing a 5-ps pulsed UV laser, microvias of 5 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m were achieved in a 5-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick Ajinomoto build-up film (ABF) through conventional laser ablation and could be reduced to 3 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m by adding a thin copper layer on top of the ABF as a buffer. With thinner and filler-free materials, the minimum demonstrated microvia size was further down to 1.26 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m on a 2-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick JSR dielectric film. A via matrix of <inline-formula> <tex-math>$26times 33$ </tex-math></inline-formula> (858) was presented. The heat-affected zone (HAZ) and defects were around 0.5 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m. The landing accuracy within <inline-formula> <tex-math>$16times 16$ </tex-math></inline-formula> (256) with a via pitch of 5-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m matrix was analyzed, which was ±0.34 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m. Considerations for the next-generation system designs for 1 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m and submicrometer microvias are discussed.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 11","pages":"2531-2538"},"PeriodicalIF":3.0,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145584666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-11DOI: 10.1109/TCPMT.2025.3609236
Walter Hartner;Simon Kornprobst;Mathias Zinnoecker;Martin Niessner;Markus Fink;Franz-Peter Kalz;Peter Lutz
As the automotive industry continues to advance, the demand for high-performance radar systems increases. To address this need, we explored the potential of fan-out wafer-level packaging (FO-WLP) or embedded wafer-level ball grid Aarray (eWLB) for monolithic microwave integrated circuits (MMICs) in the 77-GHz range, with a focus on thermal management through top-side cooling (TSC). Our thermal simulations revealed that using a thin, high-thermal-conductivity thermal interface material (TIM) layer, the thermal resistance can be reduced by up to 75%. We assessed various scenarios, including TIM/absorber layer thickness and thermal conductivity variations, chip/package size influences, and overmold thickness impacts. To ensure reliability, we analyzed the mechanical aspects of pressure and force applied by TIM compression on the MMIC using thermomechanical simulations. Our results showed a zone with less than 10% loss in lifetime under certain top-force loading conditions. Experimental thermo-mechanical Temperature Cycling on Board (TCoB) board-level reliability tests verified these findings, highlighting the importance of avoiding excessive top-side forces and thermomechanical cycling numbers to prevent solder ball bridging. Electromagnetic characterization of TIM materials’ electrical properties and RF measurements of the radar system with TSC were also conducted. A key takeaway is the recommendation to use high-loss TIM materials to prevent RF performance deterioration when applying TSC with metallic components. By optimizing FO-WLP/eWLB packaging for MMICs in automotive radar applications, we can enable more efficient, reliable, and high-performance systems that make our roads safer and more efficient.
{"title":"Enabling Reliable and Efficient Automotive Radar Systems by Investigating FO-WLP/eWLB Packaging for 77-GHz MMICs With Top-Side Cooling","authors":"Walter Hartner;Simon Kornprobst;Mathias Zinnoecker;Martin Niessner;Markus Fink;Franz-Peter Kalz;Peter Lutz","doi":"10.1109/TCPMT.2025.3609236","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3609236","url":null,"abstract":"As the automotive industry continues to advance, the demand for high-performance radar systems increases. To address this need, we explored the potential of fan-out wafer-level packaging (FO-WLP) or embedded wafer-level ball grid Aarray (eWLB) for monolithic microwave integrated circuits (MMICs) in the 77-GHz range, with a focus on thermal management through top-side cooling (TSC). Our thermal simulations revealed that using a thin, high-thermal-conductivity thermal interface material (TIM) layer, the thermal resistance can be reduced by up to 75%. We assessed various scenarios, including TIM/absorber layer thickness and thermal conductivity variations, chip/package size influences, and overmold thickness impacts. To ensure reliability, we analyzed the mechanical aspects of pressure and force applied by TIM compression on the MMIC using thermomechanical simulations. Our results showed a zone with less than 10% loss in lifetime under certain top-force loading conditions. Experimental thermo-mechanical Temperature Cycling on Board (TCoB) board-level reliability tests verified these findings, highlighting the importance of avoiding excessive top-side forces and thermomechanical cycling numbers to prevent solder ball bridging. Electromagnetic characterization of TIM materials’ electrical properties and RF measurements of the radar system with TSC were also conducted. A key takeaway is the recommendation to use high-loss TIM materials to prevent RF performance deterioration when applying TSC with metallic components. By optimizing FO-WLP/eWLB packaging for MMICs in automotive radar applications, we can enable more efficient, reliable, and high-performance systems that make our roads safer and more efficient.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 11","pages":"2521-2530"},"PeriodicalIF":3.0,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145584637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-22DOI: 10.1109/TCPMT.2025.3593032
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information","authors":"","doi":"10.1109/TCPMT.2025.3593032","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3593032","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"C2-C2"},"PeriodicalIF":3.0,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11134682","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-22DOI: 10.1109/TCPMT.2025.3593037
{"title":"IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information","authors":"","doi":"10.1109/TCPMT.2025.3593037","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3593037","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"C3-C3"},"PeriodicalIF":3.0,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11134681","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144892375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-22DOI: 10.1109/TCPMT.2025.3591951
Hiren D. Thacker;Stéphane Bernabé;Richard Pitwon
{"title":"Foreword: Frontiers of Photonic Integration and Packaging","authors":"Hiren D. Thacker;Stéphane Bernabé;Richard Pitwon","doi":"10.1109/TCPMT.2025.3591951","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3591951","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 8","pages":"1562-1564"},"PeriodicalIF":3.0,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11134684","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144891281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-18DOI: 10.1109/TCPMT.2025.3599484
Wonchul Do;Sanghyun Jin;Insoo Choi;Jinho Jeong
This article presents a novel redistribution layer (RDL) technology with embedded trace structures, targeting high-density interconnects for organic interposers and bridge chips in 2.5-D integration. The proposed embedded trace RDL (ETR) adopts grayscale lithography, enabling the simultaneous formation of vias and traces in a single lithography step. This single-mask process reduces manufacturing complexity and cost compared to conventional dual-mask ETR approaches and is compatible with I-line steppers commonly used in advanced packaging. The proposed ETR successfully demonstrates four-stacked vias with a minimum diameter of $1.5~mu $ m and traces with 2/$1~mu $ m line/space, validating its capability for fine-pitch, multilayer interconnects. Trace width and dielectric thickness variations were within 7.5% and 2.9% of the median, respectively, and critical dimension uniformity was within 5%. Dense traces between two vias were fabricated and compared with conventional semi-additive process (SAP)-based RDL, confirming that the pad-less vias in the proposed ETR enhance interconnection density. Furthermore, the rounded-edge traces, a distinctive feature of the ETR, reduce conductor loss by mitigating current crowding, leading to improved signal transmission bandwidth. Together, these effects increase bandwidth density, making the proposed ETR highly suitable for advanced high-speed, high-density interconnect applications. Finally, to the best of our knowledge, electromigration (EM) testing was conducted on the ETR structure for the first time, demonstrating a $34.2times $ improvement in mean time-to-failure (MTTF) over SAP-based RDL.
{"title":"Single-Mask Embedded Trace Redistribution Layer Technology Using Grayscale Lithography","authors":"Wonchul Do;Sanghyun Jin;Insoo Choi;Jinho Jeong","doi":"10.1109/TCPMT.2025.3599484","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3599484","url":null,"abstract":"This article presents a novel redistribution layer (RDL) technology with embedded trace structures, targeting high-density interconnects for organic interposers and bridge chips in 2.5-D integration. The proposed embedded trace RDL (ETR) adopts grayscale lithography, enabling the simultaneous formation of vias and traces in a single lithography step. This single-mask process reduces manufacturing complexity and cost compared to conventional dual-mask ETR approaches and is compatible with I-line steppers commonly used in advanced packaging. The proposed ETR successfully demonstrates four-stacked vias with a minimum diameter of <inline-formula> <tex-math>$1.5~mu $ </tex-math></inline-formula>m and traces with 2/<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>m line/space, validating its capability for fine-pitch, multilayer interconnects. Trace width and dielectric thickness variations were within 7.5% and 2.9% of the median, respectively, and critical dimension uniformity was within 5%. Dense traces between two vias were fabricated and compared with conventional semi-additive process (SAP)-based RDL, confirming that the pad-less vias in the proposed ETR enhance interconnection density. Furthermore, the rounded-edge traces, a distinctive feature of the ETR, reduce conductor loss by mitigating current crowding, leading to improved signal transmission bandwidth. Together, these effects increase bandwidth density, making the proposed ETR highly suitable for advanced high-speed, high-density interconnect applications. Finally, to the best of our knowledge, electromigration (EM) testing was conducted on the ETR structure for the first time, demonstrating a <inline-formula> <tex-math>$34.2times $ </tex-math></inline-formula> improvement in mean time-to-failure (MTTF) over SAP-based RDL.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 10","pages":"2269-2278"},"PeriodicalIF":3.0,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145374744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/TCPMT.2025.3597811
Bijan Shahriari;Roni Khazaka
Behavioral modeling of analog circuits is an important step of the integrated circuit design flow. Indeed, closed-box behavior modeling allows users to replicate the behavior of circuit elements and devices without explicitly knowing the inner workings of the device. Prior works have automated the generation of behavioral models using machine learning (ML) at both the device and circuit level. More specifically, a recent work has used high-order polynomial projection operators (HIPPOs) to augment gated recurrent unit (GRU)-based macro-models. This new HIPPO-based model has been shown to outperform state-of-the-art GRU-based circuit macro-models. In this article, we introduce a new type of modified recurrent neural network (RNN) circuit macro-model that uses the HIPPO framework, called HIPPO-RNN. Additionally, we present a modified HIPPO-RNN (stable-HIPPO-RNN) model that is more suitable for enforcing input-to-state stability (ISS), and derive corresponding stability constraints. These constraints effectively guarantee ISS stability of the macro-model during transient simulation. We show the validity and superior performance of our macro-models on two circuit modeling examples.
{"title":"Stable HIPPO-Based Circuit Macro-Modeling","authors":"Bijan Shahriari;Roni Khazaka","doi":"10.1109/TCPMT.2025.3597811","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3597811","url":null,"abstract":"Behavioral modeling of analog circuits is an important step of the integrated circuit design flow. Indeed, closed-box behavior modeling allows users to replicate the behavior of circuit elements and devices without explicitly knowing the inner workings of the device. Prior works have automated the generation of behavioral models using machine learning (ML) at both the device and circuit level. More specifically, a recent work has used high-order polynomial projection operators (HIPPOs) to augment gated recurrent unit (GRU)-based macro-models. This new HIPPO-based model has been shown to outperform state-of-the-art GRU-based circuit macro-models. In this article, we introduce a new type of modified recurrent neural network (RNN) circuit macro-model that uses the HIPPO framework, called HIPPO-RNN. Additionally, we present a modified HIPPO-RNN (stable-HIPPO-RNN) model that is more suitable for enforcing input-to-state stability (ISS), and derive corresponding stability constraints. These constraints effectively guarantee ISS stability of the macro-model during transient simulation. We show the validity and superior performance of our macro-models on two circuit modeling examples.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1823-1835"},"PeriodicalIF":3.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-11DOI: 10.1109/TCPMT.2025.3597771
Antonio Carlucci;Ion Victor Gosea;Stefano Grivet-Talocia
This article presents a complete framework for the generation of behavioral macromodels of a wide class of nonlinear components, devices, and systems. The model structure and related identification algorithms are based on the Volterra series formulated in the frequency domain through multivariate generalized transfer functions (GTFs). A multivariate rational model is first estimated in pole-residue form from sampled responses and then converted to a bilinear state-space form. The main novel contribution of this work is the SPICE-compatible circuit synthesis, which enables the usage of nonlinear macromodels within circuit simulation environments as part of more complex system-level simulations. Examples are provided for a low dropout voltage regulator and a system-level power distribution network embedding integrated regulators. For such examples, the proposed SPICE equivalents offer speedup factors ranging from $12times $ up to $650times $ with negligible loss in accuracy.
{"title":"On the Generation of SPICE-Compatible Nonlinear Behavioral Macromodels","authors":"Antonio Carlucci;Ion Victor Gosea;Stefano Grivet-Talocia","doi":"10.1109/TCPMT.2025.3597771","DOIUrl":"https://doi.org/10.1109/TCPMT.2025.3597771","url":null,"abstract":"This article presents a complete framework for the generation of behavioral macromodels of a wide class of nonlinear components, devices, and systems. The model structure and related identification algorithms are based on the Volterra series formulated in the frequency domain through multivariate generalized transfer functions (GTFs). A multivariate rational model is first estimated in pole-residue form from sampled responses and then converted to a bilinear state-space form. The main novel contribution of this work is the SPICE-compatible circuit synthesis, which enables the usage of nonlinear macromodels within circuit simulation environments as part of more complex system-level simulations. Examples are provided for a low dropout voltage regulator and a system-level power distribution network embedding integrated regulators. For such examples, the proposed SPICE equivalents offer speedup factors ranging from <inline-formula> <tex-math>$12times $ </tex-math></inline-formula> up to <inline-formula> <tex-math>$650times $ </tex-math></inline-formula> with negligible loss in accuracy.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 9","pages":"1857-1867"},"PeriodicalIF":3.0,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145100296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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