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Ultralow-Temperature Deposition and Enhanced Bonding of SiCN Films for Advanced 3-D Integration 用于先进三维集成的SiCN薄膜的超低温沉积和增强键合
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-10-03 DOI: 10.1109/TCPMT.2025.3617495
Yeonju Kim;Kyungmin Shin;Donghyeok Choi;Jongshin Hyun;Byungjoo Jin;Jong Kyung Park
This study explores the potential of SiCN films as a low-temperature alternative to SiO2 insulators for hybrid bonding in 3-D integration. SiCN films were deposited at $180~^{circ }$ C and $350~^{circ }$ C to investigate the effects of deposition temperature and composition on bonding performance. By optimizing precursor flow rates, we tailored the film properties, enhancing Si dangling bonds crucial for bonding. To achieve ultralow-temperature bonding below $100~^{circ }$ C, O2 plasma and potassium hydroxide (KOH) surface treatments were employed, significantly improving bonding interfaces by increasing Si-OH groups on the surface. Our results demonstrate that SiCN films deposited at low temperatures can achieve bonding characteristics comparable to those of high-temperature films. The enhanced bonding performance is attributed to surface treatments that mitigate hydrogen content and promote Si-OH formation. The low-temperature bonding capabilities of SiCN contribute to reducing thermal budgets, preventing device degradation, and advancing 3-D integration and hybrid bonding technologies for next-generation semiconductor applications.
本研究探索了SiCN薄膜在3d集成中作为SiO2绝缘体的低温替代品的潜力。在$180~^{circ}$ C和$350~^{circ}$ C下沉积SiCN薄膜,研究沉积温度和成分对键合性能的影响。通过优化前驱体流动速率,我们定制了薄膜的性能,增强了硅悬空键对键合至关重要。为了实现低于$100~^{circ}$ C的超低温键合,采用了O2等离子体和氢氧化钾(KOH)表面处理,通过增加表面的Si-OH基团显著改善了键合界面。我们的研究结果表明,在低温下沉积的SiCN薄膜可以获得与高温薄膜相当的键合特性。增强的键合性能是由于表面处理降低了氢含量,促进了Si-OH的形成。SiCN的低温键合能力有助于减少热预算,防止器件退化,并为下一代半导体应用推进3-D集成和混合键合技术。
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引用次数: 0
Hybrid Bonding of Nonphotosensitive Dry Films and Cu/SnAg Microbumps for Multilayer Glass Packaging 非光敏干膜与Cu/SnAg微凸点复合键合用于多层玻璃封装
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-10-01 DOI: 10.1109/TCPMT.2025.3616264
Qing Zhou;Ying Tian;Yaqing Zhou;Yi Zhong;Tian Yu;Miao Zhang;Daquan Yu
A novel low-temperature wafer-level hybrid bonding technique using metal microbumps (Cu/SnAg) and nonphotosensitive dry films has been developed and investigated. The bonding process is conducted at low temperatures: $160~^{circ }$ C for the dry film and within the range of $260~^{circ }$ C– $280~^{circ }$ C for the microbumps. The microbumps are fabricated using conventional electroplating, while patterning of the nonphotosensitive dry film is achieved through laser ablation, bypassing the need for traditional lithography. Furthermore, optimizing the thickness of the microbumps, the opening dimensions of the dry film, the maximum bonding pressure, and the bonding temperature has enabled the development of a stepped control profile, which allows a seam-free bonding interface between the microbumps and the dry films. For demonstration, superior interconnect performance with an average tensile strength of approximately 8.11 MPa is achieved. The nonphotosensitive dry film exhibits low transmission loss when applied to glass packaging due to its low dielectric constant and dissipation factor. Consequently, the proposed hybrid bonding technique provides a highly cost-effective and promising approach for future multilayer glass/polyimide (PI) radio frequency (RF) 3-D integration.
研究了一种利用金属微凸点(Cu/SnAg)和非光敏干膜的低温晶圆级杂化键合技术。结合过程在低温下进行:$160~^{circ}$ C用于干膜,$260~^{circ}$ C - $280~^{circ}$ C用于微凸起。微凸起是用传统的电镀方法制造的,而非光敏干膜的图案是通过激光烧蚀来实现的,绕过了传统光刻的需要。此外,优化微凸点的厚度、干膜的开口尺寸、最大键合压力和键合温度,使微凸点和干膜之间形成无接缝的键合界面成为可能。作为验证,该材料具有优异的互连性能,平均抗拉强度约为8.11 MPa。非光敏干膜由于介电常数和耗散系数较低,应用于玻璃封装时具有较低的传输损耗。因此,所提出的混合键合技术为未来多层玻璃/聚酰亚胺(PI)射频(RF)三维集成提供了一种极具成本效益和前景的方法。
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引用次数: 0
Effect of Process and Design Parameters in Cu/SiCN Hybrid Bonding Process: A Finite Element Analysis Study Cu/SiCN复合键合工艺及设计参数影响的有限元分析研究
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-09-29 DOI: 10.1109/TCPMT.2025.3615235
So-Yeon Park;Yoonho Choi;Cha-Hee Kim;Seung-Ho Seo;Sarah Eunkyung Kim;Won-Jun Lee
There is a critical need to understand the optimal process conditions and pad design for hybrid bonding at progressively finer pitches. The finite element method (FEM) analysis is a valuable approach for elucidating the bonding mechanism and predicting the bonded area. In this study, we investigated hybrid bonding using FEM analysis to study bonding mechanisms and suggest optimal design strategies. Models were constructed for sub-micrometer copper pads with silicon carbonitride (SiCN) as the dielectric film at the bonding interface, with variations in copper pad dimensions and dishing depth. The postbond annealing process was simulated with different annealing temperatures. The results show that high annealing temperatures and low chemical mechanical polishing (CMP) dishing depths promote sufficient pad expansion to achieve complete copper-to-copper bonding, which is consistent with established observations in the field. Furthermore, the study highlights a strong dependence of the bonded area on the copper pad dimensions, emphasizing the need for proper optimization of pad dimensions. In particular, copper bonding was highly sensitive to pad thickness and aspect ratio. As the pad thickness increased, thermal expansion increased, resulting in a larger bonded area. For all pad thicknesses, maximum thermal expansion occurred at an aspect ratio of approximately 0.4. Therefore, a specific diameter range was identified where the maximum bonded area could be achieved for a given pad thickness.
有一个迫切需要了解的最佳工艺条件和衬垫设计的混合键合在越来越细的间距。有限元分析是阐明粘接机理和预测粘接面积的重要手段。在这项研究中,我们采用有限元分析方法研究了混合键合机制,并提出了优化设计策略。建立了以碳氮化硅(SiCN)为介电膜的亚微米铜焊盘模型,并对铜焊盘尺寸和盘形深度进行了研究。模拟了不同退火温度下的键后退火过程。结果表明,较高的退火温度和较低的化学机械抛光(CMP)盘形深度可以促进衬垫充分膨胀,从而实现铜与铜的完全结合,这与现场已有的观察结果一致。此外,该研究还强调了铜衬垫尺寸对键合面积的依赖性,强调了对衬垫尺寸进行适当优化的必要性。特别是铜键合对焊盘厚度和纵横比高度敏感。随着焊盘厚度的增加,热膨胀增大,粘结面积增大。对于所有衬垫厚度,最大热膨胀发生在长径比约为0.4时。因此,确定了一个特定的直径范围,在该范围内,对于给定的焊盘厚度,可以实现最大粘合面积。
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information IEEE元件、包装与制造技术汇刊信息
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-09-16 DOI: 10.1109/TCPMT.2025.3602195
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引用次数: 0
Foreword: Special Section on Advances in Design, Modeling, and Simulation Methodologies for Modern Chip-Package-System Integration 前言:关于现代芯片封装系统集成的设计、建模和仿真方法的进展的特别部分
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-09-16 DOI: 10.1109/TCPMT.2025.3598876
Antonio Maffucci;Mihai Telescu
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information IEEE元件、封装与制造技术学会汇刊
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-09-16 DOI: 10.1109/TCPMT.2025.3602199
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE元件、封装与制造技术资讯汇刊
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-09-16 DOI: 10.1109/TCPMT.2025.3602197
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引用次数: 0
Advances in Package Microvia Interconnects: Breakthroughs With Picosecond UV Laser Ablation 封装微孔互连的进展:皮秒紫外激光烧蚀的突破
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-09-15 DOI: 10.1109/TCPMT.2025.3610036
Fuhan Liu;Rui Zhang;Kanno Kimiyuki;Joon Woo Kim;Madhavan Swaminathan;Rao R. Tummala
Downscaling of microvias to approach the critical dimension (CD) of routing half-line pitch is crucial for advanced packaging but presents significant challenges. The state of the art (SOTA), achieved with nanosecond (ns) pulsed UV laser, results in via diameters of 20 $mu $ m. By employing a 5-ps pulsed UV laser, microvias of 5 $mu $ m were achieved in a 5- $mu $ m-thick Ajinomoto build-up film (ABF) through conventional laser ablation and could be reduced to 3 $mu $ m by adding a thin copper layer on top of the ABF as a buffer. With thinner and filler-free materials, the minimum demonstrated microvia size was further down to 1.26 $mu $ m on a 2- $mu $ m-thick JSR dielectric film. A via matrix of $26times 33$ (858) was presented. The heat-affected zone (HAZ) and defects were around 0.5 $mu $ m. The landing accuracy within $16times 16$ (256) with a via pitch of 5- $mu $ m matrix was analyzed, which was ±0.34 $mu $ m. Considerations for the next-generation system designs for 1 $mu $ m and submicrometer microvias are discussed.
缩小微孔尺寸以接近布线半线间距的关键尺寸(CD)对于先进封装至关重要,但也存在重大挑战。利用纳秒(ns)脉冲紫外激光器实现的最先进技术(SOTA),其通孔直径可达20美元/ μ m。通过使用5ps脉冲紫外激光器,在5美元/ μ m厚的味之素沉积膜(ABF)中,通过常规激光烧蚀可实现5美元/ μ m的微通孔,通过在ABF顶部添加薄铜层作为缓冲,微通孔可缩小至3美元/ μ m。使用更薄和无填料的材料,在2- $mu $ m厚的JSR介电膜上,最小微孔尺寸进一步降至1.26 $mu $ m。给出了$26 × 33$(858)的via矩阵。热影响区(HAZ)和缺陷约为0.5 $mu $ m,分析了在$16 × 16(256)内,通孔间距为5- $mu $ m矩阵的着陆精度为±0.34 $mu $ m,讨论了下一代1 $mu $ m和亚微米微通孔系统设计的注意事项。
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引用次数: 0
Enabling Reliable and Efficient Automotive Radar Systems by Investigating FO-WLP/eWLB Packaging for 77-GHz MMICs With Top-Side Cooling 通过研究采用顶部冷却的77 ghz mmic的FO-WLP/eWLB封装,实现可靠高效的汽车雷达系统
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-09-11 DOI: 10.1109/TCPMT.2025.3609236
Walter Hartner;Simon Kornprobst;Mathias Zinnoecker;Martin Niessner;Markus Fink;Franz-Peter Kalz;Peter Lutz
As the automotive industry continues to advance, the demand for high-performance radar systems increases. To address this need, we explored the potential of fan-out wafer-level packaging (FO-WLP) or embedded wafer-level ball grid Aarray (eWLB) for monolithic microwave integrated circuits (MMICs) in the 77-GHz range, with a focus on thermal management through top-side cooling (TSC). Our thermal simulations revealed that using a thin, high-thermal-conductivity thermal interface material (TIM) layer, the thermal resistance can be reduced by up to 75%. We assessed various scenarios, including TIM/absorber layer thickness and thermal conductivity variations, chip/package size influences, and overmold thickness impacts. To ensure reliability, we analyzed the mechanical aspects of pressure and force applied by TIM compression on the MMIC using thermomechanical simulations. Our results showed a zone with less than 10% loss in lifetime under certain top-force loading conditions. Experimental thermo-mechanical Temperature Cycling on Board (TCoB) board-level reliability tests verified these findings, highlighting the importance of avoiding excessive top-side forces and thermomechanical cycling numbers to prevent solder ball bridging. Electromagnetic characterization of TIM materials’ electrical properties and RF measurements of the radar system with TSC were also conducted. A key takeaway is the recommendation to use high-loss TIM materials to prevent RF performance deterioration when applying TSC with metallic components. By optimizing FO-WLP/eWLB packaging for MMICs in automotive radar applications, we can enable more efficient, reliable, and high-performance systems that make our roads safer and more efficient.
随着汽车工业的不断发展,对高性能雷达系统的需求也在增加。为了满足这一需求,我们探索了77 ghz范围内单片微波集成电路(mmic)的扇出晶圆级封装(FO-WLP)或嵌入式晶圆级球栅阵列(eWLB)的潜力,重点是通过顶部冷却(TSC)进行热管理。我们的热模拟表明,使用薄的、高导热的热界面材料(TIM)层,热阻可以降低高达75%。我们评估了各种情况,包括TIM/吸收层厚度和导热系数的变化,芯片/封装尺寸的影响,以及模具厚度的影响。为了确保可靠性,我们使用热力学模拟分析了TIM压缩对MMIC施加的压力和力的力学方面。我们的结果表明,在一定的顶力加载条件下,区域的寿命损失小于10%。实验热机械板上温度循环(TCoB)板级可靠性测试验证了这些发现,强调了避免过多的顶部力和热机械循环次数以防止焊接球桥接的重要性。对TIM材料的电性能进行了电磁表征,并对雷达系统进行了射频测量。一个关键的结论是,在将TSC应用于金属元件时,建议使用高损耗TIM材料,以防止RF性能恶化。通过优化汽车雷达应用中mmic的FO-WLP/eWLB封装,我们可以实现更高效、可靠和高性能的系统,使我们的道路更安全、更高效。
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information IEEE元件、包装与制造技术汇刊信息
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-08-22 DOI: 10.1109/TCPMT.2025.3593032
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引用次数: 0
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IEEE Transactions on Components, Packaging and Manufacturing Technology
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