Pub Date : 2024-08-13DOI: 10.1109/TCPMT.2024.3442828
Pei Ge;Hao-Ran Zhu;Jia-Guo Lu
In this article, a novel ultrawide wire-bonding and vertical via interconnection are proposed for 3-D system in package (SiP) by embedded nonuniform elliptic technique. The vertical compensation structure of the bonding wires is constructed by an elliptic capacitive stripline with a series inductance short via. For vertical via interconnection, the elliptical slot is employed to act as a seventh-order low-pass filter with the quasi-coaxial structure, which is formed by the signal hole surrounded by several grounded holes. The impedance fluctuation is significantly reduced by gradually changing the width of the elliptic structure. The coupling between the adjacent wires is added to build the equivalent circuit model, which can accurately analyze the transmission behavior of the wire-bonding interconnection. From the measurement results, the return loss is better than 15 dB and the insertion loss is less than 1 dB within the frequency range of dc-43.5 GHz.
{"title":"A DC-43.5 GHz Wire-Bonding and Vertical Via Interconnection by Embedded Nonuniform Elliptical Technique for 3-D System in Package","authors":"Pei Ge;Hao-Ran Zhu;Jia-Guo Lu","doi":"10.1109/TCPMT.2024.3442828","DOIUrl":"10.1109/TCPMT.2024.3442828","url":null,"abstract":"In this article, a novel ultrawide wire-bonding and vertical via interconnection are proposed for 3-D system in package (SiP) by embedded nonuniform elliptic technique. The vertical compensation structure of the bonding wires is constructed by an elliptic capacitive stripline with a series inductance short via. For vertical via interconnection, the elliptical slot is employed to act as a seventh-order low-pass filter with the quasi-coaxial structure, which is formed by the signal hole surrounded by several grounded holes. The impedance fluctuation is significantly reduced by gradually changing the width of the elliptic structure. The coupling between the adjacent wires is added to build the equivalent circuit model, which can accurately analyze the transmission behavior of the wire-bonding interconnection. From the measurement results, the return loss is better than 15 dB and the insertion loss is less than 1 dB within the frequency range of dc-43.5 GHz.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142219866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-05DOI: 10.1109/TCPMT.2024.3438373
Bo Peng;Yaya Liang;Cong Liu;Ling Gao;Linjie Liu;Mingyang Wang;Zuoteng Gan;Pingan Du
The escalating integration level of system-in-package (SiP) has brought about significant challenges in thermal management. To meet the requirements of ever-increasing heat flux of SiP system with multichips, a method of embedding cooling microchannels into high temperature co-fired ceramics (HTCCs) substrates is proposed in this article. First, five-microchannels embedded topology structure are designed to investigate their heat transfer performance in chip cooling in terms of the fluid-thermal coupling numerical simulations, and the results show that the spider-netted microchannel yields the best heat transfer performance, especially for the chip with high heat flux, and the conclusion that the spider-netted structure has superior heat dissipation is verified through experiments. Furthermore, a personalized spider-netted microchannel parallel structure relying the distribution of multichips heat flux is proposed to achieve efficient heat dissipation for SiP system, resulting in reduced chip temperatures and minimized interference from chips with high heat flux density on neighboring chips. Finally, a series of experiments are carried out to verify the feasibility of the designed microchannel structure for SiP. The research results indicate that embedding microchannels in HTCC substrates can be employed to improve the thermal dissipation capability of SiP and enhance chips integration.
{"title":"Design of Microchannels Embedded in HTCC Substrate for Heat Dissipation of SiP With Multiple Chips","authors":"Bo Peng;Yaya Liang;Cong Liu;Ling Gao;Linjie Liu;Mingyang Wang;Zuoteng Gan;Pingan Du","doi":"10.1109/TCPMT.2024.3438373","DOIUrl":"10.1109/TCPMT.2024.3438373","url":null,"abstract":"The escalating integration level of system-in-package (SiP) has brought about significant challenges in thermal management. To meet the requirements of ever-increasing heat flux of SiP system with multichips, a method of embedding cooling microchannels into high temperature co-fired ceramics (HTCCs) substrates is proposed in this article. First, five-microchannels embedded topology structure are designed to investigate their heat transfer performance in chip cooling in terms of the fluid-thermal coupling numerical simulations, and the results show that the spider-netted microchannel yields the best heat transfer performance, especially for the chip with high heat flux, and the conclusion that the spider-netted structure has superior heat dissipation is verified through experiments. Furthermore, a personalized spider-netted microchannel parallel structure relying the distribution of multichips heat flux is proposed to achieve efficient heat dissipation for SiP system, resulting in reduced chip temperatures and minimized interference from chips with high heat flux density on neighboring chips. Finally, a series of experiments are carried out to verify the feasibility of the designed microchannel structure for SiP. The research results indicate that embedding microchannels in HTCC substrates can be employed to improve the thermal dissipation capability of SiP and enhance chips integration.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141938968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-05DOI: 10.1109/TCPMT.2024.3438763
Da-Lin Li;Mu-Shui Zhang;Zi-Xin Wang
In this article, a novel and compact centrosymmetric mushroom electromagnetic bandgap (EBG) structure is proposed for multiband power noise suppression. Different mushroom patches are integrated in a compact unit cell in a centrosymmetric pattern to generate multiple stopbands. The stopbands can be easily designed and adjusted by the area ratio of different subpatches and scaling. The most obvious advantages of the proposed method are compact in structure and easy in design, especially for tri-band and four-band stopband power noise suppression. EBG structures with double bands, treble bands, and four bands are designed and fabricated. Measurements and simulations are performed to verify the multiband characteristic, and good agreement is observed. This structure provides a simple, compact, and attractive solution for multiband power noise suppression with more than three bands.
{"title":"A Novel and Compact Centrosymmetric EBG Structure for Multiband Power Noise Suppression","authors":"Da-Lin Li;Mu-Shui Zhang;Zi-Xin Wang","doi":"10.1109/TCPMT.2024.3438763","DOIUrl":"10.1109/TCPMT.2024.3438763","url":null,"abstract":"In this article, a novel and compact centrosymmetric mushroom electromagnetic bandgap (EBG) structure is proposed for multiband power noise suppression. Different mushroom patches are integrated in a compact unit cell in a centrosymmetric pattern to generate multiple stopbands. The stopbands can be easily designed and adjusted by the area ratio of different subpatches and scaling. The most obvious advantages of the proposed method are compact in structure and easy in design, especially for tri-band and four-band stopband power noise suppression. EBG structures with double bands, treble bands, and four bands are designed and fabricated. Measurements and simulations are performed to verify the multiband characteristic, and good agreement is observed. This structure provides a simple, compact, and attractive solution for multiband power noise suppression with more than three bands.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141938964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-05DOI: 10.1109/TCPMT.2024.3430936
Danyu Yang;Yuandan Dong
The study presents a self-packaged bandpass filter (BPF) with miniaturization and wide stopband based on shielded stripline resonators using a mixed coupling scheme. First, the miniaturized effect and the field distribution at fundamental and spurious modes of a single resonator are analyzed. Then, a mixed coupling scheme is applied to two coupled resonators for spurious passband suppression to achieve wide stopband, which is verified by the second-order BPF response. Finally, shielded stripline resonators with a mixed coupling scheme are further applied to the design of the fourth-order 5G N78 band BPF. The final self-packaged fourth-order BPF achieves an extremely small volume of $0.144times 0.139times 0.025lambda 3$ g, whose stopband is extended up to 5.11f0 with a rejection level better than 20 dB or 3.37f0 with a rejection better than 50 dB.
{"title":"Packaged 5G Filter With Miniaturization and Wide Stopband Based on Shielded Stripline Resonator","authors":"Danyu Yang;Yuandan Dong","doi":"10.1109/TCPMT.2024.3430936","DOIUrl":"10.1109/TCPMT.2024.3430936","url":null,"abstract":"The study presents a self-packaged bandpass filter (BPF) with miniaturization and wide stopband based on shielded stripline resonators using a mixed coupling scheme. First, the miniaturized effect and the field distribution at fundamental and spurious modes of a single resonator are analyzed. Then, a mixed coupling scheme is applied to two coupled resonators for spurious passband suppression to achieve wide stopband, which is verified by the second-order BPF response. Finally, shielded stripline resonators with a mixed coupling scheme are further applied to the design of the fourth-order 5G N78 band BPF. The final self-packaged fourth-order BPF achieves an extremely small volume of \u0000<inline-formula> <tex-math>$0.144times 0.139times 0.025lambda 3$ </tex-math></inline-formula>\u0000g, whose stopband is extended up to 5.11f0 with a rejection level better than 20 dB or 3.37f0 with a rejection better than 50 dB.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141938963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/tcpmt.2024.3436672
Surila Guglani, Asha Kumari Jakhar, Avirup Dasgupta, Sourajeet Roy
{"title":"Combining Prior Knowledge with Transfer Learning (PKID-TL) for Fast Neural Network Enabled Uncertainty Quantification of Graphene On-Chip Interconnects","authors":"Surila Guglani, Asha Kumari Jakhar, Avirup Dasgupta, Sourajeet Roy","doi":"10.1109/tcpmt.2024.3436672","DOIUrl":"https://doi.org/10.1109/tcpmt.2024.3436672","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/tcpmt.2024.3436545
Laura Van Messem, Arno Moerman, Olivier Caytan, Hendrik Rogier, Sam Lemey
{"title":"Compact Self-Shielding Components for Beamforming Networks Implemented in Substrate Integrated Coaxial Line Technology","authors":"Laura Van Messem, Arno Moerman, Olivier Caytan, Hendrik Rogier, Sam Lemey","doi":"10.1109/tcpmt.2024.3436545","DOIUrl":"https://doi.org/10.1109/tcpmt.2024.3436545","url":null,"abstract":"","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141887303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/TCPMT.2024.3436595
Haifeng Chen;Wangyong Chen;Jiahui Chen;Haoyu Zhang;Linlin Cai
With the rapid increase in chip scale, today’s high-performance integrated circuits are facing increasingly complex thermal management challenges. It is often time-consuming to obtain a sufficiently fine-grained temperature distribution during full-chip thermal analysis. In this article, we propose a novel and efficient on-chip thermal prediction method based on a self-adapting power density sampling technique. The new method consists of a few steps. First, a partitioning strategy is employed based on the power density sampling technique on the layout, where each sample point corresponds to a distinct subregion. Analyzing the power information of standard cells within each subregion, we generate a tile-based power density map (PDM). Subsequently, the Sobel convolution, threshold filtering, K-means clustering, and self-adapting power density sampling algorithms are applied to the PDM to identify critical subareas (CSAs) within the layout and ensure the precision of temperature predictions in these areas. Finally, by conducting parallel finite element method (FEM) based thermal simulations on subregions, we efficiently extract critical temperature information (critical T info.) for the chip. This encompasses identifying the subregions with the highest average temperature (Tavg), pinpointing the coordinates of peak temperature (Tpeak) occurrences, and highlighting areas with notable temperature gradients (Tgrad). Our approach not only achieves precise temperature results with an error margin of about 4% but also outperforms traditional FEM full-chip simulations in computational efficiency while providing a fine-grained thermal map of the chip.
{"title":"Self-Adapting Power Density Sampling for On-Chip Thermal Prediction With Transistor-Level Granularity","authors":"Haifeng Chen;Wangyong Chen;Jiahui Chen;Haoyu Zhang;Linlin Cai","doi":"10.1109/TCPMT.2024.3436595","DOIUrl":"10.1109/TCPMT.2024.3436595","url":null,"abstract":"With the rapid increase in chip scale, today’s high-performance integrated circuits are facing increasingly complex thermal management challenges. It is often time-consuming to obtain a sufficiently fine-grained temperature distribution during full-chip thermal analysis. In this article, we propose a novel and efficient on-chip thermal prediction method based on a self-adapting power density sampling technique. The new method consists of a few steps. First, a partitioning strategy is employed based on the power density sampling technique on the layout, where each sample point corresponds to a distinct subregion. Analyzing the power information of standard cells within each subregion, we generate a tile-based power density map (PDM). Subsequently, the Sobel convolution, threshold filtering, K-means clustering, and self-adapting power density sampling algorithms are applied to the PDM to identify critical subareas (CSAs) within the layout and ensure the precision of temperature predictions in these areas. Finally, by conducting parallel finite element method (FEM) based thermal simulations on subregions, we efficiently extract critical temperature information (critical T info.) for the chip. This encompasses identifying the subregions with the highest average temperature (Tavg), pinpointing the coordinates of peak temperature (Tpeak) occurrences, and highlighting areas with notable temperature gradients (Tgrad). Our approach not only achieves precise temperature results with an error margin of about 4% but also outperforms traditional FEM full-chip simulations in computational efficiency while providing a fine-grained thermal map of the chip.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-31DOI: 10.1109/TCPMT.2024.3436039
Iqram Haider;Shiban Kishen Koul;Ananjan Basu
This article presents a new class of compact, inline waveguide bandpass filters with sharp rejection capabilities at the upper stopband using a novel nonlinear frequency variant coupling (NFVC) inverter, which can be fabricated only by 3-D printing. The proposed NFVC inverter is composed of three closely spaced posts, including the middle one slanted, arranged at the center of the waveguide’s broad wall. Utilizing the novel slanted post, this inverter can provide two poles above three TZs. Additionally, one of the TZs can be located very close to both sides of the passband by changing the middle post’s slant angle. To demonstrate its usefulness, a fourth-order inline waveguide filter with an operating frequency of 7.9 GHz, a bandwidth (BW) of 1.5 GHz, and three TZs is designed, fabricated, and measured. As will be seen, conventional manufacturing methods, such as milling, are impractical for this structure. Furthermore, the measured results are in reasonable agreement with the electromagnetic (EM) simulated ones.
{"title":"A 3-D Printed Compact Inline Waveguide Filter With Transmission Zeros Based on Strongly Coupled Novel Triple-Post Arrangement","authors":"Iqram Haider;Shiban Kishen Koul;Ananjan Basu","doi":"10.1109/TCPMT.2024.3436039","DOIUrl":"10.1109/TCPMT.2024.3436039","url":null,"abstract":"This article presents a new class of compact, inline waveguide bandpass filters with sharp rejection capabilities at the upper stopband using a novel nonlinear frequency variant coupling (NFVC) inverter, which can be fabricated only by 3-D printing. The proposed NFVC inverter is composed of three closely spaced posts, including the middle one slanted, arranged at the center of the waveguide’s broad wall. Utilizing the novel slanted post, this inverter can provide two poles above three TZs. Additionally, one of the TZs can be located very close to both sides of the passband by changing the middle post’s slant angle. To demonstrate its usefulness, a fourth-order inline waveguide filter with an operating frequency of 7.9 GHz, a bandwidth (BW) of 1.5 GHz, and three TZs is designed, fabricated, and measured. As will be seen, conventional manufacturing methods, such as milling, are impractical for this structure. Furthermore, the measured results are in reasonable agreement with the electromagnetic (EM) simulated ones.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141864150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-30DOI: 10.1109/TCPMT.2024.3435867
Bo Li;Min Tang;Junfa Mao
In this article, we present an efficient Laguerre-based finite element method with proper orthogonal decomposition (LBFEM-POD) for transient thermomechanical analysis of electronic packages. In the match-on-in-order scheme, we utilize a new type of basis function composed of three adjacent Laguerre polynomials, which successfully eliminates the accumulation terms in the traditional Laguerre-based method. By combining with the POD technique, the proposed method effectively reduces the order of thermomechanical model, enabling rapid prediction of temperature and thermal stress responses within the Laguerre domain. The accuracy and efficiency of the LBFEM-POD method are demonstrated by several numerical examples.
本文针对电子封装的瞬态热机械分析，提出了一种具有适当正交分解（LBFEM-POD）的高效拉盖尔有限元方法。在阶内匹配方案中，我们采用了一种由三个相邻拉盖尔多项式组成的新型基函数，成功消除了传统拉盖尔法中的累积项。通过与 POD 技术相结合，所提出的方法有效地降低了热力学模型的阶数，实现了在拉盖尔域内对温度和热应力响应的快速预测。几个数值实例证明了 LBFEM-POD 方法的准确性和高效性。
{"title":"An Efficient LBFEM-POD Scheme for Transient Thermomechanical Simulation of Electronic Packages","authors":"Bo Li;Min Tang;Junfa Mao","doi":"10.1109/TCPMT.2024.3435867","DOIUrl":"10.1109/TCPMT.2024.3435867","url":null,"abstract":"In this article, we present an efficient Laguerre-based finite element method with proper orthogonal decomposition (LBFEM-POD) for transient thermomechanical analysis of electronic packages. In the match-on-in-order scheme, we utilize a new type of basis function composed of three adjacent Laguerre polynomials, which successfully eliminates the accumulation terms in the traditional Laguerre-based method. By combining with the POD technique, the proposed method effectively reduces the order of thermomechanical model, enabling rapid prediction of temperature and thermal stress responses within the Laguerre domain. The accuracy and efficiency of the LBFEM-POD method are demonstrated by several numerical examples.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141864152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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