Pub Date : 2024-11-18DOI: 10.1109/TCPMT.2024.3501478
Augusto Rodrigues;Julien Magnien;Roland Brunner;Ali Roshanghias
The solder-based interconnections have been the backbone of microelectronics. However, the ever-growing trends toward ultrahigh-density interconnected systems with higher thermal and mechanical stability drove the solder to its limit. Alternatively, the solid-state copper (Cu)-based interconnects have gained momentum not only due to their compatibility with back-end-of-the-line and downscalability through the lithography process but also due to the unique characteristics of Cu (e.g., low resistivity, high-temperature stability, high electromigration resistance, as well as low cost). As an interconnect, Cu pillars favor ultrafine pitch applications, as the bump height and footprint can be well-controlled. However, the conventional direct (thermocompression) Cu pillar bonding involves high bonding temperature and pressure. The use of solder caps alleviated these requirements but at the cost of possible issues, such as thermal mismatch and brittle intermetallic compound. Therefore, a solder-free, all-Cu interconnect solution with reduced processing temperature and pressures is currently the holy grail in advanced microelectronics packaging. Accordingly, in this study, Cu-based interconnects consisting of Cu pillars and Cu microparticle (MP) sinter paste caps were fabricated and investigated as an alternative to direct Cu pillar bonding and solder caps. Here, recently developed Cu-based sinter-paste materials [i.e., pressure-less, pressure-assisted Cu sinter pastes, and Cu-based transient liquid phase sinter transient liquid phase sintering (TLPS) pastes] were assessed and applied to join Cu pillars. The electrical and mechanical properties as well as the long-term reliability of the bonded samples were characterized and compared. The bonded interface was also examined using 3-D-tomography analysis.
{"title":"Cu Sintering for Cu Pillar Bonding: A Comparative Study Among Pressure-Less, Pressure-Assisted, and Transient Liquid Phase Sinter Pastes","authors":"Augusto Rodrigues;Julien Magnien;Roland Brunner;Ali Roshanghias","doi":"10.1109/TCPMT.2024.3501478","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3501478","url":null,"abstract":"The solder-based interconnections have been the backbone of microelectronics. However, the ever-growing trends toward ultrahigh-density interconnected systems with higher thermal and mechanical stability drove the solder to its limit. Alternatively, the solid-state copper (Cu)-based interconnects have gained momentum not only due to their compatibility with back-end-of-the-line and downscalability through the lithography process but also due to the unique characteristics of Cu (e.g., low resistivity, high-temperature stability, high electromigration resistance, as well as low cost). As an interconnect, Cu pillars favor ultrafine pitch applications, as the bump height and footprint can be well-controlled. However, the conventional direct (thermocompression) Cu pillar bonding involves high bonding temperature and pressure. The use of solder caps alleviated these requirements but at the cost of possible issues, such as thermal mismatch and brittle intermetallic compound. Therefore, a solder-free, all-Cu interconnect solution with reduced processing temperature and pressures is currently the holy grail in advanced microelectronics packaging. Accordingly, in this study, Cu-based interconnects consisting of Cu pillars and Cu microparticle (MP) sinter paste caps were fabricated and investigated as an alternative to direct Cu pillar bonding and solder caps. Here, recently developed Cu-based sinter-paste materials [i.e., pressure-less, pressure-assisted Cu sinter pastes, and Cu-based transient liquid phase sinter transient liquid phase sintering (TLPS) pastes] were assessed and applied to join Cu pillars. The electrical and mechanical properties as well as the long-term reliability of the bonded samples were characterized and compared. The bonded interface was also examined using 3-D-tomography analysis.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 1","pages":"224-231"},"PeriodicalIF":2.3,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-11DOI: 10.1109/TCPMT.2024.3495520
Sanghoon D. Lee;Seung Yoon Lee;Andrew S. Kim;Brett Ringel;Wenshan Cai;Nima Ghalichechian;John D. Cressler
We present a W-band on-chip planar inverted-F antenna (PIFA) featuring high efficiency and wide bandwidth. The proposed on-chip antenna (OCA) incorporates a miniaturized $0.12~lambda _{{0}}^{{2}}$ -sized substrate-integrated air cavity (SIC) that creates a high dielectric discontinuity between air and silicon enabling an increase in radiation efficiency by suppressing the parallel plate modes. Forming air cavities in the substrate avoids the need for precise heterogeneous packaging, in contrast with integrating dielectric resonators or superstrate dielectrics with OCAs. To the best of the authors’ knowledge, a through-silicon via (TSV) was incorporated into a commercial silicon-based OCA die for the first time, enhancing the electrical connection to the off-chip ground and mechanical stability. The OCA is fabricated using a 180 nm SiGe BiCMOS process, with CMOS-compatible postprocessing for SICs and TSVs. The proposed OCA complies with various design rule check (DRC) guidelines, including minimum trace width sizing and metal density considerations to achieve a high manufacturing yield. The SIC is created by etching the bottom silicon substrate using a deep reactive-ion etching (DRIE) process. We manufacture an Ag TSV by filling the SIC with Ag epoxy to prevent expensive postprocessing. Measurements of the radiation patterns of the W-band antenna were performed using a robotic arm. The PIFA achievesa −10-dB bandwidth from 89 to 105 GHz with a fractional bandwidth of 16.3%. It also delivers an 11.4 GHz 1-dB gain bandwidth with a maximum realized gain of 1.6 dBi, corresponding to a peak efficiency of 72%. This research leverages commercial SiGe BiCMOS technology to achieve high efficiency and wide bandwidth, with TSVs providing a robust ground plane and potential for use as signal paths in monolithic integrated circuits.
{"title":"Wideband, High Efficiency On-Chip Monolithic Integrated Antenna at W-Band Using Miniaturized Cavity and Through Silicon Via","authors":"Sanghoon D. Lee;Seung Yoon Lee;Andrew S. Kim;Brett Ringel;Wenshan Cai;Nima Ghalichechian;John D. Cressler","doi":"10.1109/TCPMT.2024.3495520","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3495520","url":null,"abstract":"We present a W-band on-chip planar inverted-F antenna (PIFA) featuring high efficiency and wide bandwidth. The proposed on-chip antenna (OCA) incorporates a miniaturized \u0000<inline-formula> <tex-math>$0.12~lambda _{{0}}^{{2}}$ </tex-math></inline-formula>\u0000-sized substrate-integrated air cavity (SIC) that creates a high dielectric discontinuity between air and silicon enabling an increase in radiation efficiency by suppressing the parallel plate modes. Forming air cavities in the substrate avoids the need for precise heterogeneous packaging, in contrast with integrating dielectric resonators or superstrate dielectrics with OCAs. To the best of the authors’ knowledge, a through-silicon via (TSV) was incorporated into a commercial silicon-based OCA die for the first time, enhancing the electrical connection to the off-chip ground and mechanical stability. The OCA is fabricated using a 180 nm SiGe BiCMOS process, with CMOS-compatible postprocessing for SICs and TSVs. The proposed OCA complies with various design rule check (DRC) guidelines, including minimum trace width sizing and metal density considerations to achieve a high manufacturing yield. The SIC is created by etching the bottom silicon substrate using a deep reactive-ion etching (DRIE) process. We manufacture an Ag TSV by filling the SIC with Ag epoxy to prevent expensive postprocessing. Measurements of the radiation patterns of the W-band antenna were performed using a robotic arm. The PIFA achievesa −10-dB bandwidth from 89 to 105 GHz with a fractional bandwidth of 16.3%. It also delivers an 11.4 GHz 1-dB gain bandwidth with a maximum realized gain of 1.6 dBi, corresponding to a peak efficiency of 72%. This research leverages commercial SiGe BiCMOS technology to achieve high efficiency and wide bandwidth, with TSVs providing a robust ground plane and potential for use as signal paths in monolithic integrated circuits.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2355-2363"},"PeriodicalIF":2.3,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-08DOI: 10.1109/TCPMT.2024.3493964
Kayla Y. Chuong;Jon A. Bock;Eric A. Patterson;Harlan J. Brown-Shaklee;Lukas Graber;Lauren M. Garten
Enhancing the lifetime of multilayer ceramic capacitors (MLCCs) is critical in many aerospace, naval, or electrical grid applications, where device failure could lead to catastrophic consequences. The migration of oxygen vacancies from the ceramic to the electrode interface under constant bias is known to reduce the lifetime of oxide-based MLCCs. Bias cycling presents an opportunity to enhance MLCC lifetime by reducing oxygen vacancy migration. The ideal frequency range is expected to lie between frequencies low enough to avoid self-heating but high enough to avoid interfacial defect formation. However, the impact of low-frequency bipolar voltage cycling (BVC) on MLCC degradation mechanisms has not been well studied. This work investigates the impact of periodic BVC on the degradation of MLCCs through highly accelerated lifetime testing (HALT) on X7R capacitors. HALT tests were conducted at 255 °C and 60 V using different switching frequencies: 0 (dc), 0.1, 2.5, and 10 Hz. BVC was found to improve the lifetime of MLCCs compared to dc test conditions. MLCCs tested at 10-Hz BVC showed a 311% increase in average time to failure compared to the dc case. Impedance spectroscopy shows that BVC decreases the rate of resistance degradation within MLCCs, indicating that oxygen vacancy migration to the electrodes is mitigated. The impedance spectra taken on BVC samples highlight how grain boundaries play a vital role in trapping oxygen vacancies. Periodic cycling causes oxygen vacancies to become trapped at grain boundaries, resulting in oxygen vacancies taking longer to reach the electrode interface and thus increasing MLCC lifetime. This work highlights not only how BVC can be used to increase MLCC lifetime but also how periodically cycling MLCCs could increase lifetime in extreme environments, such as at elevated temperatures and electric fields.
{"title":"Increasing Multilayer Ceramic Capacitor Lifetime With Bipolar Voltage Cycling","authors":"Kayla Y. Chuong;Jon A. Bock;Eric A. Patterson;Harlan J. Brown-Shaklee;Lukas Graber;Lauren M. Garten","doi":"10.1109/TCPMT.2024.3493964","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3493964","url":null,"abstract":"Enhancing the lifetime of multilayer ceramic capacitors (MLCCs) is critical in many aerospace, naval, or electrical grid applications, where device failure could lead to catastrophic consequences. The migration of oxygen vacancies from the ceramic to the electrode interface under constant bias is known to reduce the lifetime of oxide-based MLCCs. Bias cycling presents an opportunity to enhance MLCC lifetime by reducing oxygen vacancy migration. The ideal frequency range is expected to lie between frequencies low enough to avoid self-heating but high enough to avoid interfacial defect formation. However, the impact of low-frequency bipolar voltage cycling (BVC) on MLCC degradation mechanisms has not been well studied. This work investigates the impact of periodic BVC on the degradation of MLCCs through highly accelerated lifetime testing (HALT) on X7R capacitors. HALT tests were conducted at 255 °C and 60 V using different switching frequencies: 0 (dc), 0.1, 2.5, and 10 Hz. BVC was found to improve the lifetime of MLCCs compared to dc test conditions. MLCCs tested at 10-Hz BVC showed a 311% increase in average time to failure compared to the dc case. Impedance spectroscopy shows that BVC decreases the rate of resistance degradation within MLCCs, indicating that oxygen vacancy migration to the electrodes is mitigated. The impedance spectra taken on BVC samples highlight how grain boundaries play a vital role in trapping oxygen vacancies. Periodic cycling causes oxygen vacancies to become trapped at grain boundaries, resulting in oxygen vacancies taking longer to reach the electrode interface and thus increasing MLCC lifetime. This work highlights not only how BVC can be used to increase MLCC lifetime but also how periodically cycling MLCCs could increase lifetime in extreme environments, such as at elevated temperatures and electric fields.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 2","pages":"272-280"},"PeriodicalIF":2.3,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10747533","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-08DOI: 10.1109/TCPMT.2024.3493971
Vitaliy Smirnov;Andrey Gavrikov;Vladimir Neichev
This article shows that the results of experimental studies of thermoelectric properties of the insulated gate bipolar transistor (IGBT) power modules aimed at developing methods and means for measuring cross-couple thermal resistances between module transistors. The research has shown that the modulation method, which uses heating of a measured object with power modulated according to the harmonic law, has a number of advantages over standard methods based on measuring the transient thermal characteristics. It was possible to measure thermal resistance components “junction-top copper layer of the direct bond copper (DBC) board,” “junction-Al2O3 layer of the DBC board,” “junction-baseplate of the module body,” and “junction-heatsink” using the modulation method for all the IGBTs of the GD35PIT1205SN power module. Analysis of the results showed that the cross-couple thermal resistance between the transistors of the module may contain one or two components. If the transistors are located on the same DBC board and the heat flows between the module transistors within the same DBC board, then only one component appears. If the transistors are located on different DBC boards separated by a gap, then two components of thermal resistance appear.
{"title":"Measuring Specificities of Thermal Resistance of IGBT Power Modules","authors":"Vitaliy Smirnov;Andrey Gavrikov;Vladimir Neichev","doi":"10.1109/TCPMT.2024.3493971","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3493971","url":null,"abstract":"This article shows that the results of experimental studies of thermoelectric properties of the insulated gate bipolar transistor (IGBT) power modules aimed at developing methods and means for measuring cross-couple thermal resistances between module transistors. The research has shown that the modulation method, which uses heating of a measured object with power modulated according to the harmonic law, has a number of advantages over standard methods based on measuring the transient thermal characteristics. It was possible to measure thermal resistance components “junction-top copper layer of the direct bond copper (DBC) board,” “junction-Al2O3 layer of the DBC board,” “junction-baseplate of the module body,” and “junction-heatsink” using the modulation method for all the IGBTs of the GD35PIT1205SN power module. Analysis of the results showed that the cross-couple thermal resistance between the transistors of the module may contain one or two components. If the transistors are located on the same DBC board and the heat flows between the module transistors within the same DBC board, then only one component appears. If the transistors are located on different DBC boards separated by a gap, then two components of thermal resistance appear.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2348-2354"},"PeriodicalIF":2.3,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-06DOI: 10.1109/TCPMT.2024.3492672
Ming Kong;Yung-Cheng Lee;Christopher Oshman
Solder self-alignment is a crucial manufacturing technology for the cost-effective assembly of optoelectronic devices that require precise positioning. However, concerns remain about the quality of self-alignment, especially due to dynamic factors like mechanical vibrations from conveyor belts during the manufacturing process. Additionally, there has been a lack of comprehensive experimental studies and models to fully address these issues. In this article, the dynamic behavior of a ball grid array (BGA) flip-chip assembly reflowed under forced environmental periodical vibration was investigated. Due to the low dissipative force of the molten solder joint, resonant oscillations between chip and substrate were observed at around 12 Hz driving frequency. The maximum chip’s oscillation amplitude can reach more than $100mu$ m for only several microns’ driven amplitude on the substrate. This resonant motion can be “frozen in” during the solidification of the joint, resulting in large post-assembly misalignments. In order to reduce the adverse influence of environmental vibration on self-alignment accuracy, several feasible methods were proposed, including varying solder surface tension coefficient, adjusting solder joint aspect ratio, adjusting chip mass or the number of joint interconnections, in order to shift the resonant frequency of the to-be-assembled device to a range that is different from the frequency of environmental vibrations.
{"title":"The Impact of Substrate Vibrations on Self-Alignment Accuracy in BGA/Flip-Chip Assembly","authors":"Ming Kong;Yung-Cheng Lee;Christopher Oshman","doi":"10.1109/TCPMT.2024.3492672","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3492672","url":null,"abstract":"Solder self-alignment is a crucial manufacturing technology for the cost-effective assembly of optoelectronic devices that require precise positioning. However, concerns remain about the quality of self-alignment, especially due to dynamic factors like mechanical vibrations from conveyor belts during the manufacturing process. Additionally, there has been a lack of comprehensive experimental studies and models to fully address these issues. In this article, the dynamic behavior of a ball grid array (BGA) flip-chip assembly reflowed under forced environmental periodical vibration was investigated. Due to the low dissipative force of the molten solder joint, resonant oscillations between chip and substrate were observed at around 12 Hz driving frequency. The maximum chip’s oscillation amplitude can reach more than \u0000<inline-formula> <tex-math>$100mu$ </tex-math></inline-formula>\u0000m for only several microns’ driven amplitude on the substrate. This resonant motion can be “frozen in” during the solidification of the joint, resulting in large post-assembly misalignments. In order to reduce the adverse influence of environmental vibration on self-alignment accuracy, several feasible methods were proposed, including varying solder surface tension coefficient, adjusting solder joint aspect ratio, adjusting chip mass or the number of joint interconnections, in order to shift the resonant frequency of the to-be-assembled device to a range that is different from the frequency of environmental vibrations.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2373-2379"},"PeriodicalIF":2.3,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-05DOI: 10.1109/TCPMT.2024.3490672
Yuxiang Li;Zhili Long;Shuyuan Ye;Mian Yao;Xiangqing Li
Ultrasonic transducer (UT) plays a critical role in the aluminum wedge bonding of insulated gate bipolar transistors (IGBTs). Compared with the conventional single longitudinal transducer, we propose a dual-frequency UT that can effectively bond aluminum wires ranging from 100 to $500~mu $ m. The configuration of the transducer is designed by finite element method (FEM). A grooved annular flange is developed to obtain the transducer with the common nodal flanges of the two disparate frequencies. The effect of pretightening torques on the performances of the transducer is investigated, and the optimum torque with 55 kg cm is obtained. The impedance measurement proves that the dual frequency of the developed transducer is 61.3 and 86.5 kHz, respectively. Vibration tests indicate that the amplitudes of the capillary at low and high frequencies are 24.4 and $6.4~mu $ m, which can satisfy the bonding specification. Finally, the bonding of 100– $500~mu $ m aluminum wires is successfully realized, with the tensile strength exceeding standard strength.
超声换能器在绝缘栅双极晶体管（igbt）的铝楔键合中起着至关重要的作用。与传统的单纵向换能器相比，我们提出了一种双频UT，可以有效地结合100 ~ 500~mu $ m的铝线，并采用有限元法设计了换能器的结构。为了得到具有两个不同频率的共同节点法兰的换能器，设计了带槽的环形法兰。研究了预紧力矩对换能器性能的影响，得到了预紧力矩为55 kg cm的最佳预紧力矩。阻抗测量结果表明，所研制的换能器的双频分别为61.3 kHz和86.5 kHz。振动试验表明，毛细管在低、高频处的振幅分别为24.4和6.4~ $ mu $ m，满足粘接要求。最终成功实现了100 ~ 500~ μ $ m铝线的粘接，抗拉强度超过标准强度。
{"title":"Design and Experiment of a Dual-Frequency Ultrasonic Transducer for Aluminum Wedge Bonding","authors":"Yuxiang Li;Zhili Long;Shuyuan Ye;Mian Yao;Xiangqing Li","doi":"10.1109/TCPMT.2024.3490672","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3490672","url":null,"abstract":"Ultrasonic transducer (UT) plays a critical role in the aluminum wedge bonding of insulated gate bipolar transistors (IGBTs). Compared with the conventional single longitudinal transducer, we propose a dual-frequency UT that can effectively bond aluminum wires ranging from 100 to \u0000<inline-formula> <tex-math>$500~mu $ </tex-math></inline-formula>\u0000m. The configuration of the transducer is designed by finite element method (FEM). A grooved annular flange is developed to obtain the transducer with the common nodal flanges of the two disparate frequencies. The effect of pretightening torques on the performances of the transducer is investigated, and the optimum torque with 55 kg cm is obtained. The impedance measurement proves that the dual frequency of the developed transducer is 61.3 and 86.5 kHz, respectively. Vibration tests indicate that the amplitudes of the capillary at low and high frequencies are 24.4 and \u0000<inline-formula> <tex-math>$6.4~mu $ </tex-math></inline-formula>\u0000m, which can satisfy the bonding specification. Finally, the bonding of 100–\u0000<inline-formula> <tex-math>$500~mu $ </tex-math></inline-formula>\u0000m aluminum wires is successfully realized, with the tensile strength exceeding standard strength.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2364-2372"},"PeriodicalIF":2.3,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-05DOI: 10.1109/TCPMT.2024.3492022
Yung-Seop Lee;Hyewon Ko;Min Soo Park;Yonghan Ju
The design of memory semiconductors involves satisfying various customer demands and rapid provision of high-quality products; therefore, manufacturers have developed high-quality memory semiconductors using various technological elements to ensure their performance, reliability, and operation in various environments. Major quality aspects, such as warpage, stress, and strain, have different effects. Through experimental investigations, appropriate technological elements are selected using different technological elements (thickness and materials) to deliver the quality desired by customers. Experimental investigations may, however, delay product deliveries and incur considerable costs. This study proposes a new design method to overcome these limitations and determine optimal solutions based on the prepared technological elements for the quality desired by customers. The proposed method differs from traditional optimization methods in that it provides multiple solutions that satisfy the customer’s requirements. Traditional experimental designs that use orthogonal arrays fail to reflect the various constraints involved in memory semiconductor designs. We, therefore, aimed to solve this problem by applying an analysis methodology for a mixture of experimental designs based on orthogonal arrays using the coordinate exchange algorithm. A desirability function was, furthermore, used to assess the satisfaction of multiple quality characteristics (warpage, stress, strain), through which optimal packaging conditions were confirmed at approximately 12.5% of the total combination level. The results of this study are expected to improve the optimization and efficiency of semiconductor packaging processes.
{"title":"Custom Design Experiments for Semiconductor Package Optimization","authors":"Yung-Seop Lee;Hyewon Ko;Min Soo Park;Yonghan Ju","doi":"10.1109/TCPMT.2024.3492022","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3492022","url":null,"abstract":"The design of memory semiconductors involves satisfying various customer demands and rapid provision of high-quality products; therefore, manufacturers have developed high-quality memory semiconductors using various technological elements to ensure their performance, reliability, and operation in various environments. Major quality aspects, such as warpage, stress, and strain, have different effects. Through experimental investigations, appropriate technological elements are selected using different technological elements (thickness and materials) to deliver the quality desired by customers. Experimental investigations may, however, delay product deliveries and incur considerable costs. This study proposes a new design method to overcome these limitations and determine optimal solutions based on the prepared technological elements for the quality desired by customers. The proposed method differs from traditional optimization methods in that it provides multiple solutions that satisfy the customer’s requirements. Traditional experimental designs that use orthogonal arrays fail to reflect the various constraints involved in memory semiconductor designs. We, therefore, aimed to solve this problem by applying an analysis methodology for a mixture of experimental designs based on orthogonal arrays using the coordinate exchange algorithm. A desirability function was, furthermore, used to assess the satisfaction of multiple quality characteristics (warpage, stress, strain), through which optimal packaging conditions were confirmed at approximately 12.5% of the total combination level. The results of this study are expected to improve the optimization and efficiency of semiconductor packaging processes.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2380-2390"},"PeriodicalIF":2.3,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Surface-mounted technology (SMT) welding defect detection plays a key role in the printed circuit board assembly (PCBA) production process, which affects the use of electronic products and cost. Previous works tend to realize defect detection with only defect samples and they assume that there are sufficient defect samples. However, defect samples are usually difficult to collect in real-life scenarios while enough template samples can be easily obtained. In addition, most existing works carry out defect detection based on benchmarks with simple backgrounds of PCBA, which is not suitable for PCBA with complex structures in modern electronic product manufacturing. To address the above issues, we propose a template-guidance Siamese network based on YOLO for SMT welding defect detection (TGSYOLO), which is deployed on a real SMT automatic optical inspection (AOI) system. First, the two-stream structure is introduced to extract deep features in defect images and template images, in which template features serve as guidance knowledge. Then, a template fusion Transformer (TFT) is proposed to model global features between detect and template features in the low-level stage, which could acquire long-range correlations to force the network to focus on potential defect regions. Next, to avoid the disappearance of tiny defect features during deep feature fusion, a multiscale attention feature pyramid network (MAFPN) is proposed to directly fuse defect semantic information from low-level features, which retains detailed expressions of defects through skip connection and obtains compact fusion features. Furthermore, we collect limited welding defect samples based on more complex PCBA backgrounds than previous works through a real SMT AOI system. Experiments on the limited dataset show that TGSYOLO could reach 0.985 of mAP@0.5, 0.885 of mAP@0.75, and 0.984 of F1, which is 0.008, 0.054, and 0.025 higher than other SOTA methods. Also, generalization experiments on the public DeepPCB show that TGSYOLO could still reach the best with 0.991 of mAP@0.5 and 0.89 of mAP@0.75, which proves that TGSYOLO has good generalization performance.
{"title":"TGSYOLO: Template-Guidance Siamese Network for SMT Welding Defect Detection","authors":"Kehao Shi;Chengkai Yu;Yang Cao;Yu Kang;Yunbo Zhao;Lijun Zhao;Zhenyi Xu","doi":"10.1109/TCPMT.2024.3491163","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3491163","url":null,"abstract":"Surface-mounted technology (SMT) welding defect detection plays a key role in the printed circuit board assembly (PCBA) production process, which affects the use of electronic products and cost. Previous works tend to realize defect detection with only defect samples and they assume that there are sufficient defect samples. However, defect samples are usually difficult to collect in real-life scenarios while enough template samples can be easily obtained. In addition, most existing works carry out defect detection based on benchmarks with simple backgrounds of PCBA, which is not suitable for PCBA with complex structures in modern electronic product manufacturing. To address the above issues, we propose a template-guidance Siamese network based on YOLO for SMT welding defect detection (TGSYOLO), which is deployed on a real SMT automatic optical inspection (AOI) system. First, the two-stream structure is introduced to extract deep features in defect images and template images, in which template features serve as guidance knowledge. Then, a template fusion Transformer (TFT) is proposed to model global features between detect and template features in the low-level stage, which could acquire long-range correlations to force the network to focus on potential defect regions. Next, to avoid the disappearance of tiny defect features during deep feature fusion, a multiscale attention feature pyramid network (MAFPN) is proposed to directly fuse defect semantic information from low-level features, which retains detailed expressions of defects through skip connection and obtains compact fusion features. Furthermore, we collect limited welding defect samples based on more complex PCBA backgrounds than previous works through a real SMT AOI system. Experiments on the limited dataset show that TGSYOLO could reach 0.985 of mAP@0.5, 0.885 of mAP@0.75, and 0.984 of F1, which is 0.008, 0.054, and 0.025 higher than other SOTA methods. Also, generalization experiments on the public DeepPCB show that TGSYOLO could still reach the best with 0.991 of mAP@0.5 and 0.89 of mAP@0.75, which proves that TGSYOLO has good generalization performance.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2391-2404"},"PeriodicalIF":2.3,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-01DOI: 10.1109/TCPMT.2024.3489882
Zong-Rui Xu;Zhi-Yi Zhang;Lin-Sheng Wu;Jun-Fa Mao
A wideband digital conductive bridging random access memory (CBRAM)-based attenuator is proposed in this article, which can be used to realize reconfigurable RF systems-in-package (SiPs). The fabrication process is developed under the processing temperature lower than $120~^{circ }$ C, compatible with the advanced packaging technology on silicon substrates. The CBRAM switches based on Nafion are integrated with bridged-T-type resistor subnetworks to form single-bit attenuation unit cells, with wide attenuation range and large operating bandwidth. The resistance values and layouts of TaN thin film resistors are optimized when considering the parasitic effects. A 5-bit attenuator prototype is designed for 5–15 GHz, which is highly integrated with the occupied area of $0.84times 0.84$ mm2. The relative attenuation is from 1.0 to 31.3 dB at the central frequency, with a 2.2-dB insertion loss of the reference state. The return loss is better than 10 dB for all the 32 attenuation states. The root mean square (rms) attenuation error is less than 0.74 dB with a relative bandwidth of 100%. Moreover, the proposed digital CBRAM-based attenuator has the advantages of low actuation voltage and no dc power consumption, due to the nonvolatile RF switches used. It is a promising technique for the application of reconfigurable RF SiPs.
{"title":"A Wideband Digital Attenuator Based on Conductive Bridging Random Access Memory Switches for RF System-in-Package","authors":"Zong-Rui Xu;Zhi-Yi Zhang;Lin-Sheng Wu;Jun-Fa Mao","doi":"10.1109/TCPMT.2024.3489882","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3489882","url":null,"abstract":"A wideband digital conductive bridging random access memory (CBRAM)-based attenuator is proposed in this article, which can be used to realize reconfigurable RF systems-in-package (SiPs). The fabrication process is developed under the processing temperature lower than \u0000<inline-formula> <tex-math>$120~^{circ }$ </tex-math></inline-formula>\u0000C, compatible with the advanced packaging technology on silicon substrates. The CBRAM switches based on Nafion are integrated with bridged-T-type resistor subnetworks to form single-bit attenuation unit cells, with wide attenuation range and large operating bandwidth. The resistance values and layouts of TaN thin film resistors are optimized when considering the parasitic effects. A 5-bit attenuator prototype is designed for 5–15 GHz, which is highly integrated with the occupied area of \u0000<inline-formula> <tex-math>$0.84times 0.84$ </tex-math></inline-formula>\u0000 mm2. The relative attenuation is from 1.0 to 31.3 dB at the central frequency, with a 2.2-dB insertion loss of the reference state. The return loss is better than 10 dB for all the 32 attenuation states. The root mean square (rms) attenuation error is less than 0.74 dB with a relative bandwidth of 100%. Moreover, the proposed digital CBRAM-based attenuator has the advantages of low actuation voltage and no dc power consumption, due to the nonvolatile RF switches used. It is a promising technique for the application of reconfigurable RF SiPs.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 12","pages":"2321-2330"},"PeriodicalIF":2.3,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TCPMT.2024.3447124
Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang
The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.
{"title":"Failure Mechanism and Reliability Research of Solder Layer Tilt in Double-Sided Cooling Power Modules","authors":"Guoliao Sun;Wen Jing;Siyuan Lu;Cheng Peng;Wenhui Zhu;Liancheng Wang","doi":"10.1109/TCPMT.2024.3447124","DOIUrl":"https://doi.org/10.1109/TCPMT.2024.3447124","url":null,"abstract":"The double-sided cooling (DSC) module introduces greater thermomechanical stress compared to single-sided cooling (SSC) modules, posing a significant threat to reliability. The manufacturing process is complex, requiring multiple sintering or reflow operations. Due to gravitational factors, this results in uneven thickness in the solder layer, further exacerbating the reliability issues. This article investigates the failure mechanism of the middle solder layer (SAC305) in flip-chip double-sided cooling (FCDSC) modules under thermal cycling conditions using a thermomechanical coupled model. The results indicate that when the solder layer tilt angle reaches 1.53°, the lifetime is reduced by 99.3%. Local viscoplastic strain in the solder at stress concentration areas is identified as a key factor in solder layer fatigue failure. Subsequent experiments confirm that fatigue cracks occur on the thinner side of the solder layer. There, the coarsening of the Ag3Sn eutectic phase is more severe, leading to reduced tensile strength, thus becoming a crack initiation site. Finally, the protrusions-spacer technique is proposed to control the evenness of the solder layer, with experiments demonstrating an average reduction in solder layer tilt by 79.7%.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"14 9","pages":"1585-1592"},"PeriodicalIF":2.3,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142551996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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