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The Pressure Balance Effect of the Polytetrafluoroethylene Buffer Film in Pressure-Assisted Sintering Bonding 聚四氟乙烯缓冲膜在压力辅助烧结键合中的压力平衡效应
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-07-10 DOI: 10.1109/TCPMT.2025.3587762
Chenxiao Huang;Guisheng Zou;Shuaiqi Wang;Zehua Li;Guoqiang Qi;Lei Liu
Bonding pressure is one of the most important process parameters in pressure-assisted sintering bonding of the SiC power chips. The buffer film, placed between the pressure indenter and the chips, is essential to balance the pressure during the simultaneous bonding of multiple chips. However, the pressure balance mechanism, optimization, and enhancement of the buffer film have been rarely studied. In this study, a simulation model for the pressure balance effect of the polytetrafluoroethylene (PTFE) buffer film was established and verified by experimental results. The mean relative error (MRE) between the simulation and experimental results was merely 1.06% and 1.98%, regarding to the compression ratio and porosity of the joint. It was found that the pressure balance ability peaked at an optimal pressure for the first time. The optimal pressure value was negatively correlated with the sintering temperature regardless of the film thickness. To improve the pressure balance effect at lower pressure, drilled buffer films were proposed to enhance the pressure balance ability of the PTFE film. With a drilled film, the joint porosity difference between two chips with a 60- $mu $ m-height difference was reduced by 44%. The combination of films with different removal rates could further eliminate the influence of a specific height difference. This work is promising to deepen the understanding of the pressure balance mechanisms of the buffer film and pave the way for low-cost and low-pressure sintering bonding.
在SiC功率芯片的压力辅助烧结键合中,键合压力是最重要的工艺参数之一。缓冲膜放置在压力压头和芯片之间,在多个芯片同时粘合时平衡压力是必不可少的。然而,对缓冲膜的压力平衡机理、优化和增强等方面的研究却很少。本文建立了聚四氟乙烯(PTFE)缓冲膜压力平衡效应的仿真模型,并通过实验结果进行了验证。节理压缩比和孔隙率的平均相对误差(MRE)仅为1.06%和1.98%。结果表明,压力平衡能力首次在最佳压力下达到峰值。与膜厚无关,最佳压力值与烧结温度呈负相关。为了提高PTFE薄膜在较低压力下的压力平衡效果,提出了钻孔缓冲膜来提高PTFE薄膜的压力平衡能力。使用钻孔膜后,高度差为60 μ m的两个芯片之间的接头孔隙度差异降低了44%。不同去除率的膜组合可以进一步消除比高差的影响。这项工作有望加深对缓冲膜压力平衡机制的理解,为低成本、低压烧结键合铺平道路。
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE元件、封装与制造技术资讯汇刊
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-07-08 DOI: 10.1109/TCPMT.2025.3583863
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information IEEE元件、封装与制造技术学会汇刊
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-07-08 DOI: 10.1109/TCPMT.2025.3583865
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information IEEE元件、包装与制造技术汇刊信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-07-08 DOI: 10.1109/TCPMT.2025.3583861
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引用次数: 0
IC Modeling via Machine Learning Regressions: A Data-Driven Approach to SPICE Integration 通过机器学习回归的IC建模:SPICE集成的数据驱动方法
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-30 DOI: 10.1109/TCPMT.2025.3584470
Marco Atlante;Riccardo Trinchero;Igor S. Stievano;Mihai Telescu;Noël Tanguy
This article presents a method for generating accurate and efficient macromodels of high-speed input/output (I/O) buffers. Extending existing techniques, the proposed approach enables a modular and scalable model generation tool based on machine learning. Given the limitations of traditional methods, this work leverages kernel regression to develop SPICE-compliant models. Two compression schemes, random selection and Nyström approximation, are used and thoroughly compared to reduce the number of expansion terms, with beneficial effects in terms of compactness of the SPICE implementation. The effectiveness of the method in terms of model accuracy and efficiency is stressed through real devices and typical signal and power integrity (SIPI) cosimulations.
本文提出了一种生成高速输入/输出(I/O)缓冲区的精确和高效宏模型的方法。该方法扩展了现有技术,实现了基于机器学习的模块化和可扩展的模型生成工具。考虑到传统方法的局限性,这项工作利用内核回归来开发符合spice的模型。我们使用了随机选择和Nyström近似两种压缩方案,并对其进行了彻底的比较,以减少扩展项的数量,这在SPICE实现的紧凑性方面产生了有益的影响。通过实际设备和典型的信号功率完整性(SIPI)协同仿真,强调了该方法在模型精度和效率方面的有效性。
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引用次数: 0
Advanced Polymer Dry Etching Processes for Enhanced Cu/Polymer Hybrid Bonding 用于增强铜/聚合物杂化键合的先进聚合物干蚀刻工艺
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-30 DOI: 10.1109/TCPMT.2025.3584053
Jihun Kim;Nam Ki Hwang;Seul Ki Hong;Min Ju Kim;Jong Kyung Park
As semiconductor devices continue to demand higher performance and density, Cu/polymer hybrid structures have gained significant attention due to their potential to replace conventional SiO2 dielectrics. In this study, we explore the optimization of dry etching processes for 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane (p $text {V}_{{3}}text {D}_{{3}}$ ) a low-dielectric constant polymer ( $k =2.2$ ), used in Cu/polymer hybrid structures. By employing initiated chemical vapor deposition (iCVD) high purity, p $text {V}_{{3}}text {D}_{{3}}$ thin films with a thickness of 200 nm were deposited. Various gas mixtures, including O2, CF4, and Ar, were used for dry etching to evaluate the optimal etching conditions. Results show that the most anisotropic etching occurred with an O2/Ar gas mixture, achieving an etching depth of 200 nm and near-vertical sidewalls. Detailed analysis of the etching mechanism was conducted using Gibbs free energy calculations and X-ray photoelectron spectroscopy (XPS). The findings of this study provide valuable insights into the fabrication of high-density, high-performance Cu/polymer hybrid structures for next-generation semiconductor devices.
随着半导体器件不断要求更高的性能和密度,Cu/聚合物混合结构由于其取代传统SiO2介电材料的潜力而受到了极大的关注。在本研究中,我们探索了用于铜/聚合物杂化结构的低介电常数聚合物($k =2.2$) 1,3,5-三甲基-1,3,5-三乙烯基环三硅氧烷(p $text {V}_{{3}}text {D}_{{3}}$)的干刻蚀工艺优化。采用高纯度化学气相沉积(iCVD)法制备了厚度为200 nm的p $text {V}_{{3}}text {D}_{{3}}$薄膜。采用O2、CF4和Ar等不同混合气体进行干燥刻蚀,以评价最佳刻蚀条件。结果表明,在O2/Ar混合气体中,各向异性蚀刻效果最好,蚀刻深度为200 nm,侧壁接近垂直;利用吉布斯自由能计算和x射线光电子能谱(XPS)对腐蚀机理进行了详细分析。本研究的发现为下一代半导体器件的高密度、高性能铜/聚合物混合结构的制造提供了有价值的见解。
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Society Information IEEE元件、封装与制造技术学会汇刊
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-26 DOI: 10.1109/TCPMT.2025.3570046
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Information for Authors IEEE元件、封装与制造技术资讯汇刊
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-26 DOI: 10.1109/TCPMT.2025.3570044
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引用次数: 0
IEEE Transactions on Components, Packaging and Manufacturing Technology Publication Information IEEE元件、包装与制造技术汇刊信息
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-26 DOI: 10.1109/TCPMT.2025.3570042
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引用次数: 0
VO2 Switch-Based Tunable 3-D Cavity Filters 基于VO2开关的可调三维腔滤波器
IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-24 DOI: 10.1109/TCPMT.2025.3582617
Junwen Jiang;Raafat R. Mansour
This article presents the design and implementation of vanadium oxide (VO2) switch-based tunable 3-D cavity filters. The proposed concept employs switched strip lines integrated with cavity resonators to tune their resonance frequencies. This eliminates the need to use variable/switched capacitors, which are known to degrade the loaded Q of the filters over the tuning range. Combline filters and dielectric filters integrated with VO2 switches are designed, fabricated, and measured. The measurement results verify the tunability and feasibility of using the proposed tuning scheme to realize a relatively high-Q VO2 combline and dielectric resonator tunable filters that can maintain their Q values over the tuning range.
本文介绍了一种基于氧化钒(VO2)开关的可调谐三维腔滤波器的设计与实现。所提出的概念采用与腔谐振器集成的开关带线来调整其谐振频率。这消除了使用可变/开关电容器的需要,众所周知,这些电容器会降低滤波器在调谐范围内的负载Q。组合滤波器和介电滤波器集成的VO2开关的设计,制造和测量。测量结果验证了该调谐方案的可调性和可行性,实现了在调谐范围内保持Q值的高Q的VO2组合和介电谐振器可调谐滤波器。
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引用次数: 0
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