Abstract-In this work, to improve NiSi2-induced crystallization (SIC), NiSi2 formation was experimentally explored with three different silicidation processes. The nucleation and morphology of NiSi2 are significantly improved via lowering the heating rate of two-step rapid thermal processing (RTP). Further adopting the self-limiting formation method, a uniform NiSi2 with an ultra-thin thickness of 38 Å is attained. This formed NiSi2 warrants an increased crystallization and a reduced Ni contamination when used as the inductor to crystallize amorphous Si. Subsequently, integrating this NiSi2 formation scheme to crystallize the channel in a self-aligned manner, high-performance n-type poly-Si field-effect transistors are developed, showing superior electrical characteristics, including high mobility of 69.1 cm2 / V-s, steep subthreshold swing (SS) of 111.47 mV / dec, low leakage current of 4.67 pA / $mu$ m, and a large on-off current ratio of $2.51 times 10^7$ .
摘要--在这项工作中，为了改善 NiSi2 诱导结晶（SIC），通过三种不同的硅化工艺对 NiSi2 的形成进行了实验探索。通过降低两步快速热处理（RTP）的加热速率，NiSi2 的成核和形貌得到了显著改善。进一步采用自限制形成法，可获得厚度为 38 Å 的超薄均匀 NiSi2。这种已形成的 NiSi2 在用作非晶态硅的结晶感应器时，可提高结晶度并减少镍污染。随后，结合这种 NiSi2 形成方案，以自对准方式结晶沟道，开发出了高性能 n 型多晶硅场效应晶体管，显示出卓越的电气特性，包括 69.1 cm2 / V-s 的高迁移率、111.47 mV / dec 的陡峭亚阈值摆幅 (SS)、4.67 pA / $mu$ m 的低漏电流和 2.51 times 10^7$ 的大导通电流比。
{"title":"Self-Limiting Formation of NiSi₂ to Improve NiSi₂-Induced Crystallization and Develop High-Performance Poly-Si FETs With Self-Aligned NiSi₂-Induced Lateral Crystallization","authors":"Shujuan Mao;Xianglie Sun;Jinbiao Liu;Guobin Bai;Chenchen Zhang;Wenjuan Xiong;Jianfeng Gao;Jun Luo;Guilei Wang;Zhao Chao","doi":"10.1109/TED.2025.3527423","DOIUrl":"https://doi.org/10.1109/TED.2025.3527423","url":null,"abstract":"Abstract-In this work, to improve NiSi2-induced crystallization (SIC), NiSi2 formation was experimentally explored with three different silicidation processes. The nucleation and morphology of NiSi2 are significantly improved via lowering the heating rate of two-step rapid thermal processing (RTP). Further adopting the self-limiting formation method, a uniform NiSi2 with an ultra-thin thickness of 38 Å is attained. This formed NiSi2 warrants an increased crystallization and a reduced Ni contamination when used as the inductor to crystallize amorphous Si. Subsequently, integrating this NiSi2 formation scheme to crystallize the channel in a self-aligned manner, high-performance n-type poly-Si field-effect transistors are developed, showing superior electrical characteristics, including high mobility of 69.1 cm2 / V-s, steep subthreshold swing (SS) of 111.47 mV / dec, low leakage current of 4.67 pA / <inline-formula> <tex-math>$mu$ </tex-math></inline-formula> m, and a large on-off current ratio of <inline-formula> <tex-math>$2.51 times 10^7$ </tex-math></inline-formula>.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1160-1166"},"PeriodicalIF":2.9,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we investigate the effect of annealing in deuterium (D2) ambient on the performance and reliability of InGaZnO (IGZO) thin-film transistors (TFTs). We examined the current-voltage (I–V) characteristics, as well as the on-state current (${I}_{text {on}}$ ), off-state current (${I}_{text {off}}$ ), and subthreshold slope (SS) under three different conditions: after device fabrication (as-fabricated), in a deteriorated state (after 7 days), and after D2 annealing. To analyze the reliability of IGZO TFTs, the oxygen vacancy (${V}_{text {O}}$ ) behavior was observed by extracting the subgap density of state (DOS) using I–V data. Quantitative and qualitative analyses of the changes in ion distribution inside the IGZO channel after D2 annealing were performed by X-ray photoelectron spectroscopy (XPS) and secondary-ion mass spectrometry (SIMS), respectively, both of which verified the effect of the D2 annealing. The validity of our results was further verified by comparing them to model parameters generated using a technology computer-aided design (TCAD) simulation.
{"title":"Quantitative Analysis of Trap Behaviors for Deuterium Annealing Effect on IGZO TFTs by TCAD and Experimental Characterization","authors":"Hyeonjun Song;Soon Joo Yoon;Jaewook Yoo;Seongbin Lim;Ja-Yun Ku;Tae-Hyun Kil;Hongseung Lee;Jo Hak Jeong;Soyeon Kim;Moon-Kwon Lee;Hyeon-Sik Jang;Kiyoung Lee;Keun Heo;Jun-Young Park;Yoon Kyeung Lee;Hagyoul Bae","doi":"10.1109/TED.2025.3529399","DOIUrl":"https://doi.org/10.1109/TED.2025.3529399","url":null,"abstract":"In this article, we investigate the effect of annealing in deuterium (D2) ambient on the performance and reliability of InGaZnO (IGZO) thin-film transistors (TFTs). We examined the current-voltage (I–V) characteristics, as well as the on-state current (<inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>), off-state current (<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula>), and subthreshold slope (SS) under three different conditions: after device fabrication (as-fabricated), in a deteriorated state (after 7 days), and after D2 annealing. To analyze the reliability of IGZO TFTs, the oxygen vacancy (<inline-formula> <tex-math>${V}_{text {O}}$ </tex-math></inline-formula>) behavior was observed by extracting the subgap density of state (DOS) using I–V data. Quantitative and qualitative analyses of the changes in ion distribution inside the IGZO channel after D2 annealing were performed by X-ray photoelectron spectroscopy (XPS) and secondary-ion mass spectrometry (SIMS), respectively, both of which verified the effect of the D2 annealing. The validity of our results was further verified by comparing them to model parameters generated using a technology computer-aided design (TCAD) simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1180-1183"},"PeriodicalIF":2.9,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1109/TED.2025.3527434
Alberto Leggieri;Mostafa Behtouei;Graeme Burt;Valery Dolgashev;Franco Di Paolo;Bruno Spataro
A new principle for the design of frequency converters, operating at significantly higher power and efficiency than previous devices, is described in this article. The presented solution is implemented as a particular klystron topology for which a new design criterion is formulated through analytical expressions and a specific design procedure. The described frequency multiplier is suitable for telecommunications, nonlethal weapons, or scientific and medical particle accelerators, where the most interested exploitation is in the field of high gradient particle acceleration and free electron laser (FEL) devices for which no current sources meet the required performance. The frequency converter replaces all the low-level circuitry needed for frequency multiplication, representing a less expensive alternative. The presented structure can offer efficiencies in the range of 50%–60% in the Ka-band with power levels of 20–30 MW without phase noise, sideband generation, jitter, or chirp effects. The proposed principle is also applicable to other bands or power ranges.
{"title":"Harmonic Klystron Frequency Converter","authors":"Alberto Leggieri;Mostafa Behtouei;Graeme Burt;Valery Dolgashev;Franco Di Paolo;Bruno Spataro","doi":"10.1109/TED.2025.3527434","DOIUrl":"https://doi.org/10.1109/TED.2025.3527434","url":null,"abstract":"A new principle for the design of frequency converters, operating at significantly higher power and efficiency than previous devices, is described in this article. The presented solution is implemented as a particular klystron topology for which a new design criterion is formulated through analytical expressions and a specific design procedure. The described frequency multiplier is suitable for telecommunications, nonlethal weapons, or scientific and medical particle accelerators, where the most interested exploitation is in the field of high gradient particle acceleration and free electron laser (FEL) devices for which no current sources meet the required performance. The frequency converter replaces all the low-level circuitry needed for frequency multiplication, representing a less expensive alternative. The presented structure can offer efficiencies in the range of 50%–60% in the Ka-band with power levels of 20–30 MW without phase noise, sideband generation, jitter, or chirp effects. The proposed principle is also applicable to other bands or power ranges.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1396-1403"},"PeriodicalIF":2.9,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rapid progress has been achieved in experimental research of heterojunction organic phototransistors (HJ-OPTs); however, a model that captures essential physical phenomena occurring in HJ-OPTs is still lacking. Herein, we developed a compact model for HJ-OPTs by associating the excitonic photocarrier generation, the approach of equivalent the effect of light illumination as an additional gate voltage, and the power law dependence of photocarrier sheet density on light intensity with the generic 1-D charge drift theory for organic field-effect transistors (OFETs). The model can describe the output and transfer characteristics of HJ-OPTs both in the dark and under illumination. We fabricated and characterized an HJ-OPT based on C60/tin phthalocyanine (SnPc), and calculated its output and transfer characteristics, as well as photoresponsivity with the developed model. Excellent agreements between experiment and model fitting were obtained with the exception of the dark output curves in the case of high drain and gate voltages. Extending the model by incorporating the short-channel effect (SCE) and contact resistance effect, the imperfectness could be completely eliminated. The validation results showed that this model can be effectively applied to HJ-OPTs, which is of great significance for optimizing their performance in the future.
{"title":"Compact Modeling of Near-Infrared Heterojunction Organic Phototransistors Based on Tin Phthalocyanine","authors":"Qiyue Zhang;Xiancheng Cao;Jiapei Huang;Xiaoyue Xu;Yingquan Peng;Wenli Lv;Sunan Xu;Lei Sun;Lin Jiang","doi":"10.1109/TED.2025.3529402","DOIUrl":"https://doi.org/10.1109/TED.2025.3529402","url":null,"abstract":"Rapid progress has been achieved in experimental research of heterojunction organic phototransistors (HJ-OPTs); however, a model that captures essential physical phenomena occurring in HJ-OPTs is still lacking. Herein, we developed a compact model for HJ-OPTs by associating the excitonic photocarrier generation, the approach of equivalent the effect of light illumination as an additional gate voltage, and the power law dependence of photocarrier sheet density on light intensity with the generic 1-D charge drift theory for organic field-effect transistors (OFETs). The model can describe the output and transfer characteristics of HJ-OPTs both in the dark and under illumination. We fabricated and characterized an HJ-OPT based on C60/tin phthalocyanine (SnPc), and calculated its output and transfer characteristics, as well as photoresponsivity with the developed model. Excellent agreements between experiment and model fitting were obtained with the exception of the dark output curves in the case of high drain and gate voltages. Extending the model by incorporating the short-channel effect (SCE) and contact resistance effect, the imperfectness could be completely eliminated. The validation results showed that this model can be effectively applied to HJ-OPTs, which is of great significance for optimizing their performance in the future.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1308-1314"},"PeriodicalIF":2.9,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1109/TED.2025.3526906
Uttam Kumar Das;Xiaofeng Chen;Nabeel Aslam;Muhammad Ashraful Alam;Muhammad Mustafa Hussain;Nazek El-Atab
In this article, we report the fabrication and characterizations of sub-20-$mu $ m thin flexible Si die containing active devices. Thermally grown 2.62-nm silicon dioxide (SiO2), atomic layer deposition (ALD)-deposited 3-nm HfO2 (high-$kappa $ ), and 10-nm TiN layers are used to fabricate an array of MOSCAPs on Si wafers. The fabricated devices are characterized to analyze the doping density (${N} _{a}$ ), flat-band voltage (${V} _{text {fb}}$ ), threshold voltage (${V} _{text {th}}$ ), fixed oxide charge (${Q} _{f}$ ), and interface trap densities (${D} _{text {it}}$ ). Then, a deep reactive ion etching (DRIE) reduces the die thickness to $sim 15mu $ m for flexibility. The encapsulated flexible devices are found to have relatively better breakdown performances when tested in compressive stressing and no variations when in tensile stress. The time-dependent dielectric breakdown (TDDB) measurement shows a minimal variation in flexible and bulk devices. The TDDB and a voltage acceleration slope are projected in flexible devices after performing a 10000 times bending and relaxation process (cycling).
{"title":"Impact of Physical Stress on Gate Dielectric in Ultrathin Si Gate-Stack for Next-Generation Flexible CMOS Technology","authors":"Uttam Kumar Das;Xiaofeng Chen;Nabeel Aslam;Muhammad Ashraful Alam;Muhammad Mustafa Hussain;Nazek El-Atab","doi":"10.1109/TED.2025.3526906","DOIUrl":"https://doi.org/10.1109/TED.2025.3526906","url":null,"abstract":"In this article, we report the fabrication and characterizations of sub-20-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m thin flexible Si die containing active devices. Thermally grown 2.62-nm silicon dioxide (SiO2), atomic layer deposition (ALD)-deposited 3-nm HfO2 (high-<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula>), and 10-nm TiN layers are used to fabricate an array of MOSCAPs on Si wafers. The fabricated devices are characterized to analyze the doping density (<inline-formula> <tex-math>${N} _{a}$ </tex-math></inline-formula>), flat-band voltage (<inline-formula> <tex-math>${V} _{text {fb}}$ </tex-math></inline-formula>), threshold voltage (<inline-formula> <tex-math>${V} _{text {th}}$ </tex-math></inline-formula>), fixed oxide charge (<inline-formula> <tex-math>${Q} _{f}$ </tex-math></inline-formula>), and interface trap densities (<inline-formula> <tex-math>${D} _{text {it}}$ </tex-math></inline-formula>). Then, a deep reactive ion etching (DRIE) reduces the die thickness to <inline-formula> <tex-math>$sim 15mu $ </tex-math></inline-formula>m for flexibility. The encapsulated flexible devices are found to have relatively better breakdown performances when tested in compressive stressing and no variations when in tensile stress. The time-dependent dielectric breakdown (TDDB) measurement shows a minimal variation in flexible and bulk devices. The TDDB and a voltage acceleration slope are projected in flexible devices after performing a 10000 times bending and relaxation process (cycling).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"959-964"},"PeriodicalIF":2.9,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Back-end-of-line (BEOL) compatible and high-performance thin-film transistors (TFTs) and emer- ging memory devices trigger significant interest in their integration into 3-D computing and memory systems. In this work, we demonstrate, for the first time, the fully integrated 2T1C memory cells with InGaZnO TFTs and Hf0.5Zr0.5O2 (HZO)-based ferroelectric capacitors (FeCaps). The write and read operations of this recently pro- posed ferroelectric memory structure were systematically studied. The impacts of critical parameters on device per- formances were elucidated, including 1) applied voltage; 2) ferroelectric remnant polarization (${P}_{text {r}}$ ); 3) transistor threshold voltage (${V}_{text {th}}$ ); and 4) area ratio (AR) between the FeCap and the MOS capacitor of the Read transistor. The device with an AR of 1:8 can be operated with low voltages of 2 V for write and 2.5 V for read. Finally, the reliabilities of our fabricated 2T1C memory cells including retention ($geqq 10^{{5}}$ s) and endurance ($geqq 10^{{7}}$ cycles) were experimentally characterized.
{"title":"Back-End-of-Line Compatible 2T1C Memory Cell With InGaZnO Thin-Film Transistors and Hf₀.₅Zr₀.₅O₂-Based Ferroelectric Capacitors","authors":"Yize Sun;Shucheng Zhang;Qihan Liu;Yu Li;Haoyu Lu;Xumeng Zhang;Yingfen Wei;Mengwei Si;Hao Jiang;Qi Liu","doi":"10.1109/TED.2025.3529400","DOIUrl":"https://doi.org/10.1109/TED.2025.3529400","url":null,"abstract":"Back-end-of-line (BEOL) compatible and high-performance thin-film transistors (TFTs) and emer- ging memory devices trigger significant interest in their integration into 3-D computing and memory systems. In this work, we demonstrate, for the first time, the fully integrated 2T1C memory cells with InGaZnO TFTs and Hf0.5Zr0.5O2 (HZO)-based ferroelectric capacitors (FeCaps). The write and read operations of this recently pro- posed ferroelectric memory structure were systematically studied. The impacts of critical parameters on device per- formances were elucidated, including 1) applied voltage; 2) ferroelectric remnant polarization (<inline-formula> <tex-math>${P}_{text {r}}$ </tex-math></inline-formula>); 3) transistor threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>); and 4) area ratio (AR) between the FeCap and the MOS capacitor of the Read transistor. The device with an AR of 1:8 can be operated with low voltages of 2 V for write and 2.5 V for read. Finally, the reliabilities of our fabricated 2T1C memory cells including retention (<inline-formula> <tex-math>$geqq 10^{{5}}$ </tex-math></inline-formula> s) and endurance (<inline-formula> <tex-math>$geqq 10^{{7}}$ </tex-math></inline-formula> cycles) were experimentally characterized.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1097-1103"},"PeriodicalIF":2.9,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1109/TED.2025.3526104
Daniel Lizzit;Mattia Segatto;David Esseni
The progress of biologically inspired neuromorphic computing hardware in the last decade has been fostered also by the advancement in CMOS-compatible memristors, providing a nonvolatile storage of multiconductance states mimicking the synaptic weights in biological systems. This article is instead focused on the less-explored field of memcapacitors (MemCaps), which only very recently has attracted a renewed interest, and it is based on devices capable of tuning their capacitance. In particular, we present by means of extensive numerical simulations carefully calibrated against experimental data the operation of a two-terminal ferroelectric MemCap exhibiting multilevel, polarization-dependent capacitance values. The MemCap exploits a ferroelectric gated-diode structure, and it is thus fully compatible with CMOS processing. Our results show that multilevel operation is viable using properly shaped pulse trains at the gate terminal, and moreover, a nondestructive readout can be achieved by means of small-amplitude ac signals.
{"title":"A Novel Ferroelectric MemCapacitor Enabling Multilevel Operation","authors":"Daniel Lizzit;Mattia Segatto;David Esseni","doi":"10.1109/TED.2025.3526104","DOIUrl":"https://doi.org/10.1109/TED.2025.3526104","url":null,"abstract":"The progress of biologically inspired neuromorphic computing hardware in the last decade has been fostered also by the advancement in CMOS-compatible memristors, providing a nonvolatile storage of multiconductance states mimicking the synaptic weights in biological systems. This article is instead focused on the less-explored field of memcapacitors (MemCaps), which only very recently has attracted a renewed interest, and it is based on devices capable of tuning their capacitance. In particular, we present by means of extensive numerical simulations carefully calibrated against experimental data the operation of a two-terminal ferroelectric MemCap exhibiting multilevel, polarization-dependent capacitance values. The MemCap exploits a ferroelectric gated-diode structure, and it is thus fully compatible with CMOS processing. Our results show that multilevel operation is viable using properly shaped pulse trains at the gate terminal, and moreover, a nondestructive readout can be achieved by means of small-amplitude ac signals.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1083-1090"},"PeriodicalIF":2.9,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two-terminal perovskite/ACIGS tandem solar cells were numerically simulated and optimized using Silvaco TCAD tools. The perovskite model was designed to match the fabricated structure, making it suitable as the top cell in tandem configurations. Similarly, the ACIGS solar cell was calibrated to align with the fabricated device, ensuring it functions effectively as the bottom cell beneath the perovskite layer. Individual simulations of these cells demonstrated efficiencies of up to 20.92% for the perovskite and 23.6% for the ACIGS cell. The two-terminal tandem model was simulated by integrating the top and bottom cells, with a transparent contact electrically connecting the subcells in series. The impact of the notch region (minimum bandgap) and Ga composition in single- and double-graded profiles in thin-film ACIGS was examined. The primary goal was to increase ${V} _{text {oc}}$ without losing ${J} _{text {sc}}$ of the tandem device. To achieve this, the Ga content was varied from 0.30 to 0.85 (${x} _{{1}}$ ) for the first layer and from 0.05 to 0.60 (${x} _{{2}}$ ) for the second layer of the ACIGS material for various notch positions. The optimized tandem device achieved an efficiency of 29.14%, with a ${J} _{text {sc}}$ of 18.04 mA/cm2, a ${V} _{text {oc}}$ of 2.037 V, and a fill factor (FF) of 79.25%. This was achieved using a V-shaped Ga content gradient (GGI profile) with ${x} _{{1}} =0.70$ , ${x} _{{2}} =0.40$ , and a notch position of 200 nm for a 2-$mu $ m-thick ACIGS layer. These numerical simulations provide insights into the effect of Ga content and bandgap grading on tandem solar cell performance.
{"title":"Optimizing Thin-Film Tandem Solar Cells: The Impact of Bandgap Grading in ACIGS Subcell on Performance","authors":"Nour Boukortt;Antonio Garcia Loureiro;Johan Lauwaert","doi":"10.1109/TED.2025.3527954","DOIUrl":"https://doi.org/10.1109/TED.2025.3527954","url":null,"abstract":"Two-terminal perovskite/ACIGS tandem solar cells were numerically simulated and optimized using Silvaco TCAD tools. The perovskite model was designed to match the fabricated structure, making it suitable as the top cell in tandem configurations. Similarly, the ACIGS solar cell was calibrated to align with the fabricated device, ensuring it functions effectively as the bottom cell beneath the perovskite layer. Individual simulations of these cells demonstrated efficiencies of up to 20.92% for the perovskite and 23.6% for the ACIGS cell. The two-terminal tandem model was simulated by integrating the top and bottom cells, with a transparent contact electrically connecting the subcells in series. The impact of the notch region (minimum bandgap) and Ga composition in single- and double-graded profiles in thin-film ACIGS was examined. The primary goal was to increase <inline-formula> <tex-math>${V} _{text {oc}}$ </tex-math></inline-formula> without losing <inline-formula> <tex-math>${J} _{text {sc}}$ </tex-math></inline-formula> of the tandem device. To achieve this, the Ga content was varied from 0.30 to 0.85 (<inline-formula> <tex-math>${x} _{{1}}$ </tex-math></inline-formula>) for the first layer and from 0.05 to 0.60 (<inline-formula> <tex-math>${x} _{{2}}$ </tex-math></inline-formula>) for the second layer of the ACIGS material for various notch positions. The optimized tandem device achieved an efficiency of 29.14%, with a <inline-formula> <tex-math>${J} _{text {sc}}$ </tex-math></inline-formula> of 18.04 mA/cm2, a <inline-formula> <tex-math>${V} _{text {oc}}$ </tex-math></inline-formula> of 2.037 V, and a fill factor (FF) of 79.25%. This was achieved using a V-shaped Ga content gradient (GGI profile) with <inline-formula> <tex-math>${x} _{{1}} =0.70$ </tex-math></inline-formula>, <inline-formula> <tex-math>${x} _{{2}} =0.40$ </tex-math></inline-formula>, and a notch position of 200 nm for a 2-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m-thick ACIGS layer. These numerical simulations provide insights into the effect of Ga content and bandgap grading on tandem solar cell performance.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1197-1205"},"PeriodicalIF":2.9,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1109/TED.2025.3526129
Seung Hee Kang;Moon Ho Lee;Won Ho Son;Do-Kyung Kim;Jeong Woo Jang;Sung Jin So;Sang Yoon Park;Hyun Jae Kim
This study fabricated double-gate (DG) amorphous indium-gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) and consequently assessed their characteristics in both bottom gate-top gate connection (BTC) and bottom gate-source connection (BSC) modes to improve the performance of active-matrix organic light-emitting diode (AMOLED) displays. The BTC mode exhibited a subthreshold swing (SS) of 84.4 mV/dec, demonstrating superior switching performance, whereas the BSC mode showed a relatively lower characteristic at 199.9 mV/dec. It is well known that low SS is beneficial for TFT switches. However, this article demonstrates that a TFT with low SS is disadvantageous for threshold voltage compensation in pixel circuits. To investigate the effect of the electrical characteristics of DG a-IGZO TFTs on the compensation quality of OLED displays, simulations were conducted via the application of each BG connection mode to the driving TFT (${T}_{text {DR}}$ ) within a circuit comprising four nMOS TFTs and two capacitors. The compensation performance was evaluated based on the variations in ${V}_{text {TH}}$ . In the BTC mode, when the ${V}_{text {TH}}$ variation ($Delta {V}_{text {TH}}$ ) of ${T}_{text {DR}}$ was −0.5 V, the pixel current variation (PCV) was 133.6%. By contrast, in the BSC mode, the PCV was significantly lower 18.6%, demonstrating superior compensation quality.
{"title":"Investigation of Bottom Gate Connection in Double-Gate a-IGZO TFTs for Optimizing Compensation Performance of AMOLED Displays","authors":"Seung Hee Kang;Moon Ho Lee;Won Ho Son;Do-Kyung Kim;Jeong Woo Jang;Sung Jin So;Sang Yoon Park;Hyun Jae Kim","doi":"10.1109/TED.2025.3526129","DOIUrl":"https://doi.org/10.1109/TED.2025.3526129","url":null,"abstract":"This study fabricated double-gate (DG) amorphous indium-gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) and consequently assessed their characteristics in both bottom gate-top gate connection (BTC) and bottom gate-source connection (BSC) modes to improve the performance of active-matrix organic light-emitting diode (AMOLED) displays. The BTC mode exhibited a subthreshold swing (SS) of 84.4 mV/dec, demonstrating superior switching performance, whereas the BSC mode showed a relatively lower characteristic at 199.9 mV/dec. It is well known that low SS is beneficial for TFT switches. However, this article demonstrates that a TFT with low SS is disadvantageous for threshold voltage compensation in pixel circuits. To investigate the effect of the electrical characteristics of DG a-IGZO TFTs on the compensation quality of OLED displays, simulations were conducted via the application of each BG connection mode to the driving TFT (<inline-formula> <tex-math>${T}_{text {DR}}$ </tex-math></inline-formula>) within a circuit comprising four nMOS TFTs and two capacitors. The compensation performance was evaluated based on the variations in <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>. In the BTC mode, when the <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> variation (<inline-formula> <tex-math>$Delta {V}_{text {TH}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>${T}_{text {DR}}$ </tex-math></inline-formula> was −0.5 V, the pixel current variation (PCV) was 133.6%. By contrast, in the BSC mode, the PCV was significantly lower 18.6%, demonstrating superior compensation quality.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1154-1159"},"PeriodicalIF":2.9,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The heteroepitaxy process for growing thin films of single crystal $beta $ -phase gallium oxide ($beta $ -Ga2O3) on c-plane sapphire substrates was conducted using nonvacuum process mist-chemical vapor deposition. The Sn delta ($delta $ )-doping technique was employed to improve the doping concentration, output current, and gate controllability. The use of tetramethylammonium hydroxide (TMAH) to treat the surface of $beta $ -Ga2O3 results in improving the surface morphology, which reduces contact resistance between the source/drain electrode and $beta $ -Ga2O3. Experimental results show that the $beta $ -Ga2O3 MOSFET with Sn $delta $ -doped layer exposed for 80 s and treatment with TMAH for 5 min proposed in this work exhibit excellent electrical properties, including ${V}_{text {TH}}$ of −7.5 V, ${I}_{text {DS},max }$ of 3.71 mA/mm, a subthreshold swing (SS) of 313.26 mV/dec, ${R}_{text {on},text {sp}}$ of $0.6~Omega cdot text {cm}^{{2}}$ , anoff-state breakdown voltage of 1085 V, and a power figure of merit (PFOM) of 1.96 MW/cm2.
{"title":"Heteroepitaxial Growth of Sn δ-Doped β-Ga₂O₃ MOSFETs on c-Plane Sapphire via Nonvacuum Mist-CVD Process","authors":"Hao-Chun Hung;Yin-Chu Hsiao;Ching-Yu Cheng;Chia-Cheng Hsu;Fang-Yu Hsu;Rong-Ming Ko;Han-Yin Liu;Wei-Chou Hsu","doi":"10.1109/TED.2025.3527952","DOIUrl":"https://doi.org/10.1109/TED.2025.3527952","url":null,"abstract":"The heteroepitaxy process for growing thin films of single crystal <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-phase gallium oxide (<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3) on c-plane sapphire substrates was conducted using nonvacuum process mist-chemical vapor deposition. The Sn delta (<inline-formula> <tex-math>$delta $ </tex-math></inline-formula>)-doping technique was employed to improve the doping concentration, output current, and gate controllability. The use of tetramethylammonium hydroxide (TMAH) to treat the surface of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 results in improving the surface morphology, which reduces contact resistance between the source/drain electrode and <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3. Experimental results show that the <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 MOSFET with Sn <inline-formula> <tex-math>$delta $ </tex-math></inline-formula>-doped layer exposed for 80 s and treatment with TMAH for 5 min proposed in this work exhibit excellent electrical properties, including <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> of −7.5 V, <inline-formula> <tex-math>${I}_{text {DS},max }$ </tex-math></inline-formula> of 3.71 mA/mm, a subthreshold swing (SS) of 313.26 mV/dec, <inline-formula> <tex-math>${R}_{text {on},text {sp}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$0.6~Omega cdot text {cm}^{{2}}$ </tex-math></inline-formula>, an<sc>off</small>-state breakdown voltage of 1085 V, and a power figure of merit (PFOM) of 1.96 MW/cm2.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"996-1001"},"PeriodicalIF":2.9,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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