Pub Date : 2025-07-31DOI: 10.1109/TED.2025.3592642
Zhiwei Zheng;Chenyang Huang;Yufeng Jin;Meng Zhang;Yan Yan;Daohua Zhang;Man Hoi Wong;Hoi Sing Kwok;Lei Lu
The interaction between metal and oxide semiconductors (OSs) is critical for advancing OS applications in large-area, flexible, and heterogeneously integrated electronics. Both ohmic and Schottky contacts are essential in these devices. The abundant intrinsic defects in OSs promote ohmic contact formation but adversely affect the Schottky barrier interface, especially in OSs with diverse sub-bandgap states, such as amorphous indium–zinc oxide (a-IZO). This study introduces an ultrathin alumina (Al2O3) interlayer, deposited via plasma-enhanced atomic layer deposition (PEALD), to effectively reduce interface defects and metal-induced gap states (MIGSs) between a-IZO and the platinum (Pt) anode. The top-anode a-IZO Schottky barrier diode (SBD) demonstrates a Schottky barrier height ($Phi _{text {B}}$ ) of 0.73 eV and an ideality factor (n) of 1.35. Such ultrathin Al2O3 engineering effectively enhances the feasibility of high-quality OS Schottky contact.
{"title":"ALD Al2O3-Engineered Schottky Barrier Interface for Amorphous Indium–Zinc Oxide","authors":"Zhiwei Zheng;Chenyang Huang;Yufeng Jin;Meng Zhang;Yan Yan;Daohua Zhang;Man Hoi Wong;Hoi Sing Kwok;Lei Lu","doi":"10.1109/TED.2025.3592642","DOIUrl":"https://doi.org/10.1109/TED.2025.3592642","url":null,"abstract":"The interaction between metal and oxide semiconductors (OSs) is critical for advancing OS applications in large-area, flexible, and heterogeneously integrated electronics. Both ohmic and Schottky contacts are essential in these devices. The abundant intrinsic defects in OSs promote ohmic contact formation but adversely affect the Schottky barrier interface, especially in OSs with diverse sub-bandgap states, such as amorphous indium–zinc oxide (a-IZO). This study introduces an ultrathin alumina (Al2O3) interlayer, deposited via plasma-enhanced atomic layer deposition (PEALD), to effectively reduce interface defects and metal-induced gap states (MIGSs) between a-IZO and the platinum (Pt) anode. The top-anode a-IZO Schottky barrier diode (SBD) demonstrates a Schottky barrier height (<inline-formula> <tex-math>$Phi _{text {B}}$ </tex-math></inline-formula>) of 0.73 eV and an ideality factor (n) of 1.35. Such ultrathin Al2O3 engineering effectively enhances the feasibility of high-quality OS Schottky contact.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5004-5010"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high thermal stability AlGaN-based back-illuminated solar-blind ultraviolet (SBUV) p-i-n photodetectors (PDs) are fabricated on double-sided, polished sapphire substrates. The PD exhibits low dark current of less than 18 pA under –5 V bias at room temperature (RT), which corresponds to a dark current density of $lt 1.8times 10^{-{9}}$ A/cm2. Even at a high temperature of $150~^{circ }$ C, the dark current of the PD is still below 50 pA. The PD also shows a high solar-blind/UV rejection ratio up to four orders of magnitude in the temperature range of RT to $150~^{circ }$ C. As the temperature continuously rises from RT to $150~^{circ }$ C, the photocurrent of the PD only increases by less than 8%, which corresponds to an extremely small temperature coefficient (TC) of <0.06%/°C. The ultralow TC achieved is believed to be related to the high polarization electric field at the composition-graded heterojunction interface.
{"title":"Back-Illuminated AlGaN-Based Solar-Blind Ultraviolet Photodetectors With High-Temperature Photoresponse Stability","authors":"Zixi Lv;Wenkuo Zhang;Jiagui Li;Wei Zeng;Benli Yu;Feng Xie","doi":"10.1109/TED.2025.3592914","DOIUrl":"https://doi.org/10.1109/TED.2025.3592914","url":null,"abstract":"A high thermal stability AlGaN-based back-illuminated solar-blind ultraviolet (SBUV) p-i-n photodetectors (PDs) are fabricated on double-sided, polished sapphire substrates. The PD exhibits low dark current of less than 18 pA under –5 V bias at room temperature (RT), which corresponds to a dark current density of <inline-formula> <tex-math>$lt 1.8times 10^{-{9}}$ </tex-math></inline-formula> A/cm2. Even at a high temperature of <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C, the dark current of the PD is still below 50 pA. The PD also shows a high solar-blind/UV rejection ratio up to four orders of magnitude in the temperature range of RT to <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C. As the temperature continuously rises from RT to <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C, the photocurrent of the PD only increases by less than 8%, which corresponds to an extremely small temperature coefficient (TC) of <0.06%/°C. The ultralow TC achieved is believed to be related to the high polarization electric field at the composition-graded heterojunction interface.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5247-5250"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The 2-D semiconductors, such as molybdenum disulfide (MoS2), have seen extensive use in the fields of electronics and optoelectronics. However, the lower carrier mobility and weak light absorption ability of the ultrathin layered structure greatly limit commercial applications. In this study, we use a single-step UV-ozone oxidation method to transform flat magnesium (Mg) into a rippled substrate, which effectively enhances the carrier mobility of MoS2 from the range of $19.2sim 31.2$ to $45.3sim 78.2$ cm${}^{{2}} cdot $ V${}^{text {-1}} cdot $ s${}^{text {-1}}$ . Owing to the multiple reflections from peak to peak, the device also demonstrates high photoresponsivity of $1.6times 10^{{5}}$ A/W. Interestingly, with appropriate gate bias, the device exhibits constant photoresponsivity of ~220 A/W independent of the incident light intensity. This work presents a simple oxidation-induced rippled Mg substrate, which simultaneously addresses low carrier mobility and weak light absorption in 2-D semiconductors, enabling synergistic electrical-optical improvements, paving the way for the design of high-performance optoelectronic devices.
二维半导体，如二硫化钼（MoS2），已经在电子和光电子领域得到了广泛的应用。然而，超薄层状结构载流子迁移率低，光吸收能力弱，极大地限制了其商业应用。在本研究中，我们使用单步紫外-臭氧氧化方法将平面镁（Mg）转化为脉动衬底，有效地提高了MoS2的载流子迁移率，从$19.2sim 31.2$到$45.3sim 78.2$ cm ${}^{{2}} cdot $ V ${}^{text {-1}}$ s ${}^{text{-1}}$。由于从一个峰到另一个峰的多次反射，该器件也显示出1.6 × 10^{{5}}$ A/W的高光响应性。有趣的是，在适当的栅极偏置下，该器件具有恒定的~220 A/W的光响应性，与入射光强度无关。这项工作提出了一种简单的氧化诱导波纹Mg衬底，同时解决了二维半导体中的低载流子迁移率和弱光吸收问题，实现了电光协同改进，为高性能光电器件的设计铺平了道路。
{"title":"High-Mobility and High-Responsivity MoS2 Phototransistor Enabled by Rippled Mg Substrate Engineering","authors":"Qianlei Tian;Changsheng You;Long Yue;Yang Xiao;Renfei Chen;Jin Yang;Xinpei Duan;Liming Wang;Ruohao Hong;Yuan Zhou","doi":"10.1109/TED.2025.3592175","DOIUrl":"https://doi.org/10.1109/TED.2025.3592175","url":null,"abstract":"The 2-D semiconductors, such as molybdenum disulfide (MoS2), have seen extensive use in the fields of electronics and optoelectronics. However, the lower carrier mobility and weak light absorption ability of the ultrathin layered structure greatly limit commercial applications. In this study, we use a single-step UV-ozone oxidation method to transform flat magnesium (Mg) into a rippled substrate, which effectively enhances the carrier mobility of MoS2 from the range of <inline-formula> <tex-math>$19.2sim 31.2$ </tex-math></inline-formula> to <inline-formula> <tex-math>$45.3sim 78.2$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{{2}} cdot $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}^{text {-1}} cdot $ </tex-math></inline-formula>s<inline-formula> <tex-math>${}^{text {-1}}$ </tex-math></inline-formula>. Owing to the multiple reflections from peak to peak, the device also demonstrates high photoresponsivity of <inline-formula> <tex-math>$1.6times 10^{{5}}$ </tex-math></inline-formula> A/W. Interestingly, with appropriate gate bias, the device exhibits constant photoresponsivity of ~220 A/W independent of the incident light intensity. This work presents a simple oxidation-induced rippled Mg substrate, which simultaneously addresses low carrier mobility and weak light absorption in 2-D semiconductors, enabling synergistic electrical-optical improvements, paving the way for the design of high-performance optoelectronic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5255-5258"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TED.2025.3592887
Yufei Sheng;Yonglin Xia;Jiaxuan Xu;Shuying Wang;Pengpeng Ren;Zhigang Ji;Hua Bao
For next-generation advanced logic devices, gate-all-around field-effect transistors (GAAFETs) with characteristic size reaching the 10 nm scale, necessitate thorough consideration of nanoscale thermal transport to assess the impact of self-heating on device performance and reliability. However, previous studies predominantly relied on simplified or fitting models to directly adjust the effective thermal conductivities of various device components within the heat diffusion equation (HDE) or thermal resistance networks. These methods are inadequate for fully capturing nanoscale thermal transport. Here, we perform multiscale thermal simulations of GAAFETs by integrating first-principles-based nongray Boltzmann transport equation (BTE) with the HDE. By comparing the temperature distributions calculated using the gray BTE and HDE, we demonstrate the necessity of employing the nongray phonon BTE for accurate simulation of the active region. We further discover that the size-dependent thermal conductivity of metal regions should be incorporated using the electron–phonon BTE. Moreover, based on comprehensive thermal simulations of a stacked nanosheet GAAFET, we identify that the amorphous passive layer, interfacial thermal resistance between different layers, along with the thermal resistance of the STI/BDI layers and interconnections, are key factors limiting heat dissipation. Our approach fully incorporates nanoscale thermal transport while eliminating reliance on empirical parameters and facilitates multiscale simulations from materials to structures to devices, with potential applicability to circuit-level simulations.
{"title":"Multiscale Thermal Simulation for GAAFET With First-Principles-Based Boltzmann Transport Equation","authors":"Yufei Sheng;Yonglin Xia;Jiaxuan Xu;Shuying Wang;Pengpeng Ren;Zhigang Ji;Hua Bao","doi":"10.1109/TED.2025.3592887","DOIUrl":"https://doi.org/10.1109/TED.2025.3592887","url":null,"abstract":"For next-generation advanced logic devices, gate-all-around field-effect transistors (GAAFETs) with characteristic size reaching the 10 nm scale, necessitate thorough consideration of nanoscale thermal transport to assess the impact of self-heating on device performance and reliability. However, previous studies predominantly relied on simplified or fitting models to directly adjust the effective thermal conductivities of various device components within the heat diffusion equation (HDE) or thermal resistance networks. These methods are inadequate for fully capturing nanoscale thermal transport. Here, we perform multiscale thermal simulations of GAAFETs by integrating first-principles-based nongray Boltzmann transport equation (BTE) with the HDE. By comparing the temperature distributions calculated using the gray BTE and HDE, we demonstrate the necessity of employing the nongray phonon BTE for accurate simulation of the active region. We further discover that the size-dependent thermal conductivity of metal regions should be incorporated using the electron–phonon BTE. Moreover, based on comprehensive thermal simulations of a stacked nanosheet GAAFET, we identify that the amorphous passive layer, interfacial thermal resistance between different layers, along with the thermal resistance of the STI/BDI layers and interconnections, are key factors limiting heat dissipation. Our approach fully incorporates nanoscale thermal transport while eliminating reliance on empirical parameters and facilitates multiscale simulations from materials to structures to devices, with potential applicability to circuit-level simulations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4700-4707"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TED.2025.3591390
Soyoung Choi;Jaewook Jeong
The channel potential distribution of the dual-gate a-IGZO thin-film transistors (TFTs) was analyzed in the active layer using a gated-multiprobe method (GMP method) combining theory of quantum mechanics for the analysis of TFTs having very thin active layer. From the GMP method, the channel potential distribution follows the conventional gradual channel approximation rule from the source to the drain electrodes in case of linear region operation. In the saturation region, pinch-off with the formation of a space-charge-limited region was observed. To compare the result with the theory of quantum mechanics, ATLAS from Silvaco Inc. (ATLAS) device simulation was performed using both classical and quantum mechanical approach. The resulting parasitic resistance values of the dual-gate biasing (DGB) mode differed from the classical approach, owing to the same current spreading path of the top- and bottom-gate channel electrons, when the quantum mechanical density gradient method was applied. The accuracy of the quantum theory was confirmed using the prolonged stress results, which indicated defect creation near the middle of the channel region was the dominant mechanism for the bias stress instability, considering quantum mechanical channel electron distribution.
{"title":"Quantum Mechanical Analysis of Dual-Gate InGaZnO TFTs Employing a Gated-Multiprobe","authors":"Soyoung Choi;Jaewook Jeong","doi":"10.1109/TED.2025.3591390","DOIUrl":"https://doi.org/10.1109/TED.2025.3591390","url":null,"abstract":"The channel potential distribution of the dual-gate a-IGZO thin-film transistors (TFTs) was analyzed in the active layer using a gated-multiprobe method (GMP method) combining theory of quantum mechanics for the analysis of TFTs having very thin active layer. From the GMP method, the channel potential distribution follows the conventional gradual channel approximation rule from the source to the drain electrodes in case of linear region operation. In the saturation region, pinch-off with the formation of a space-charge-limited region was observed. To compare the result with the theory of quantum mechanics, ATLAS from Silvaco Inc. (ATLAS) device simulation was performed using both classical and quantum mechanical approach. The resulting parasitic resistance values of the dual-gate biasing (DGB) mode differed from the classical approach, owing to the same current spreading path of the top- and bottom-gate channel electrons, when the quantum mechanical density gradient method was applied. The accuracy of the quantum theory was confirmed using the prolonged stress results, which indicated defect creation near the middle of the channel region was the dominant mechanism for the bias stress instability, considering quantum mechanical channel electron distribution.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4983-4990"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TED.2025.3592912
Seongjae Heo;Sunhyeong Lee;Hyunsang Hwang
As the demand for low-power electronic devices in the Internet of Things (IoT) and embedded systems continues to grow, there is an increasing need for new devices that can operate at low voltages with minimal leakage current while maintaining fast switching speeds. To address this challenge, we developed a two-terminal threshold switching (TS) device based on Ag2S, demonstrating both low leakage current and fast switching speed at low voltages. The Ag2S-based TS devices were integrated in series with MOSFETs to form a 1T-1S array, designed for steep-slope FET applications. The Ag2S-based TS device exhibited a low leakage current of 2 pA, and when integrated with the MOSFET, the combined FET demonstrated a subthreshold swing (SS) of 3 mV/dec. Remarkably, the device exhibited a fast switching speed of 1 ns at 2.0 V. In addition, as the Ag2S composition approached stoichiometry, both leakage current and threshold voltage decreased, alleviating the voltage–time dilemma typically encountered in filamentary switching devices. These enhanced properties are attributed to the local phase transition of Ag2S and superionic conductivity of $beta $ -Ag2S, which facilitate rapid ion transport and filament formation under an electric field. Furthermore, at a compliance current of $30~mu $ A, the device demonstrated a turn-off speed of tens of nanoseconds. By increasing the compliance current to several hundred microamperes, the device also exhibited a short-term retention of several minutes, showing potential for application in next-generation DRAM-like volatile memory.
{"title":"Low-Power and High-Speed Ag2S-Based Threshold Switching Device Enabled by Local Phase Transition-Assisted Filamentary Switching","authors":"Seongjae Heo;Sunhyeong Lee;Hyunsang Hwang","doi":"10.1109/TED.2025.3592912","DOIUrl":"https://doi.org/10.1109/TED.2025.3592912","url":null,"abstract":"As the demand for low-power electronic devices in the Internet of Things (IoT) and embedded systems continues to grow, there is an increasing need for new devices that can operate at low voltages with minimal leakage current while maintaining fast switching speeds. To address this challenge, we developed a two-terminal threshold switching (TS) device based on Ag2S, demonstrating both low leakage current and fast switching speed at low voltages. The Ag2S-based TS devices were integrated in series with MOSFETs to form a 1T-1S array, designed for steep-slope FET applications. The Ag2S-based TS device exhibited a low leakage current of 2 pA, and when integrated with the MOSFET, the combined FET demonstrated a subthreshold swing (SS) of 3 mV/dec. Remarkably, the device exhibited a fast switching speed of 1 ns at 2.0 V. In addition, as the Ag2S composition approached stoichiometry, both leakage current and threshold voltage decreased, alleviating the voltage–time dilemma typically encountered in filamentary switching devices. These enhanced properties are attributed to the local phase transition of Ag2S and superionic conductivity of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ag2S, which facilitate rapid ion transport and filament formation under an electric field. Furthermore, at a compliance current of <inline-formula> <tex-math>$30~mu $ </tex-math></inline-formula>A, the device demonstrated a turn-off speed of tens of nanoseconds. By increasing the compliance current to several hundred microamperes, the device also exhibited a short-term retention of several minutes, showing potential for application in next-generation DRAM-like volatile memory.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4916-4921"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Silicon carbide (SiC) MOSFETs are widely favored for their excellent performance. However, reliability concerns have hindered their rapid development, with threshold voltage drift being one of the key concerns. Although threshold voltage drift under static and dynamic gate stress has been widely investigated, limited attention has been paid to the threshold voltage drift induced by drain stress. In this work, a dedicated test platform for SiC MOSFETs was developed, enabling independent and decoupled application of gate and drain stresses. Moreover, the drain stress can be further decomposed into voltage and current components for more detailed analysis. In addition, TCAD simulations were used to investigate the mechanisms underlying the different threshold voltage drifts induced by various stress modes. It was found that drain stress has a noticeable effect on threshold voltage drift, which cannot be neglected. Moreover, there is a coupling effect between drain and gate stresses. These findings aim to provide better management and coping strategies for threshold voltage drift in power electronic device applications.
{"title":"Dynamic Threshold Voltage Drift of Silicon Carbide MOSFET With Drain Stress","authors":"Huapping Jiang;Yao Li;Xinxin Li;Mengya Qiu;Nianlei Xiao;Lei Tang;Xiaohan Zhong;Ruijin Liao","doi":"10.1109/TED.2025.3592639","DOIUrl":"https://doi.org/10.1109/TED.2025.3592639","url":null,"abstract":"Silicon carbide (SiC) MOSFETs are widely favored for their excellent performance. However, reliability concerns have hindered their rapid development, with threshold voltage drift being one of the key concerns. Although threshold voltage drift under static and dynamic gate stress has been widely investigated, limited attention has been paid to the threshold voltage drift induced by drain stress. In this work, a dedicated test platform for SiC MOSFETs was developed, enabling independent and decoupled application of gate and drain stresses. Moreover, the drain stress can be further decomposed into voltage and current components for more detailed analysis. In addition, TCAD simulations were used to investigate the mechanisms underlying the different threshold voltage drifts induced by various stress modes. It was found that drain stress has a noticeable effect on threshold voltage drift, which cannot be neglected. Moreover, there is a coupling effect between drain and gate stresses. These findings aim to provide better management and coping strategies for threshold voltage drift in power electronic device applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4802-4809"},"PeriodicalIF":3.2,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Molybdenum disulfide (MoS2), is a novel 2-D material, has recently garnered significant attention. In this study, MoS2 nanosheets (NSs) were synthesized via a liquid-phase exfoliation (LPE) method, and subsequently used to modify the titanium dioxide (TiO2) photoanode of dye-sensitized solar cells (DSSCs). The incorporation of MoS2 NSs not only enhances dye adsorption due to their high specific surface area but also reduces the carrier recombination rate attributed to their excellent carrier mobility. These combined effects contribute to an improvement in the photovoltaic conversion efficiency (PCE) of DSSCs. Notably, the efficiency of DSSCs with MoS2 modification increased from 4.99% to 6.55%, representing a 31% improvement.
{"title":"Enhanced Dye-Sensitized Solar Cells via MoS2 Nanosheets-Modified TiO2 Photoanodes","authors":"Chih-Hsien Lai;Wen-Hao Chen;Jung-Chuan Chou;Chun-Yu Li;Po-Hui Yang;Po-Yu Kuo;Yu-Hsun Nien;Jhih-Wei Zeng","doi":"10.1109/TED.2025.3592167","DOIUrl":"https://doi.org/10.1109/TED.2025.3592167","url":null,"abstract":"Molybdenum disulfide (MoS2), is a novel 2-D material, has recently garnered significant attention. In this study, MoS2 nanosheets (NSs) were synthesized via a liquid-phase exfoliation (LPE) method, and subsequently used to modify the titanium dioxide (TiO2) photoanode of dye-sensitized solar cells (DSSCs). The incorporation of MoS2 NSs not only enhances dye adsorption due to their high specific surface area but also reduces the carrier recombination rate attributed to their excellent carrier mobility. These combined effects contribute to an improvement in the photovoltaic conversion efficiency (PCE) of DSSCs. Notably, the efficiency of DSSCs with MoS2 modification increased from 4.99% to 6.55%, representing a 31% improvement.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5045-5053"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-30DOI: 10.1109/TED.2025.3592165
Lei Cao;Guanqiao Sang;Qingzhu Zhang;Jiaxin Yao;Xiaohui Zhu;Qingkun Li;Junjie Li;Jianfeng Gao;Tingting Li;Yihong Lu;Xiaobin He;Zhenhua Wu;Yongliang Li;Junfeng Li;Huaxiang Yin;Jun Luo
In this article, to optimize the performance of silicon-on-insulator (SOI) stacked Si nanosheet (NS) gate-all-around field-effect transistor (GAAFET) with long source/drain (S/D) regions, special process techniques of Ni(Pt)Si silicide-first and Load-Si thinning are successfully integrated in the experimental devices. Because of the introduced silicide-first process, the transistor performance merits of on-current (${I}_{mathrm {ON}}$ ) and transconductance (${G}_{text {m}}$ ) are also increased by 34.19% and 80.55% for the reduction of 68.66% in the S/D parasitic resistance. Meanwhile, compared to the Bulk-Si GAAFET, the gate-induced drain leakage (GIDL) current of the SOI GAAFET is also decreased by more than one order of magnitude. However, the subthreshold characteristics of SOI GAAFETs exhibit a rapid degradation as the gate length (${L}_{text {g}}$ ) scaling, which is mainly due to the effect of parasitic channel in the remaining Load-Si layer. To optimize the leakage and subthreshold characteristics, the electrical impacts of Load-Si thickness (${T}_{text {Load-Si}}$ ) are thoroughly investigated by the experiment and TCAD simulation. The experimental SOI GAAFET fabricated by thinning Load-Si to 19 nm has obtained better subthreshold characteristics, improved normalized ${I}_{mathrm {ON}}$ , and caused an obvious decrease of off-current (${I}_{mathrm {OFF}}$ ) at ${L}_{text {g}} = {30}$ nm. Meanwhile, the simulation results further show that the SOI GAAFET with shorter ${L}_{text {g}}$ needs to continuously decrease ${T}_{text {Load-Si}}$ to meet the requirements of a fully depleted channel and low ${I}_{mathrm {OFF}}$ .
{"title":"Optimized SOI Stacked Si Nanosheet Gate-All-Around FET With Ni(Pt)Si Silicide-First and Load-Si Thinning Techniques","authors":"Lei Cao;Guanqiao Sang;Qingzhu Zhang;Jiaxin Yao;Xiaohui Zhu;Qingkun Li;Junjie Li;Jianfeng Gao;Tingting Li;Yihong Lu;Xiaobin He;Zhenhua Wu;Yongliang Li;Junfeng Li;Huaxiang Yin;Jun Luo","doi":"10.1109/TED.2025.3592165","DOIUrl":"https://doi.org/10.1109/TED.2025.3592165","url":null,"abstract":"In this article, to optimize the performance of silicon-on-insulator (SOI) stacked Si nanosheet (NS) gate-all-around field-effect transistor (GAAFET) with long source/drain (S/D) regions, special process techniques of Ni(Pt)Si silicide-first and Load-Si thinning are successfully integrated in the experimental devices. Because of the introduced silicide-first process, the transistor performance merits of <sc>on</small>-current (<inline-formula> <tex-math>${I}_{mathrm {ON}}$ </tex-math></inline-formula>) and transconductance (<inline-formula> <tex-math>${G}_{text {m}}$ </tex-math></inline-formula>) are also increased by 34.19% and 80.55% for the reduction of 68.66% in the S/D parasitic resistance. Meanwhile, compared to the Bulk-Si GAAFET, the gate-induced drain leakage (GIDL) current of the SOI GAAFET is also decreased by more than one order of magnitude. However, the subthreshold characteristics of SOI GAAFETs exhibit a rapid degradation as the gate length (<inline-formula> <tex-math>${L}_{text {g}}$ </tex-math></inline-formula>) scaling, which is mainly due to the effect of parasitic channel in the remaining Load-Si layer. To optimize the leakage and subthreshold characteristics, the electrical impacts of Load-Si thickness (<inline-formula> <tex-math>${T}_{text {Load-Si}}$ </tex-math></inline-formula>) are thoroughly investigated by the experiment and TCAD simulation. The experimental SOI GAAFET fabricated by thinning Load-Si to 19 nm has obtained better subthreshold characteristics, improved normalized <inline-formula> <tex-math>${I}_{mathrm {ON}}$ </tex-math></inline-formula>, and caused an obvious decrease of <sc>off</small>-current (<inline-formula> <tex-math>${I}_{mathrm {OFF}}$ </tex-math></inline-formula>) at <inline-formula> <tex-math>${L}_{text {g}} = {30}$ </tex-math></inline-formula> nm. Meanwhile, the simulation results further show that the SOI GAAFET with shorter <inline-formula> <tex-math>${L}_{text {g}}$ </tex-math></inline-formula> needs to continuously decrease <inline-formula> <tex-math>${T}_{text {Load-Si}}$ </tex-math></inline-formula> to meet the requirements of a fully depleted channel and low <inline-formula> <tex-math>${I}_{mathrm {OFF}}$ </tex-math></inline-formula>.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4685-4690"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, electrolyte synaptic transistors have become a popular choice for neuromorphic computing hardware due to their low power consumption, high linearity, and dynamic conductance modulation capabilities. However, the lack of precise circuit models of electrolyte synaptic transistors limits the convenience of exploring electrolyte transistors-based circuits or systems. In this study, we propose a universal model for electrolyte synaptic transistors by decoupling ionic and electronic transport process. The model is highly flexible and adaptable to various electrolyte synaptic transistor devices, allowing for easy modulation of synaptic characteristics through parameter adjustments. Inspired by the adaptive capabilities of biological sensory systems, we constructed a simplified circuit based on the proposed model and validated it through LTSPICE simulations. The results demonstrate that the model accurately captures the pulse modulation capabilities of electrolyte synaptic transistors and effectively simulates the response characteristics of biological sensory neurons. The proposed electrolyte synaptic transistor model would facilitate the convenience of exploring electrolyte transistors-based circuits or systems.
{"title":"A SPICE Model of Electrolyte Synaptic Transistors","authors":"Zuheng Wu;Yang Hao;Hao Ruan;Haochen Wang;Zhihao Lin;Jianxun Zou;Zhe Feng;Wenbin Guo;Yunlai Zhu;Zuyu Xu;Yuehua Dai","doi":"10.1109/TED.2025.3591092","DOIUrl":"https://doi.org/10.1109/TED.2025.3591092","url":null,"abstract":"In recent years, electrolyte synaptic transistors have become a popular choice for neuromorphic computing hardware due to their low power consumption, high linearity, and dynamic conductance modulation capabilities. However, the lack of precise circuit models of electrolyte synaptic transistors limits the convenience of exploring electrolyte transistors-based circuits or systems. In this study, we propose a universal model for electrolyte synaptic transistors by decoupling ionic and electronic transport process. The model is highly flexible and adaptable to various electrolyte synaptic transistor devices, allowing for easy modulation of synaptic characteristics through parameter adjustments. Inspired by the adaptive capabilities of biological sensory systems, we constructed a simplified circuit based on the proposed model and validated it through LTSPICE simulations. The results demonstrate that the model accurately captures the pulse modulation capabilities of electrolyte synaptic transistors and effectively simulates the response characteristics of biological sensory neurons. The proposed electrolyte synaptic transistor model would facilitate the convenience of exploring electrolyte transistors-based circuits or systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4902-4909"},"PeriodicalIF":3.2,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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