Pub Date : 2024-11-21DOI: 10.1109/TED.2024.3499940
Nobuyuki Sano
A new theoretical framework for the nonequilibrium Green’s function (NEGF) scheme is presented to account for the discrete nature of impurities doped in semiconductors. Since the impurity potential is singular, the short-range screened impurity potential is included as the self-energy due to spatially localized impurity scattering. The long-range part of the impurity potential is treated as the self-consistent Hartree potential. The present framework is applied to cylindrical wires under the quasi-one-dimensional (quasi-1D) approximation. We show explicitly how the discrete nature of impurities affects transport properties such as electrostatic potential, local density of states (LDOSs), carrier density, and scattering rates. Furthermore, we demonstrate that the present scheme allows for the quantitative analysis of variabilities in transport characteristics of nanoscale thin wires.
{"title":"Fundamental Aspects of Semiconductor Device Modeling Associated With Discrete Impurities: Nonequilibrium Green’s Function Scheme","authors":"Nobuyuki Sano","doi":"10.1109/TED.2024.3499940","DOIUrl":"https://doi.org/10.1109/TED.2024.3499940","url":null,"abstract":"A new theoretical framework for the nonequilibrium Green’s function (NEGF) scheme is presented to account for the discrete nature of impurities doped in semiconductors. Since the impurity potential is singular, the short-range screened impurity potential is included as the self-energy due to spatially localized impurity scattering. The long-range part of the impurity potential is treated as the self-consistent Hartree potential. The present framework is applied to cylindrical wires under the quasi-one-dimensional (quasi-1D) approximation. We show explicitly how the discrete nature of impurities affects transport properties such as electrostatic potential, local density of states (LDOSs), carrier density, and scattering rates. Furthermore, we demonstrate that the present scheme allows for the quantitative analysis of variabilities in transport characteristics of nanoscale thin wires.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"24-30"},"PeriodicalIF":2.9,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-20DOI: 10.1109/TED.2024.3488676
Liang Tian;Yizhang Liu;Wenchao Chen
Hybrid bonding plays an important role in advanced 2.5-D/3-D chiplet integration due to its distinctive advantages, such as higher interconnect density, lower power consumption, and better signal integrity. However, the dc/ac performance of the logic device in chiplet can be affected by the strain induced by the annealing and cooling steps of hybrid bonding. In this article, a coupled multiphysics simulation is performed to investigate the impact of the hybrid bonding process on the performance of p-type FinFET by introducing stress from the hybrid bonding process into quantum transport simulation for FinFET based on nonequilibrium Green’s function (NEGF) formalism, in which the impact of hybrid bonding process-induced stress on the band structure of the device is captured by employing six-band ${k} cdot {p}$ Hamiltonian and deformation potential theory. The simulation results indicate that the on-state current and the hole density in the channel can be enhanced due to the variation of the density of states (DOSs) caused by hybrid bonding process-induced stress, the effect of process-induced stress on Y parameters and gate capacitance in the frequency domain is also explored. Devices near the center of copper pillars are more affected than those far away from the copper pillars. Decreasing the radius of copper pillars and annealing temperature or increasing the distance between copper pillars can decrease the hybrid bonding process-induced stress in FinFET, hence decreasing the change in device performance, including on -state current, Y parameters, and gate capacitance.
混合键合以其更高的互连密度、更低的功耗和更好的信号完整性等独特优势，在先进的2.5 d /3-D芯片集成中发挥着重要作用。然而，杂化键合的退火和冷却过程中产生的应变会影响芯片中逻辑器件的直流/交流性能。本文基于非平衡格林函数（NEGF）形式，将杂化键合过程中的应力引入到FinFET的量子输运模拟中，进行了耦合多物理场模拟，研究了杂化键合过程对p型FinFET性能的影响。其中，利用六波段${k} cdot {p}$哈密顿量和变形势理论，捕捉了杂化键合过程引起的应力对器件能带结构的影响。仿真结果表明，杂化键合过程诱导应力引起的态密度（DOSs）变化可以提高通道内的导通电流和空穴密度，并探讨了过程诱导应力对Y参数和栅极电容频域的影响。靠近铜柱中心的设备比远离铜柱的设备受影响更大。减小铜柱半径和退火温度或增大铜柱之间的距离可以减小FinFET中杂化键合过程引起的应力，从而减小器件性能的变化，包括导通电流、Y参数和栅极电容。
{"title":"Multiphysics Simulation of Chiplet Integration Process-Induced Stress Effects on AC and DC Quantum Transport of FinFET From System Technology Co-Optimization Perspective","authors":"Liang Tian;Yizhang Liu;Wenchao Chen","doi":"10.1109/TED.2024.3488676","DOIUrl":"https://doi.org/10.1109/TED.2024.3488676","url":null,"abstract":"Hybrid bonding plays an important role in advanced 2.5-D/3-D chiplet integration due to its distinctive advantages, such as higher interconnect density, lower power consumption, and better signal integrity. However, the dc/ac performance of the logic device in chiplet can be affected by the strain induced by the annealing and cooling steps of hybrid bonding. In this article, a coupled multiphysics simulation is performed to investigate the impact of the hybrid bonding process on the performance of p-type FinFET by introducing stress from the hybrid bonding process into quantum transport simulation for FinFET based on nonequilibrium Green’s function (NEGF) formalism, in which the impact of hybrid bonding process-induced stress on the band structure of the device is captured by employing six-band \u0000<inline-formula> <tex-math>${k} cdot {p}$ </tex-math></inline-formula>\u0000 Hamiltonian and deformation potential theory. The simulation results indicate that the on-state current and the hole density in the channel can be enhanced due to the variation of the density of states (DOSs) caused by hybrid bonding process-induced stress, the effect of process-induced stress on Y parameters and gate capacitance in the frequency domain is also explored. Devices near the center of copper pillars are more affected than those far away from the copper pillars. Decreasing the radius of copper pillars and annealing temperature or increasing the distance between copper pillars can decrease the hybrid bonding process-induced stress in FinFET, hence decreasing the change in device performance, including \u0000<sc>on</small>\u0000-state current, Y parameters, and gate capacitance.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 12","pages":"7294-7301"},"PeriodicalIF":2.9,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We report on fully vertical gallium nitride (GaN)-on-silicon (Si) p-i-n diodes delivering above 1200-V soft breakdown voltage (BV). Temperature dependence measurements indicate avalanche breakdown capability reflecting the high-quality processing and epitaxy growth. The ON-state characteristics of the fabricated vertical p-i-n diodes reveal on-resistances ranging from 0.48 m $Omega cdot $ cm2 for small anode to 1.7 m $Omega cdot $ cm2 for large anode diameters (i.e., 1 mm). The ON-state resistance increase is attributed to the thermal dissipation issues. Nevertheless, the large devices exhibit high ON-state current close to 12 A owing to an optimized process, including a deep mesa etch as edge terminations and thick Cu layer for heat sink on the backside enabled by a polyimide passivation that strengthen the mechanical robustness of the membranes. To the best of our knowledge, this represents the first demonstration of fully vertical 1200-V GaN-based devices grown on Si substrates with high-current operation above 10 A, corresponding to a Baliga figure of merit (BFOM) of 3 GW/cm2.
我们报道了完全垂直的氮化镓(GaN)-硅（Si） p-i-n二极管提供超过1200 v的软击穿电压（BV）。温度依赖性测量表明雪崩击穿能力反映了高质量的加工和外延生长。制造的垂直p-i-n二极管的导通状态特性显示，小阳极的导通电阻为0.48 m $Omega cdot $ cm2，大阳极直径（即1 mm）的导通电阻为1.7 m $Omega cdot $ cm2。导通状态电阻的增加是由于散热问题。尽管如此，由于优化的工艺，大型器件表现出接近12 A的高导通状态电流，包括边缘终端的深台面蚀刻和背面热沉的厚Cu层，通过聚酰亚胺钝化来增强膜的机械坚固性。据我们所知，这代表了在硅衬底上生长的完全垂直的1200 v gan基器件的首次演示，其工作电流高于10 A，对应于3 GW/cm2的Baliga优值（bom）。
{"title":"1200-V Fully Vertical GaN-on-Silicon p-i-n Diodes With Avalanche Capability and High On-State Current Above 10 A","authors":"Youssef Hamdaoui;Sondre Michler;Adrien Bidaud;Katir Ziouche;Farid Medjdoub","doi":"10.1109/TED.2024.3496440","DOIUrl":"https://doi.org/10.1109/TED.2024.3496440","url":null,"abstract":"We report on fully vertical gallium nitride (GaN)-on-silicon (Si) p-i-n diodes delivering above 1200-V soft breakdown voltage (BV). Temperature dependence measurements indicate avalanche breakdown capability reflecting the high-quality processing and epitaxy growth. The ON-state characteristics of the fabricated vertical p-i-n diodes reveal on-resistances ranging from 0.48 m\u0000<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>\u0000cm2 for small anode to 1.7 m\u0000<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>\u0000cm2 for large anode diameters (i.e., 1 mm). The ON-state resistance increase is attributed to the thermal dissipation issues. Nevertheless, the large devices exhibit high ON-state current close to 12 A owing to an optimized process, including a deep mesa etch as edge terminations and thick Cu layer for heat sink on the backside enabled by a polyimide passivation that strengthen the mechanical robustness of the membranes. To the best of our knowledge, this represents the first demonstration of fully vertical 1200-V GaN-based devices grown on Si substrates with high-current operation above 10 A, corresponding to a Baliga figure of merit (BFOM) of 3 GW/cm2.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"338-343"},"PeriodicalIF":2.9,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-19DOI: 10.1109/TED.2024.3494753
Alex G. Sinelli;Lorin I. Breen;N. R. Sree Harsha;Adam M. Darr;Allison M. Komrska;Allen L. Garner
Theoretically and computationally describing the operation of nanodiodes requires characterizing the transitions between multiple electron emission mechanisms for nanodiodes with complicated geometries. This motivates our development of techniques to determine when simplified theories for individual mechanisms suffice compared to more complete, but more computationally expensive, models. Leveraging recent theories that define a canonical gap distance to translate planar theory to nonplanar diodes, we derive the conditions for the transitions among thermal emission, field emission, and space-charge-limited current density (SCLCD) in vacuum and with collisions for non-Cartesian coordinate systems, including spherical, cylindrical, and prolate spheroidal coordinate systems. Particle-in-cell (PIC) simulations of the current density as a function of applied voltage for a tip-to-plate geometry in vacuum agreed qualitatively with the asymptotes for thermal emission at low voltage and SCLCD at higher voltage using the canonical gap distance. This demonstrates the utility of this approach for guiding system design and suggests future extensions to save simulation time for more realistic geometries that are more computationally expensive.
{"title":"Theoretical Assessment of the Transition Between Electron Emission Mechanisms for Nonplanar Diodes","authors":"Alex G. Sinelli;Lorin I. Breen;N. R. Sree Harsha;Adam M. Darr;Allison M. Komrska;Allen L. Garner","doi":"10.1109/TED.2024.3494753","DOIUrl":"https://doi.org/10.1109/TED.2024.3494753","url":null,"abstract":"Theoretically and computationally describing the operation of nanodiodes requires characterizing the transitions between multiple electron emission mechanisms for nanodiodes with complicated geometries. This motivates our development of techniques to determine when simplified theories for individual mechanisms suffice compared to more complete, but more computationally expensive, models. Leveraging recent theories that define a canonical gap distance to translate planar theory to nonplanar diodes, we derive the conditions for the transitions among thermal emission, field emission, and space-charge-limited current density (SCLCD) in vacuum and with collisions for non-Cartesian coordinate systems, including spherical, cylindrical, and prolate spheroidal coordinate systems. Particle-in-cell (PIC) simulations of the current density as a function of applied voltage for a tip-to-plate geometry in vacuum agreed qualitatively with the asymptotes for thermal emission at low voltage and SCLCD at higher voltage using the canonical gap distance. This demonstrates the utility of this approach for guiding system design and suggests future extensions to save simulation time for more realistic geometries that are more computationally expensive.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"397-403"},"PeriodicalIF":2.9,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Defects at the interfaces in the Josephson junction (JJ) are well known as a primary source of decoherence in superconducting quantum devices, indicating the necessity of elucidating defect reaction mechanisms to improve qubit performance. However, their micromechanism remains elusive. Here, we reveal the micromechanism of defects affecting the transport properties by building interfacial defective JJ device models combined with density functional theory (DFT) and nonequilibrium Green’s function (NEGF) approach. By comparing the conductance values of various interface classification models with oxygen vacancies (OVs), we find that the aluminum-rich (Al-rich) interface exhibits the smallest conductance variation, resulting in less qubit frequency fluctuations, and this can be further explained by changes in the electrostatic potential relative to the average barrier height. More importantly, the Al-rich interface demonstrates the highest stability. This work provides a theoretical basis and optimization direction for superconducting quantum chip fabrication.
{"title":"Impact of Interfacial Atomic Ratios on Stabilized Transport Properties in Defective Josephson Junctions","authors":"Junling Qiu;Shuya Wang;Huihui Sun;Chuanbing Han;Yonglong Shen;Yibin Hu;Bo Zhao;Zheng Shan","doi":"10.1109/TED.2024.3496433","DOIUrl":"https://doi.org/10.1109/TED.2024.3496433","url":null,"abstract":"Defects at the interfaces in the Josephson junction (JJ) are well known as a primary source of decoherence in superconducting quantum devices, indicating the necessity of elucidating defect reaction mechanisms to improve qubit performance. However, their micromechanism remains elusive. Here, we reveal the micromechanism of defects affecting the transport properties by building interfacial defective JJ device models combined with density functional theory (DFT) and nonequilibrium Green’s function (NEGF) approach. By comparing the conductance values of various interface classification models with oxygen vacancies (OVs), we find that the aluminum-rich (Al-rich) interface exhibits the smallest conductance variation, resulting in less qubit frequency fluctuations, and this can be further explained by changes in the electrostatic potential relative to the average barrier height. More importantly, the Al-rich interface demonstrates the highest stability. This work provides a theoretical basis and optimization direction for superconducting quantum chip fabrication.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"488-493"},"PeriodicalIF":2.9,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-19DOI: 10.1109/TED.2024.3496668
Jinsu Jeong;Sanguk Lee;Rock-Hyun Baek
This article presents a thorough investigation of the optimization of asymmetries in vertical-transport nanosheet field-effect transistors (VFETs), considering both asymmetric source/drain (S/D) structures and channel tapering. For asymmetric S/D configurations, n-type FETs (nFETs) exhibit smaller RC delay in the top-source (TopS) configuration, wherein the source has a shorter current path and less voltage drop. Conversely, p-type FETs (pFETs) exhibit smaller RC delay in the bottom-source (BotS) configuration owing to the dominant effect of asymmetric channel stress over the current path difference. Meanwhile, channel tapering significantly affects the optimization of asymmetric VFETs, especially for nFETs. Considering channel tapering, nFET with the smallest RC delay is the BotS configuration, in contrast to the untapered case, whereas BotS configuration is still the optimal structure for pFETs, regardless of the channel tapering. Finally, optimal structures of asymmetric VFETs are presented for various channel widths based on a comparison of the power-delay product (PDP). In nFETs, BotS configuration is optimal for wide channel widths; however, the TopS becomes superior as the channel width decreases in terms of PDP. Meanwhile, optimal structures for pFETs are BotS configurations regardless of the channel tapering and width. For various system-on-chip (SoC) applications, nFETs require a more detailed design than pFETs. Consequently, this study affords comprehensive insights for optimizing VFETs suitable for various applications.
{"title":"Optimization of Asymmetries in Source/Drain Configurations and Tapered Channels for Vertical-Transport Silicon Nanosheet FETs","authors":"Jinsu Jeong;Sanguk Lee;Rock-Hyun Baek","doi":"10.1109/TED.2024.3496668","DOIUrl":"https://doi.org/10.1109/TED.2024.3496668","url":null,"abstract":"This article presents a thorough investigation of the optimization of asymmetries in vertical-transport nanosheet field-effect transistors (VFETs), considering both asymmetric source/drain (S/D) structures and channel tapering. For asymmetric S/D configurations, n-type FETs (nFETs) exhibit smaller RC delay in the top-source (TopS) configuration, wherein the source has a shorter current path and less voltage drop. Conversely, p-type FETs (pFETs) exhibit smaller RC delay in the bottom-source (BotS) configuration owing to the dominant effect of asymmetric channel stress over the current path difference. Meanwhile, channel tapering significantly affects the optimization of asymmetric VFETs, especially for nFETs. Considering channel tapering, nFET with the smallest RC delay is the BotS configuration, in contrast to the untapered case, whereas BotS configuration is still the optimal structure for pFETs, regardless of the channel tapering. Finally, optimal structures of asymmetric VFETs are presented for various channel widths based on a comparison of the power-delay product (PDP). In nFETs, BotS configuration is optimal for wide channel widths; however, the TopS becomes superior as the channel width decreases in terms of PDP. Meanwhile, optimal structures for pFETs are BotS configurations regardless of the channel tapering and width. For various system-on-chip (SoC) applications, nFETs require a more detailed design than pFETs. Consequently, this study affords comprehensive insights for optimizing VFETs suitable for various applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"75-82"},"PeriodicalIF":2.9,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-19DOI: 10.1109/TED.2024.3492153
Mukul Kumar;Shu-Wei Chang;Chao-Hsin Wu
This study investigates variations in quantum well (QW) width and the influence of temperature on the electrical behavior of quantum well heterojunction bipolar transistors (QW-HBTs), reflecting recent interest in thermal sensor technology. We propose a modified charge control model to accurately predict this temperature-dependent current gain behavior. Through experimental and simulation studies, we show that as temperature rises, carriers stored within the QW gain energy to escape, leading to an increase in current gain. The study systematically investigates the impact of QW width on thermal sensitivity and linearity, revealing an optimal compromise at a QW width of 90 Å, particularly in the temperature range of 25 °C–100 °C. At 100 °C, the thermal sensitivity of a QW width of 90 Å is 1.34 mA/°C, with the fitting linearity parameter B equal to 0.67748. This study offers a best structure design that can be applied for the development of high-performance temperature sensors integrated into optoelectronic integrated circuits (OEICs), promising advancements in temperature sensing technologies.
{"title":"Investigation of Thermal Sensitivity and Linearity of Quantum Well-Based Heterojunction Bipolar Transistor","authors":"Mukul Kumar;Shu-Wei Chang;Chao-Hsin Wu","doi":"10.1109/TED.2024.3492153","DOIUrl":"https://doi.org/10.1109/TED.2024.3492153","url":null,"abstract":"This study investigates variations in quantum well (QW) width and the influence of temperature on the electrical behavior of quantum well heterojunction bipolar transistors (QW-HBTs), reflecting recent interest in thermal sensor technology. We propose a modified charge control model to accurately predict this temperature-dependent current gain behavior. Through experimental and simulation studies, we show that as temperature rises, carriers stored within the QW gain energy to escape, leading to an increase in current gain. The study systematically investigates the impact of QW width on thermal sensitivity and linearity, revealing an optimal compromise at a QW width of 90 Å, particularly in the temperature range of 25 °C–100 °C. At 100 °C, the thermal sensitivity of a QW width of 90 Å is 1.34 mA/°C, with the fitting linearity parameter B equal to 0.67748. This study offers a best structure design that can be applied for the development of high-performance temperature sensors integrated into optoelectronic integrated circuits (OEICs), promising advancements in temperature sensing technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"111-118"},"PeriodicalIF":2.9,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An oscillatory neural network (ONN) is demonstrated by coupling a set of bistable resistor-based oscillators (birillators) through a coupling resistor ( ${R}_{text {C}}$ ). Each birillator is composed of a nonlinear bistable resistor (biristor) and a load resistor ( ${R}_{text {L}}$ ), which are connected in series. The synchronization behavior of oscillations among the resistively coupled birillators varies according to ${R}_{text {C}}$ . When an external sine-wave signal was applied to the resistively coupled birillators, the phase of the oscillations was binarized by second-harmonic injection locking (SHIL). These coupled birillators with SHIL solved combinatorial optimization problems.
{"title":"Resistive Coupling of Bistable Resistor-Based Oscillators for Oscillatory Neural Network","authors":"Seong-Yun Yun;Ye-Seong Chung;Joon-Kyu Han;Sang-Won Lee;Yang-Kyu Choi","doi":"10.1109/TED.2024.3496436","DOIUrl":"https://doi.org/10.1109/TED.2024.3496436","url":null,"abstract":"An oscillatory neural network (ONN) is demonstrated by coupling a set of bistable resistor-based oscillators (birillators) through a coupling resistor (\u0000<inline-formula> <tex-math>${R}_{text {C}}$ </tex-math></inline-formula>\u0000). Each birillator is composed of a nonlinear bistable resistor (biristor) and a load resistor (\u0000<inline-formula> <tex-math>${R}_{text {L}}$ </tex-math></inline-formula>\u0000), which are connected in series. The synchronization behavior of oscillations among the resistively coupled birillators varies according to \u0000<inline-formula> <tex-math>${R}_{text {C}}$ </tex-math></inline-formula>\u0000. When an external sine-wave signal was applied to the resistively coupled birillators, the phase of the oscillations was binarized by second-harmonic injection locking (SHIL). These coupled birillators with SHIL solved combinatorial optimization problems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"494-499"},"PeriodicalIF":2.9,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article introduces a method to mitigate conductance time drift of phase-change memory (PCM) cells for improved resilience of matrix-vector multiplication (MVM) in analog in-memory computing (AIMC) systems. The proposed approach consists of on-chip current-induced annealing of each PCM device to stabilize its conductance at a target level, avoiding any rearrangement of the cell lattice. The procedure is performed within the programming phase of PCM devices with no severe constraints on execution time because of the infrequent update of MVM weights in deep neural networks (DNNs). Experimental validations were conducted on a 90-nm STMicroelectronics CMOS Ge-rich GeSbTe (GST)-embedded PCM targeting 16 conductance levels, and results indicate that the average time drift and variability of cells conductance are reduced by at least a factor of 2.3 and 3.5, respectively, compared with standard programming. Simulations based on empirical results reveal a 0.8% MVM accuracy loss after 12 h at room temperature and 4.8% after an additional 64-h bake at 85 ° C, with a considerable increase in MVM computing retention compared with those granted with standard programming. Accuracy loss is minimized to around 1% even at high temperatures when the proposed method is combined with hardware drift compensation.
{"title":"Controlled Acceleration of PCM Cells Time Drift Through On-Chip Current-Induced Annealing for AIMC Multilevel MVM Computation","authors":"Alessio Antolini;Francesco Zavalloni;Andrea Lico;Riccardo Vignali;Luca Iannelli;Riccardo Zurla;Jacopo Bertolini;Emanuela Calvetti;Marco Pasotti;Eleonora Franchi Scarselli;Alessandro Cabrini","doi":"10.1109/TED.2024.3496445","DOIUrl":"https://doi.org/10.1109/TED.2024.3496445","url":null,"abstract":"This article introduces a method to mitigate conductance time drift of phase-change memory (PCM) cells for improved resilience of matrix-vector multiplication (MVM) in analog in-memory computing (AIMC) systems. The proposed approach consists of on-chip current-induced annealing of each PCM device to stabilize its conductance at a target level, avoiding any rearrangement of the cell lattice. The procedure is performed within the programming phase of PCM devices with no severe constraints on execution time because of the infrequent update of MVM weights in deep neural networks (DNNs). Experimental validations were conducted on a 90-nm STMicroelectronics CMOS Ge-rich GeSbTe (GST)-embedded PCM targeting 16 conductance levels, and results indicate that the average time drift and variability of cells conductance are reduced by at least a factor of 2.3 and 3.5, respectively, compared with standard programming. Simulations based on empirical results reveal a 0.8% MVM accuracy loss after 12 h at room temperature and 4.8% after an additional 64-h bake at 85 ° C, with a considerable increase in MVM computing retention compared with those granted with standard programming. Accuracy loss is minimized to around 1% even at high temperatures when the proposed method is combined with hardware drift compensation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"215-221"},"PeriodicalIF":2.9,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142925443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-19DOI: 10.1109/TED.2024.3496441
Nadim Ahmed;Gourab Dutta
This article presents a novel analytical model for the threshold voltage ( ${V}_{T}$ ) of p-GaN/AlGaN/GaN high-electron-mobility transistors (HEMTs), taking into account the influence of magnesium (Mg)-dopant out-diffusion from the top p-GaN layer into the AlGaN barrier and GaN layer. The proposed model incorporates realistic Mg out-diffusion profiles to accurately estimate ${V}_{T}$ of these normally off devices. Rigorous validation of the analytical model is conducted using experimental data and well-calibrated TCAD simulations, covering a wide range of device parameters and Mg out-diffusion profiles. Furthermore, the model enables the assessment of individual contributions of Mg dopants in the AlGaN and unintentionally doped (UID)-GaN layers. It also facilitates the estimation of the effects of growth duration and temperature of the p-GaN layer on the device’s threshold voltage.
{"title":"Modeling the Impact of Mg Out-Diffusion on Threshold Voltage of p-GaN/AlGaN/GaN HEMT","authors":"Nadim Ahmed;Gourab Dutta","doi":"10.1109/TED.2024.3496441","DOIUrl":"https://doi.org/10.1109/TED.2024.3496441","url":null,"abstract":"This article presents a novel analytical model for the threshold voltage (\u0000<inline-formula> <tex-math>${V}_{T}$ </tex-math></inline-formula>\u0000) of p-GaN/AlGaN/GaN high-electron-mobility transistors (HEMTs), taking into account the influence of magnesium (Mg)-dopant out-diffusion from the top p-GaN layer into the AlGaN barrier and GaN layer. The proposed model incorporates realistic Mg out-diffusion profiles to accurately estimate \u0000<inline-formula> <tex-math>${V}_{T}$ </tex-math></inline-formula>\u0000 of these normally off devices. Rigorous validation of the analytical model is conducted using experimental data and well-calibrated TCAD simulations, covering a wide range of device parameters and Mg out-diffusion profiles. Furthermore, the model enables the assessment of individual contributions of Mg dopants in the AlGaN and unintentionally doped (UID)-GaN layers. It also facilitates the estimation of the effects of growth duration and temperature of the p-GaN layer on the device’s threshold voltage.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 1","pages":"135-141"},"PeriodicalIF":2.9,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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