In this work, by analyzing the properties and dynamics of defects in detail, the role of nitrogen in improving the endurance of ferroelectric field-effect transistors (FeFETs) is clarified. First, the properties of defects (trap energy level ${E}_{text {T}}$ , relaxation energy ${E}_{text {R}}$ , and defect density ${N}_{text {T}}$ ) of FeFETs with SiO2/SiON are investigated in depth through nonradiative multi-phonon (NMP) model. The nitridation process can significantly decrease the population and density of defects in the interfacial layer. Moreover, by comparing the defect dynamics in the interfacial and ferroelectric layers of nitridation/nonnitridation devices during cycling, we find that the nitridation process reduces the charge transition rate of defects and the number of memory window (MW) degradation pathways. The underlying mechanism of the nitridation process that can explain the increase in endurance is revealed. These findings enhance the understanding of reliability concerns in FeFET devices, paving the way for improving the performance of FeFETs.
{"title":"In-Depth Understanding of Nitridation-Induced Endurance Enhancement in FeFETs: Defect Properties and Dynamics Characterized by Nonradiative Multi-Phonon Model","authors":"Yuanquan Huang;Hongye Yuan;Tiancheng Gong;Yuan Wang;Pengfei Jiang;Wei Wei;Yang Yang;Junshuai Chai;Zhicheng Wu;Xiaolei Wang;Qing Luo","doi":"10.1109/TED.2024.3435177","DOIUrl":"10.1109/TED.2024.3435177","url":null,"abstract":"In this work, by analyzing the properties and dynamics of defects in detail, the role of nitrogen in improving the endurance of ferroelectric field-effect transistors (FeFETs) is clarified. First, the properties of defects (trap energy level \u0000<inline-formula> <tex-math>${E}_{text {T}}$ </tex-math></inline-formula>\u0000, relaxation energy \u0000<inline-formula> <tex-math>${E}_{text {R}}$ </tex-math></inline-formula>\u0000, and defect density \u0000<inline-formula> <tex-math>${N}_{text {T}}$ </tex-math></inline-formula>\u0000) of FeFETs with SiO2/SiON are investigated in depth through nonradiative multi-phonon (NMP) model. The nitridation process can significantly decrease the population and density of defects in the interfacial layer. Moreover, by comparing the defect dynamics in the interfacial and ferroelectric layers of nitridation/nonnitridation devices during cycling, we find that the nitridation process reduces the charge transition rate of defects and the number of memory window (MW) degradation pathways. The underlying mechanism of the nitridation process that can explain the increase in endurance is revealed. These findings enhance the understanding of reliability concerns in FeFET devices, paving the way for improving the performance of FeFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-07DOI: 10.1109/TED.2024.3436711
Shaikh S. Ahmed;Ahmad E. Islam;Daniel M. Dryden;Kyle J. Liddy;Nolan S. Hendricks;Neil A. Moser;Kelson D. Chabak;Andrew J. Green
We calculated power figure-of-merit (PFoM) in $beta $ -Ga2O3-based lateral metal-semiconductor field-effect transistors (MESFETs) by simulating the current-voltage (I–V) and breakdown characteristics. Simulation results were benchmarked with the characteristics measured on similar devices. For theoretical analysis, we used atomistic analysis of carrier mobility, self-consistent simulation of electrostatics and carrier transport, and a refined impact ionization model. Our analysis revealed the importance of considering off-state leakage mechanism, 2-D electrostatics, and current conduction pathways for majority and (generated) minority carriers for avalanche breakdown simulation in $beta $ -Ga2O3 lateral MESFETs. This is a significant advancement over the electric field-based approach that is used in literature for breakdown studies. This study also highlights the importance of considering extrinsic breakdown pathways that often limit the observation of avalanche breakdown in these devices.
{"title":"Theoretical Power Figure-of-Merit in β -Ga2O3 Lateral Power Transistors Determined Using Physics-Based TCAD Simulation","authors":"Shaikh S. Ahmed;Ahmad E. Islam;Daniel M. Dryden;Kyle J. Liddy;Nolan S. Hendricks;Neil A. Moser;Kelson D. Chabak;Andrew J. Green","doi":"10.1109/TED.2024.3436711","DOIUrl":"10.1109/TED.2024.3436711","url":null,"abstract":"We calculated power figure-of-merit (PFoM) in \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3-based lateral metal-semiconductor field-effect transistors (MESFETs) by simulating the current-voltage (I–V) and breakdown characteristics. Simulation results were benchmarked with the characteristics measured on similar devices. For theoretical analysis, we used atomistic analysis of carrier mobility, self-consistent simulation of electrostatics and carrier transport, and a refined impact ionization model. Our analysis revealed the importance of considering off-state leakage mechanism, 2-D electrostatics, and current conduction pathways for majority and (generated) minority carriers for avalanche breakdown simulation in \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 lateral MESFETs. This is a significant advancement over the electric field-based approach that is used in literature for breakdown studies. This study also highlights the importance of considering extrinsic breakdown pathways that often limit the observation of avalanche breakdown in these devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/TED.2024.3434775
Ramandeep Kaur;Nihar R. Mohapatra
We explored the performance of p-type nanosheet FETs (NsFETs) with sheet thickness scaling using a well-calibrated subband BTE solver that accounts for quantum confinement. Our investigation revealed that despite enhancements in gate electrostatics, the confined pFETs exhibit significantly reduced hole mobility due to increased phonon and surface roughness scattering (SRS). It is also found that introducing uniaxial compressive stress into the channel with an ideally flat surface (very low surface roughness) could boost the pFET on-current by approximately 2.5 times. Furthermore, by integrating p-type NsFETs on ${ 110}$ substrate, rather than on conventional ${ 100}$ substrate, it is likely to yield superior hole mobility and overall device performance, particularly at scaled sheet thicknesses.
我们利用一个考虑到量子禁锢的校准良好的子带 BTE 求解器，探索了 p 型纳米片 FET（NsFET）在片厚度缩放情况下的性能。我们的研究发现，尽管栅极静电增强，但由于声子和表面粗糙度散射（SRS）增加，禁锢 pFET 的空穴迁移率显著降低。研究还发现，在具有理想平坦表面（表面粗糙度极低）的沟道中引入单轴压应力，可将 pFET 的导通电流提高约 2.5 倍。此外，通过在${ 110}$ 衬底上而不是在传统的${ 100}$ 衬底上集成 p 型 NsFET，有可能产生更优越的空穴迁移率和整体器件性能，特别是在按比例增加片厚的情况下。
{"title":"Exploring Sheet Thickness Scaling and Substrate Orientation for Maximizing Nanosheet pFET Performance","authors":"Ramandeep Kaur;Nihar R. Mohapatra","doi":"10.1109/TED.2024.3434775","DOIUrl":"10.1109/TED.2024.3434775","url":null,"abstract":"We explored the performance of p-type nanosheet FETs (NsFETs) with sheet thickness scaling using a well-calibrated subband BTE solver that accounts for quantum confinement. Our investigation revealed that despite enhancements in gate electrostatics, the confined pFETs exhibit significantly reduced hole mobility due to increased phonon and surface roughness scattering (SRS). It is also found that introducing uniaxial compressive stress into the channel with an ideally flat surface (very low surface roughness) could boost the pFET on-current by approximately 2.5 times. Furthermore, by integrating p-type NsFETs on \u0000<inline-formula> <tex-math>${ 110}$ </tex-math></inline-formula>\u0000 substrate, rather than on conventional \u0000<inline-formula> <tex-math>${ 100}$ </tex-math></inline-formula>\u0000 substrate, it is likely to yield superior hole mobility and overall device performance, particularly at scaled sheet thicknesses.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/TED.2024.3434776
Chia-You Hsieh;Chun-Yu Lin
ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18- $mu $ m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.
集成电路很容易因静电放电（ESD）而损坏，因此集成电路必须采用 ESD 保护电路。在某些应用中，内部电路可能采用全 n 型晶体管设计。在这种情况下，ESD 保护电路应只使用 n 型晶体管，以减少所需的工艺掩膜数量。本研究提出了全 MOS 电源轨 ESD 管钳的基本设计和改进设计。改进设计使用了电流镜电路和 nMOS 串，以分别减少芯片面积和漏电。这些 ESD 保护电路已在 0.18 英寸 CMOS 工艺中实现并通过验证。所提出的设计具有成本效益，并能为实际应用提供更高的 ESD 鲁棒性。
{"title":"All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage","authors":"Chia-You Hsieh;Chun-Yu Lin","doi":"10.1109/TED.2024.3434776","DOIUrl":"10.1109/TED.2024.3434776","url":null,"abstract":"ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, the degradation behaviors for large size amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under realistic waveforms in active driving circuit are revealed, and the corresponding degradation mechanisms are analyzed. When the back half of the drain pulse overlaps with the first half of the gate pulse (forward overlap), self-heating effect becomes the key factor for positive threshold voltage shift. When the front half of the drain pulse overlaps with the back half of the gate pulse (backward overlap), hot carrier effect takes the dominating role over self-heating. Under this circumstance, hot carrier effect could generate deep states, which are hard to recover, causing both positive voltage shift and ON-current deterioration. However, slightly increasing the pulse frequency leads to self-heating effect taking over again in backward overlap. To understand this phenomenon, a competition model between self-heating and hot carrier effect is proposed, which indicates the significant role played by the large W/L ratio of the a-IGZO driving transistor. The model might be suitable for degradation analysis of a-IGZO TFTs in gate driven on array (GOA) driving circuits application.
{"title":"Asymmetry Degradation Behavior Under Forward and Backward Overlap Dynamical Stress in Large-Size Amorphous InGaZnO TFT","authors":"Ruohong Duan;Zhixiang Zou;Zhong Xu;Haoxiong Zhang;Xibin Shao;Deming Zhang;Zhangtao Wang;Lang Zeng","doi":"10.1109/TED.2024.3435174","DOIUrl":"10.1109/TED.2024.3435174","url":null,"abstract":"In this work, the degradation behaviors for large size amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under realistic waveforms in active driving circuit are revealed, and the corresponding degradation mechanisms are analyzed. When the back half of the drain pulse overlaps with the first half of the gate pulse (forward overlap), self-heating effect becomes the key factor for positive threshold voltage shift. When the front half of the drain pulse overlaps with the back half of the gate pulse (backward overlap), hot carrier effect takes the dominating role over self-heating. Under this circumstance, hot carrier effect could generate deep states, which are hard to recover, causing both positive voltage shift and ON-current deterioration. However, slightly increasing the pulse frequency leads to self-heating effect taking over again in backward overlap. To understand this phenomenon, a competition model between self-heating and hot carrier effect is proposed, which indicates the significant role played by the large W/L ratio of the a-IGZO driving transistor. The model might be suitable for degradation analysis of a-IGZO TFTs in gate driven on array (GOA) driving circuits application.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/TED.2024.3435810
Ahmed Shaban;Shreshtha Gothalyan;Tuo-Hung Hou;Manan Suri
Binary neural networks (BNNs) are a highly promising option for realizing lightweight and efficient computing for applications on the edge. Spin-orbit torque MRAM (SOT-MRAM) has emerged as an attractive option for realizing fast and energy-efficient design. In this work, we propose a 4T-2R memory cell using viable and experimentally demonstrated SOT magnetic tunnel junction device (SOT-MTJ) for realizing highly energy-efficient XNOR operation (primary operation in BNNs). We also propose a pulse scheme to mitigate the inherent challenge of increased write error rate (WER) in SOT-MRAM device while achieving energy-efficient write. We perform 1000-point Monte Carlo (MC) simulations and demonstrate a bit error rate (BER) of 0.1– $5times {10}^{-{3}}$ with extremely low energy consumption of ~4.8 fJ per XNOR operation. We also perform system-level simulations to show robustness of our cell by incorporating the asymmetric BERs resulting due to thermal noise and process variations (PVs) on CIFAR-10 classification task using VGG network. Our proposed cell holds potential for highly energy-efficient and error-tolerant BNNs on edge devices.
{"title":"SOT-MRAM-Based Design for Energy-Efficient and Reliable Binary Neural Network Acceleration","authors":"Ahmed Shaban;Shreshtha Gothalyan;Tuo-Hung Hou;Manan Suri","doi":"10.1109/TED.2024.3435810","DOIUrl":"10.1109/TED.2024.3435810","url":null,"abstract":"Binary neural networks (BNNs) are a highly promising option for realizing lightweight and efficient computing for applications on the edge. Spin-orbit torque MRAM (SOT-MRAM) has emerged as an attractive option for realizing fast and energy-efficient design. In this work, we propose a 4T-2R memory cell using viable and experimentally demonstrated SOT magnetic tunnel junction device (SOT-MTJ) for realizing highly energy-efficient XNOR operation (primary operation in BNNs). We also propose a pulse scheme to mitigate the inherent challenge of increased write error rate (WER) in SOT-MRAM device while achieving energy-efficient write. We perform 1000-point Monte Carlo (MC) simulations and demonstrate a bit error rate (BER) of 0.1–\u0000<inline-formula> <tex-math>$5times {10}^{-{3}}$ </tex-math></inline-formula>\u0000 with extremely low energy consumption of ~4.8 fJ per XNOR operation. We also perform system-level simulations to show robustness of our cell by incorporating the asymmetric BERs resulting due to thermal noise and process variations (PVs) on CIFAR-10 classification task using VGG network. Our proposed cell holds potential for highly energy-efficient and error-tolerant BNNs on edge devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141969182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the capacity to separate electron-hole pairs under zero bias, the heterojunction photodetectors (PDs) can operate in self-powered manner, while it remains a challenge to maintain high self-powered photodetection performance at an elevated temperature. Herein, a hybrid $varepsilon $ -Ga2O3/PEDOT:PSS heterojunction deep ultraviolet (UV) PD was fabricated via the spin-coating method. The designed PD showed excellent signal-to-noise-ratio at room temperature (RT) with a dark current of 35 fA and photocurrent of 55 nA under zero bias. Even at the temperature of $150~^{circ }$ C, the PD could still maintain high photograph to a dark current ratio (PDCR) of $1times 10^{{5}}$ and decent responsivity of 1.8 mA/W. As the temperature rising, the dark current of the constructed hybrid heterojunction increased while the photocurrent decreased, which were possibly caused by the enhancement of thermal excitation and the recombination of electron-hole pairs. The outstanding self-powered photoelectrical properties performed at high temperature reveal the great potential of $varepsilon $ -Ga2O3/PEDOT:PSS heterojunction PDs for future low-power harsh environment photodetection.
{"title":"Temperature Dependence of Self-Powered Photodetection Performance in Hybrid ε -Ga2O3/PEDOT:PSS Heterojunction","authors":"Jia-Qi Lu;Ji-Peng Wang;Chang Zhou;Shuo-Shuo Yin;Wan-Yu Ma;Shan Li;Wei-Hua Tang","doi":"10.1109/TED.2024.3436001","DOIUrl":"10.1109/TED.2024.3436001","url":null,"abstract":"With the capacity to separate electron-hole pairs under zero bias, the heterojunction photodetectors (PDs) can operate in self-powered manner, while it remains a challenge to maintain high self-powered photodetection performance at an elevated temperature. Herein, a hybrid \u0000<inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>\u0000-Ga2O3/PEDOT:PSS heterojunction deep ultraviolet (UV) PD was fabricated via the spin-coating method. The designed PD showed excellent signal-to-noise-ratio at room temperature (RT) with a dark current of 35 fA and photocurrent of 55 nA under zero bias. Even at the temperature of \u0000<inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>\u0000C, the PD could still maintain high photograph to a dark current ratio (PDCR) of \u0000<inline-formula> <tex-math>$1times 10^{{5}}$ </tex-math></inline-formula>\u0000 and decent responsivity of 1.8 mA/W. As the temperature rising, the dark current of the constructed hybrid heterojunction increased while the photocurrent decreased, which were possibly caused by the enhancement of thermal excitation and the recombination of electron-hole pairs. The outstanding self-powered photoelectrical properties performed at high temperature reveal the great potential of \u0000<inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula>\u0000-Ga2O3/PEDOT:PSS heterojunction PDs for future low-power harsh environment photodetection.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/TED.2024.3435182
Lin Luo;Linlin Xu;Jiuzhou Zhao;Renli Liang;Zhengchen Li;Yang Peng;Xinzhong Wang;Jiangnan Dai;Mingxiang Chen
Deep-ultraviolet light-emitting diodes (DUV-LEDs) represent a new generation of ultraviolet light sources with applications in sterilization, medical health, and biological detection. However, the traditional organic packaging is unable to meet the rigorous requirements of highly reliable high-power DUV-LEDs. In this work, an all-inorganic hermetic packaging solution based on laser localized heating and welding was developed for high-power DUV-LEDs. The parameters of laser localized welding were optimized to obtain a high-strength, crack-free welded joint. In the transition welding mode, the packaging cavity displays excellent gas tightness with a leakage rate of $1.25times 10^{-{9}}~text {Pa}cdot text {m}^{{3}}$ /s and the welded joint achieves high shear strength of 184.8 MPa. At a driving current of 350 mA, the voltage and light output power (LOP) of the packaged DUV-LED are 6.172 V and 60.44 mW, respectively. After the accelerated aging test for 250 h, the LOP of hermetic packaged DUV-LED exhibited a mere 3.24% reduction, in contrast to the 31.76% and 41.18% declines in traditional semi-inorganic packaged and unpackaged DUV-LEDs, respectively. Our work provides a meaningful guidance and solution for the highly reliable and board-level packaging of DUV-LEDs.
{"title":"All-Inorganic Hermetic Packaging of Deep-Ultraviolet Light-Emitting Diodes Through Laser Localized Heating and Welding","authors":"Lin Luo;Linlin Xu;Jiuzhou Zhao;Renli Liang;Zhengchen Li;Yang Peng;Xinzhong Wang;Jiangnan Dai;Mingxiang Chen","doi":"10.1109/TED.2024.3435182","DOIUrl":"10.1109/TED.2024.3435182","url":null,"abstract":"Deep-ultraviolet light-emitting diodes (DUV-LEDs) represent a new generation of ultraviolet light sources with applications in sterilization, medical health, and biological detection. However, the traditional organic packaging is unable to meet the rigorous requirements of highly reliable high-power DUV-LEDs. In this work, an all-inorganic hermetic packaging solution based on laser localized heating and welding was developed for high-power DUV-LEDs. The parameters of laser localized welding were optimized to obtain a high-strength, crack-free welded joint. In the transition welding mode, the packaging cavity displays excellent gas tightness with a leakage rate of \u0000<inline-formula> <tex-math>$1.25times 10^{-{9}}~text {Pa}cdot text {m}^{{3}}$ </tex-math></inline-formula>\u0000/s and the welded joint achieves high shear strength of 184.8 MPa. At a driving current of 350 mA, the voltage and light output power (LOP) of the packaged DUV-LED are 6.172 V and 60.44 mW, respectively. After the accelerated aging test for 250 h, the LOP of hermetic packaged DUV-LED exhibited a mere 3.24% reduction, in contrast to the 31.76% and 41.18% declines in traditional semi-inorganic packaged and unpackaged DUV-LEDs, respectively. Our work provides a meaningful guidance and solution for the highly reliable and board-level packaging of DUV-LEDs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-05DOI: 10.1109/TED.2024.3435179
Yanqin Zhang;Xufan Li;Jianwei Zhang;Zhenzhong Yang;Jiawei Wang;Lingfei Wang;Mengmeng Li;Ling Li;Ming Liu
We report high-performance amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs), in which both rectangular and circular architectures are utilized. In comparison to the commonly used rectangular design, the circular architecture is capable of significantly improving the device-to-device uniformity without obvious deterioration in transistor performance, and the ratio of standard deviation to mean value (variation coefficient) is only 1.29% for threshold voltage ( ${V}_{text {TH}}$ ), 1.12% for maximum width-normalized transconductance ( ${G}_{text {m,max}}$ ), and 0.93% for linear electron mobility ( $mu _{text {e}}$ ), among the uniformity records for a-IGZO TFTs. Furthermore, simulations show a good agreement with experimental data and demonstrate that the improvement in device-to-device uniformity of circular architecture originates from the elimination of edge conduction paths compared to rectangular layout.
{"title":"Circular Architecture for Excellent Uniformity in Amorphous Indium–Gallium–Zinc-Oxide Thin-Film Transistors","authors":"Yanqin Zhang;Xufan Li;Jianwei Zhang;Zhenzhong Yang;Jiawei Wang;Lingfei Wang;Mengmeng Li;Ling Li;Ming Liu","doi":"10.1109/TED.2024.3435179","DOIUrl":"10.1109/TED.2024.3435179","url":null,"abstract":"We report high-performance amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs), in which both rectangular and circular architectures are utilized. In comparison to the commonly used rectangular design, the circular architecture is capable of significantly improving the device-to-device uniformity without obvious deterioration in transistor performance, and the ratio of standard deviation to mean value (variation coefficient) is only 1.29% for threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000), 1.12% for maximum width-normalized transconductance (\u0000<inline-formula> <tex-math>${G}_{text {m,max}}$ </tex-math></inline-formula>\u0000), and 0.93% for linear electron mobility (\u0000<inline-formula> <tex-math>$mu _{text {e}}$ </tex-math></inline-formula>\u0000), among the uniformity records for a-IGZO TFTs. Furthermore, simulations show a good agreement with experimental data and demonstrate that the improvement in device-to-device uniformity of circular architecture originates from the elimination of edge conduction paths compared to rectangular layout.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10623600","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To improve the thermal stability of indium-gallium-zinc-oxide (IGZO) field-effect transistors (FETs) in the oxygen-deficient environment, we examined the different annealing schemes with temperatures up to 450 °C. Our study revealed that the performance of IGZO FETs is not solely affected by the annealing temperature but also strongly influenced by the cooling scheme. Oxygen vacancies (V $_{text {O}}text {)}$ generated at high temperatures can remain at a high concentration, while VO can be gradually reduced with the slow cooling scheme. Additionally, we analyzed the impacts of downscaling the channel thickness (t $_{text {ch}}text {)}$ on the thermal stability of IGZO FETs, observing that a thin IGZO channel leads to the positive threshold voltage (V $_{text {th}}text {)}$ but suffers from more severe degradation in electrical performance and reliability. Based on the slow cooling scheme and proper selection of tch, a near-zero Vth and a relatively low subthreshold swing (SS) of 150 mV/dec of IGZO FETs with a channel length scaled to 100 nm are achieved after undergoing a high annealing temperature of 450 °C. Our discovery brings new possibilities for device fabrication and optimization for the advanced IGZO FETs.
{"title":"Discovering the Impact of Cooling Scheme During Annealing: A New Knob for Achieving Thermally Stable IGZO FETs","authors":"Qiwen Kong;Long Liu;Kaizhen Han;Chen Sun;Leming Jiao;Zuopu Zhou;Zijie Zheng;Gan Liu;Haiwen Xu;Jishen Zhang;Yue Chen;Xiao Gong","doi":"10.1109/TED.2024.3433832","DOIUrl":"10.1109/TED.2024.3433832","url":null,"abstract":"To improve the thermal stability of indium-gallium-zinc-oxide (IGZO) field-effect transistors (FETs) in the oxygen-deficient environment, we examined the different annealing schemes with temperatures up to 450 °C. Our study revealed that the performance of IGZO FETs is not solely affected by the annealing temperature but also strongly influenced by the cooling scheme. Oxygen vacancies (V\u0000<inline-formula> <tex-math>$_{text {O}}text {)}$ </tex-math></inline-formula>\u0000 generated at high temperatures can remain at a high concentration, while VO can be gradually reduced with the slow cooling scheme. Additionally, we analyzed the impacts of downscaling the channel thickness (t\u0000<inline-formula> <tex-math>$_{text {ch}}text {)}$ </tex-math></inline-formula>\u0000 on the thermal stability of IGZO FETs, observing that a thin IGZO channel leads to the positive threshold voltage (V\u0000<inline-formula> <tex-math>$_{text {th}}text {)}$ </tex-math></inline-formula>\u0000 but suffers from more severe degradation in electrical performance and reliability. Based on the slow cooling scheme and proper selection of tch, a near-zero Vth and a relatively low subthreshold swing (SS) of 150 mV/dec of IGZO FETs with a channel length scaled to 100 nm are achieved after undergoing a high annealing temperature of 450 °C. Our discovery brings new possibilities for device fabrication and optimization for the advanced IGZO FETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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